coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74710 to look at the new patch set (#2). Change subject: include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb ...................................................................... include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in line with get_top_of_mem_below_4gb. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 --- M src/include/cpu/amd/mtrr.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/74710/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Gerrit-Change-Number: 74710 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74657 ) Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers ...................................................................... soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74657 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/phoenix/xhci.c 1 file changed, 37 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c index 8bb446f..99033f9 100644 --- a/src/soc/amd/phoenix/xhci.c +++ b/src/soc/amd/phoenix/xhci.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #include <amdblocks/gpio.h> #include <amdblocks/smi.h> #include <amdblocks/xhci.h> @@ -24,6 +22,18 @@ .gpe = XHCI_GEVENT, .direction = SMI_SCI_LVL_HIGH, .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC3_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC4_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG } }; @@ -45,6 +55,16 @@ } } + if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { + if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) { + *gpe = xhci_sci_sources[2].gpe; + return CB_SUCCESS; + } else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) { + *gpe = xhci_sci_sources[3].gpe; + return CB_SUCCESS; + } + } + return CB_ERR_ARG; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95916e409b3fbd4941a861054733a34100244da9 Gerrit-Change-Number: 74657 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74656 ) Change subject: soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN ...................................................................... soc/amd/*/include/pci_devs: fix copy-paste error in PCIE_ABC_C_DEVFN Since it's an internal bus, it's PCIE_ABC_C_DEVFN and not PCIE_GPP_C_DEVFN. This also makes it consistent with the rest of the internal PCI buses. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74656 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/include/soc/pci_devs.h M src/soc/amd/glinda/include/soc/pci_devs.h M src/soc/amd/glinda/xhci.c M src/soc/amd/mendocino/include/soc/pci_devs.h M src/soc/amd/mendocino/xhci.c M src/soc/amd/phoenix/include/soc/pci_devs.h 6 files changed, 25 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/pci_devs.h b/src/soc/amd/cezanne/include/soc/pci_devs.h index 8f5793b..2337e0c 100644 --- a/src/soc/amd/cezanne/include/soc/pci_devs.h +++ b/src/soc/amd/cezanne/include/soc/pci_devs.h @@ -108,7 +108,7 @@ #define SATA1_DEVFN PCI_DEVFN(SATA1_DEV, SATA1_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) /* SMBUS */ diff --git a/src/soc/amd/glinda/include/soc/pci_devs.h b/src/soc/amd/glinda/include/soc/pci_devs.h index 4e0bf9d..a37d3ee 100644 --- a/src/soc/amd/glinda/include/soc/pci_devs.h +++ b/src/soc/amd/glinda/include/soc/pci_devs.h @@ -86,7 +86,7 @@ #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define XHCI2_DEV 0x0 diff --git a/src/soc/amd/glinda/xhci.c b/src/soc/amd/glinda/xhci.c index 78ca94f..dad5593 100644 --- a/src/soc/amd/glinda/xhci.c +++ b/src/soc/amd/glinda/xhci.c @@ -48,7 +48,7 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { + } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/mendocino/include/soc/pci_devs.h b/src/soc/amd/mendocino/include/soc/pci_devs.h index 14c8300..2c81a5b 100644 --- a/src/soc/amd/mendocino/include/soc/pci_devs.h +++ b/src/soc/amd/mendocino/include/soc/pci_devs.h @@ -84,7 +84,7 @@ #define SOC_PCIE_GPP_B_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_B_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define XHCI2_DEV 0x0 diff --git a/src/soc/amd/mendocino/xhci.c b/src/soc/amd/mendocino/xhci.c index 720cc76..e564991 100644 --- a/src/soc/amd/mendocino/xhci.c +++ b/src/soc/amd/mendocino/xhci.c @@ -49,7 +49,7 @@ *gpe = xhci_sci_sources[1].gpe; return CB_SUCCESS; } - } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) { + } else if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) { if (dev->path.pci.devfn == XHCI2_DEVFN && dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) { *gpe = xhci_sci_sources[2].gpe; diff --git a/src/soc/amd/phoenix/include/soc/pci_devs.h b/src/soc/amd/phoenix/include/soc/pci_devs.h index 0dde0ba..cd7ad08 100644 --- a/src/soc/amd/phoenix/include/soc/pci_devs.h +++ b/src/soc/amd/phoenix/include/soc/pci_devs.h @@ -104,7 +104,7 @@ #define GFX_IPU_DEVFN PCI_DEVFN(GFX_IPU_DEV, GFX_IPU_FUNC) #define PCIE_ABC_C_FUNC 3 -#define PCIE_GPP_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) +#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC) #define USB4_XHCI0_DEV 0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica8b666161c3cd3b0b4a29f8a4b0aff473b4d833 Gerrit-Change-Number: 74656 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74655 ) Change subject: soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63 ...................................................................... soc/amd/phoenix/include/soc/smi: add missing SCI map defines 61-63 In the PPRs #57019 Rev 3.03 and #57396 Rev 3.04, SMITYPE_XHC3_PME, SMITYPE_XHC4_PME and SMITYPE_CUR_TEMP_STATUS_5 are defined, so add those defines. When doing the initial update for Phoenix, at least XHC3 and XHC4 PME events were missing from the PPR. Those two are the PME events of the two USB4 controllers. SMITYPE_XHC2_PME doesn't exist on this SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74655 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/phoenix/include/soc/smi.h 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/phoenix/include/soc/smi.h b/src/soc/amd/phoenix/include/soc/smi.h index 034a327..e99b172 100644 --- a/src/soc/amd/phoenix/include/soc/smi.h +++ b/src/soc/amd/phoenix/include/soc/smi.h @@ -102,7 +102,10 @@ #define SMITYPE_XHC0_PME 56 #define SMITYPE_XHC1_PME 57 #define SMITYPE_ACDC_TIMER 58 -/* 59-63 Reserved */ +/* 59-60 Reserved */ +#define SMITYPE_XHC3_PME 61 +#define SMITYPE_XHC4_PME 62 +#define SMITYPE_CUR_TEMP_STATUS_5 63 #define SMITYPE_KB_RESET 64 #define SMITYPE_SLP_TYP 65 #define SMITYPE_AL2H_ACPI 66 -- To view, visit https://review.coreboot.org/c/coreboot/+/74655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6fff9175b73cc9d0fd324d4a568a5761b92d078 Gerrit-Change-Number: 74655 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74659 ) Change subject: cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c ...................................................................... cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c Now that the code is in a much better shape and uses native coreboot functionality to perform the initialization, rename the file from fixme.c to cpu_io_init.c to be more descriptive of what it does. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I97d1ac2b12c624210c570f189f825409bd64f318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74659 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/pi/00730F01/Makefile.inc R src/cpu/amd/pi/00730F01/cpu_io_init.c 2 files changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 51f90ef..ae5a20b 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -romstage-y += fixme.c +romstage-y += cpu_io_init.c -ramstage-y += fixme.c ramstage-y += chip_name.c +ramstage-y += cpu_io_init.c ramstage-y += model_16_init.c ramstage-y += update_microcode.c diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/cpu_io_init.c similarity index 100% rename from src/cpu/amd/pi/00730F01/fixme.c rename to src/cpu/amd/pi/00730F01/cpu_io_init.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97d1ac2b12c624210c570f189f825409bd64f318 Gerrit-Change-Number: 74659 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Jon Murphy (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74607 ) Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74607/comment/3c6c6fa0_216bb4d0 PS1, Line 3: #include <variant/gpio.h> > Not sure why include order matters. Ideally it should not be. Agree, I can circle back, just trying to get the initial functionality up for review -- To view, visit https://review.coreboot.org/c/coreboot/+/74607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a8f7e5bfa9e3e586d4189132f47551202f7d2d Gerrit-Change-Number: 74607 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Sat, 22 Apr 2023 15:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb
by Fred Reitberger (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74710 ) Change subject: include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74710/comment/8426fffe_211846de PS1, Line 9: 'g' nit: 'b' -- To view, visit https://review.coreboot.org/c/coreboot/+/74710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Gerrit-Change-Number: 74710 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 22 Apr 2023 14:36:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static
by Subrata Banik (Code Review) 22 Apr '23

22 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74388 ) Change subject: soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static ...................................................................... soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function static The patch makes `cse_get_fpt_partition_info()` AP local/static as all the references to this function are in local to the cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74388 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 24 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Sridhar Siricilla: Looks good to me, approved Kangheui Won: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4cc4f51..d6c8347 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1220,7 +1220,8 @@ return CB_SUCCESS; } -enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, struct fw_version_resp *resp) +static enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, + struct fw_version_resp *resp) { if (vboot_recovery_mode_enabled()) { printk(BIOS_WARNING, diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f3a7f83..c893846 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -561,10 +561,4 @@ */ enum cb_err cse_get_fw_feature_state(uint32_t *feature_state); -/* - * The function sends a HECI command to get the partition information of the shared ID. - * The retrieved partition is stored in the memory pointed to by the resp pointer. - * The function returns 0 on success and < 0 on failure. - */ -enum cb_err cse_get_fpt_partition_info(enum fpt_partition_id id, struct fw_version_resp *resp); #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/74388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Gerrit-Change-Number: 74388 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya: Enable CSE FPT Info config for Nissa
by Subrata Banik (Code Review) 22 Apr '23

22 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74387 ) Change subject: mb/google/brya: Enable CSE FPT Info config for Nissa ...................................................................... mb/google/brya: Enable CSE FPT Info config for Nissa Google Brya variants like Nissa family selects `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT information. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74387 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Kangheui Won: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9aa3254..eb1790e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -85,6 +85,7 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE + select SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 select SOC_INTEL_COMMON_MMC_OVERRIDE -- To view, visit https://review.coreboot.org/c/coreboot/+/74387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c Gerrit-Change-Number: 74387 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override
by Subrata Banik (Code Review) 22 Apr '23

22 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74532 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override ...................................................................... soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command. TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/marasov. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532 Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/chip.c 1 file changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 7cdeb7c..f052279 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -162,6 +162,26 @@ } #endif +#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) +/* + * SoC override API to identify if ISH Firmware existed inside CSE FPT. + * + * SoC with UFS enabled would like to keep ISH enabled as well, hence + * identifying the UFS enabled device is enough to conclude that the ISH + * partition also is available. + */ +bool soc_is_ish_partition_enabled(void) +{ + struct device *ufs = pcidev_path_on_root(PCH_DEVFN_UFS); + uint16_t ufs_pci_id = ufs ? pci_read_config16(ufs, PCI_DEVICE_ID) : 0xFFFF; + + if (ufs_pci_id == 0xFFFF) + return false; + + return true; +} +#endif + /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Gerrit-Change-Number: 74532 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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