coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Generate SPD ID for supported memory part
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74586 ) Change subject: mb/google/dedede/var/boxy: Generate SPD ID for supported memory part ...................................................................... mb/google/dedede/var/boxy: Generate SPD ID for supported memory part Add boxy supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 3. Micron MT53E512M32D1NP-046 WT:B BUG=b:278983561 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang(a)lcfc.corp-partner.google.com> Change-Id: I317f2b31774627706babdea10776af05ab692d1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc M src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt 3 files changed, 39 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc b/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc index eace2e4..fa024d4 100644 --- a/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boxy/memory/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/boxy/memory/ src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B diff --git a/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt index fa24790..52ffb42 100644 --- a/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/boxy/memory/dram_id.generated.txt @@ -1 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/boxy/memory/ src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K4U6E3S4AB-MGCL 0 (0000) +H54G46CYRBX267 0 (0000) +MT53E512M32D1NP-046 WT:B 0 (0000) diff --git a/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt index 9621137..f971a01 100644 --- a/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/boxy/memory/mem_parts_used.txt @@ -9,3 +9,6 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K4U6E3S4AB-MGCL +H54G46CYRBX267 +MT53E512M32D1NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/74586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317f2b31774627706babdea10776af05ab692d1e Gerrit-Change-Number: 74586 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74584 ) Change subject: mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks ...................................................................... mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks Yavilla board memory id setting references to yaviks. This CL aligen it with yaviks. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) H58G56BK7BX068 3 (0011) MT62F1G32D2DS-026 WT:B 3 (0011) K3KL8L80CM-MGCT 3 (0011) H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc M src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt 3 files changed, 54 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Kevin Chiu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc index a0e6c21..82e3814 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc @@ -5,5 +5,8 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT -SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 5(0b0101) Parts = H58G66AK6BX070 diff --git a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt index 598edff..425762c 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt @@ -5,10 +5,14 @@ DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) -H58G56BK7BX068 1 (0001) -MT62F1G32D2DS-026 WT:B 1 (0001) -K3KL8L80CM-MGCT 1 (0001) -H58G66BK7BX067 2 (0010) -MT62F2G32D4DS-026 WT:B 2 (0010) -K3KL9L90CM-MGCT 2 (0010) +H58G56AK6BX069 2 (0010) +K3LKBKB0BM-MGCP 2 (0010) +H58G56BK7BX068 3 (0011) +MT62F1G32D2DS-026 WT:B 3 (0011) +K3KL8L80CM-MGCT 3 (0011) +H58G66BK7BX067 4 (0100) +MT62F2G32D4DS-026 WT:B 4 (0100) +K3KL9L90CM-MGCT 4 (0100) +H58G66AK6BX070 5 (0101) diff --git a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt index 5ef4186..607026b 100644 --- a/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt @@ -10,10 +10,14 @@ # Part Name MT62F512M32D2DR-031 WT:B +MT62F1G32D4DR-031 WT:B H9JCNNNBK3MLYR-N6E +H58G56AK6BX069 +K3LKBKB0BM-MGCP H58G56BK7BX068 MT62F1G32D2DS-026 WT:B K3KL8L80CM-MGCT H58G66BK7BX067 MT62F2G32D4DS-026 WT:B K3KL9L90CM-MGCT +H58G66AK6BX070 -- To view, visit https://review.coreboot.org/c/coreboot/+/74584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Gerrit-Change-Number: 74584 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/variants/hades: Swap LAN and SD Card PCIE Ports
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74630 ) Change subject: mb/google/brya/variants/hades: Swap LAN and SD Card PCIE Ports ...................................................................... mb/google/brya/variants/hades: Swap LAN and SD Card PCIE Ports To aid in layout, the PCI ports for LAN and SD card were swapped. SD Card is now on RP3 (clksrc 4) LAN is now on RP8 (clksrc 3) BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/hades/overridetree.cb 1 file changed, 40 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index 9c9171c..1412a1f 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -211,10 +211,27 @@ end end device ref pcie_rp3 on - # Enable PCIE 3 using clk 4 + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + # Enable SD Card PCIE 3 using clk 4 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 SD card + device ref pcie_rp4 off end + device ref pcie_rp6 off end + device ref pcie_rp7 off end + device ref pcie_rp8 on + # Enable PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip drivers/net @@ -225,23 +242,6 @@ device pci 00.0 on end end end #RTL8111H Ethernet NIC - device ref pcie_rp4 off end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 on - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" - register "srcclk_pin" = "3" - device generic 0 on end - end - # Enable SD Card PCIE 8 using clk 3 - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE8 SD card device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 register "pch_pcie_rp[PCH_RP(9)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/74630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb Gerrit-Change-Number: 74630 Gerrit-PatchSet: 6 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteoerlake: set power limits dynamically
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74380 ) Change subject: soc/intel/meteoerlake: set power limits dynamically ...................................................................... soc/intel/meteoerlake: set power limits dynamically Set power limit values dynamically based on Meteor Lake CPU TDP and PCI ID of SKU. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/systemagent.c 3 files changed, 83 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 2537013..d87a67c 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <device/pci_ids.h> #include <gpio.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> @@ -19,13 +20,24 @@ /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { - MTL_P_POWER_LIMITS_1, - MTL_P_POWER_LIMITS_2, - MTL_P_POWER_LIMITS_3, - MTL_P_POWER_LIMITS_4, + MTL_P_282_CORE, MTL_POWER_LIMITS_COUNT }; +/* TDP values for different SKUs */ +enum soc_intel_meteorlake_cpu_tdps { + TDP_15W = 15 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int cpu_id; + enum soc_intel_meteorlake_power_limits limits; + enum soc_intel_meteorlake_cpu_tdps cpu_tdp; +} cpuid_to_mtl[] = { + { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_CORE, TDP_15W }, +}; + /* Types of display ports */ enum ddi_ports { DDI_PORT_A, diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 3af284c..57d1205 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -2,15 +2,10 @@ device cpu_cluster 0 on end - #FIXME: update values for MTL and enable override in systemagent.c - register "power_limits_config[MTL_P_POWER_LIMITS_2]" = "{ + register "power_limits_config[MTL_P_282_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - }" - - register "power_limits_config[MTL_P_POWER_LIMITS_1]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 115, + .tdp_pl2_override = 57, + .tdp_pl4 = 114, }" # NOTE: if any variant wants to override this value, use the same format diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 81e4bed..875ddcc 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -5,7 +5,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> @@ -145,52 +144,64 @@ sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count); } -/* - * SoC implementation - * - * Perform System Agent Initialization during Ramstage phase. - */ -void soc_systemagent_init(struct device *dev) +static void configure_tdp(struct device *dev) { struct soc_power_limits_config *soc_config; struct device *sa; uint16_t sa_pci_id; + u8 tdp; + size_t i; + bool config_tdp = false; config_t *config; - /* Enable Power Aware Interrupt Routing */ - enable_power_aware_intr(); - config = config_of_soc(); /* Get System Agent PCI ID */ sa = pcidev_path_on_root(PCI_DEVFN_ROOT); sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; - /* Choose a power limits configuration based on the SoC SKU type, - * differentiated here based on SA PCI ID. */ - switch (sa_pci_id) { - case PCI_DID_INTEL_MTL_P_ID_1: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_1]; - break; - case PCI_DID_INTEL_MTL_P_ID_2: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_2]; - break; - case PCI_DID_INTEL_MTL_P_ID_3: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_3]; - break; - case PCI_DID_INTEL_MTL_P_ID_4: - soc_config = &config->power_limits_config[MTL_P_POWER_LIMITS_4]; - break; - default: - printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipping power limits configuration\n", - sa_pci_id); + if (sa_pci_id == 0xFFFF) { + printk(BIOS_WARNING, "Unknown SA PCI Device!\n"); return; } - /* Remove once commented line below is enabled */ - (void)soc_config; - /* UPDATEME: Need to enable later */ - //set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + tdp = get_cpu_tdp(); + + /* + * Choose power limits configuration based on the CPU SA PCI ID and + * CPU TDP value. + */ + for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) { + if (sa_pci_id == cpuid_to_mtl[i].cpu_id && + tdp == cpuid_to_mtl[i].cpu_tdp) { + soc_config = &config->power_limits_config[cpuid_to_mtl[i].limits]; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + config_tdp = true; + printk(BIOS_DEBUG, "Configured power limits for SA PCI ID: 0x%4x\n", + sa_pci_id); + break; + } + } + + if (!config_tdp) { + printk(BIOS_WARNING, "Skipped power limits configuration for SA PCI ID: 0x%4x\n", + sa_pci_id); + return; + } +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Configure TDP */ + configure_tdp(dev); } uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz) -- To view, visit https://review.coreboot.org/c/coreboot/+/74380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Gerrit-Change-Number: 74380 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74627 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating ...................................................................... mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index dca4333..075acf8 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -85,6 +85,11 @@ .v1p05_icc_max_ma = 500, .vnn_sx_voltage_mv = 1250, }" + + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/74627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Gerrit-Change-Number: 74627 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/corsola: Rename common config from `STARMIE` to `STARYU`
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74654 ) Change subject: mb/google/corsola: Rename common config from `STARMIE` to `STARYU` ...................................................................... mb/google/corsola: Rename common config from `STARMIE` to `STARYU` The STARYU is the mt8186 detachable reference design, and the STARMIE is a variant of STARYU. Let's rename the common config from STARMIE to STARYU, and we can select the STARYU config for the follow up mt8186 detachable variant. BRANCH=corsola BUG=b:275470328 TEST=./utils/abuild/abuild -t google/corsola -a Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74654 Reviewed-by: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 27 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve cong yang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 3bb43bc..6e8c81e 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -12,7 +12,7 @@ def_bool n select BOARD_GOOGLE_CORSOLA_COMMON -config BOARD_GOOGLE_STARMIE_COMMON +config BOARD_GOOGLE_STARYU_COMMON def_bool n select BOARD_GOOGLE_CORSOLA_COMMON diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index 90f3b48..5d6021d 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -26,8 +26,8 @@ bool "-> Magikarp" select BOARD_GOOGLE_KRABBY_COMMON -comment "Starmie" +comment "Staryu" config BOARD_GOOGLE_STARMIE bool "-> Starmie" - select BOARD_GOOGLE_STARMIE_COMMON + select BOARD_GOOGLE_STARYU_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/74654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c Gerrit-Change-Number: 74654 Gerrit-PatchSet: 2 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: samsung/lumpy: Use APMC defines
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74523 ) Change subject: samsung/lumpy: Use APMC defines ...................................................................... samsung/lumpy: Use APMC defines Change-Id: I658596da1d84b486126d751b6066c3efd3f65290 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74523 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/samsung/lumpy/smihandler.c 1 file changed, 16 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/samsung/lumpy/smihandler.c b/src/mainboard/samsung/lumpy/smihandler.c index 1c7d626..50cfa47 100644 --- a/src/mainboard/samsung/lumpy/smihandler.c +++ b/src/mainboard/samsung/lumpy/smihandler.c @@ -47,12 +47,12 @@ ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1); switch (apmc) { - case 0xe1: /* ACPI ENABLE */ + case APM_CNT_ACPI_ENABLE: send_ec_command(EC_SMI_DISABLE); send_ec_command(EC_ACPI_ENABLE); break; - case 0x1e: /* ACPI DISABLE */ + case APM_CNT_ACPI_DISABLE: send_ec_command(EC_SMI_ENABLE); send_ec_command(EC_ACPI_DISABLE); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/74523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658596da1d84b486126d751b6066c3efd3f65290 Gerrit-Change-Number: 74523 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: samsung/lumpy: Use APMC defines
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74523 ) Change subject: samsung/lumpy: Use APMC defines ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658596da1d84b486126d751b6066c3efd3f65290 Gerrit-Change-Number: 74523 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Apr 2023 16:21:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: lib/version: Move board identification strings
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74449 ) Change subject: lib/version: Move board identification strings ...................................................................... lib/version: Move board identification strings These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/root_device.c M src/include/device/device.h A src/include/identity.h M src/include/version.h M src/lib/Makefile.inc M src/lib/coreboot_table.c A src/lib/identity.c M src/lib/version.c M util/sconfig/main.c 9 files changed, 50 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/device/root_device.c b/src/device/root_device.c index 1f51786..d8edbd5 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -5,8 +5,6 @@ #include <device/pci.h> #include <reset.h> -const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; - void enable_static_device(struct device *dev) { if (dev->chip_ops && dev->chip_ops->enable_dev) diff --git a/src/include/device/device.h b/src/include/device/device.h index 0b67d3d..d044ae2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -174,8 +174,6 @@ extern struct resource *free_resources; extern struct bus *free_links; -extern const char mainboard_name[]; - /* Generic device interface functions */ struct device *alloc_dev(struct bus *parent, struct device_path *path); void dev_initialize_chips(void); diff --git a/src/include/identity.h b/src/include/identity.h new file mode 100644 index 0000000..d939291 --- /dev/null +++ b/src/include/identity.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef IDENTITY_H +#define IDENTITY_H + +/* Motherboard Information */ +extern const char mainboard_name[]; +extern const char mainboard_vendor[]; +extern const char mainboard_part_number[]; + +#endif /* IDENTITY_H */ diff --git a/src/include/version.h b/src/include/version.h index 84bb34a..926756a 100644 --- a/src/include/version.h +++ b/src/include/version.h @@ -3,10 +3,6 @@ #ifndef VERSION_H #define VERSION_H -/* Motherboard Information */ -extern const char mainboard_vendor[]; -extern const char mainboard_part_number[]; - /* coreboot Version */ extern const char coreboot_version[]; extern const char coreboot_extra_version[]; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index c83004a..385c87e 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -229,12 +229,8 @@ smm-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c endif -bootblock-y += version.c -romstage-y += version.c -ramstage-y += version.c -smm-y += version.c -verstage-y += version.c -postcar-y += version.c +all-y += identity.c version.c +smm-y += identity.c version.c $(call src-to-obj,bootblock,$(dir)/version.c) : $(obj)/build.h $(call src-to-obj,romstage,$(dir)/version.c) : $(obj)/build.h diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 0707fd3..bee389d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -4,12 +4,12 @@ #include <arch/cbconfig.h> #include <console/console.h> #include <console/uart.h> +#include <identity.h> #include <ip_checksum.h> #include <boot/coreboot_tables.h> #include <boot/tables.h> #include <boot_device.h> #include <string.h> -#include <version.h> #include <boardid.h> #include <device/device.h> #include <drivers/tpm/tpm_ppi.h> @@ -23,6 +23,7 @@ #include <spi_flash.h> #include <smmstore.h> #include <types.h> +#include <version.h> #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> diff --git a/src/lib/identity.c b/src/lib/identity.c new file mode 100644 index 0000000..04371a7 --- /dev/null +++ b/src/lib/identity.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <identity.h> + +#ifndef CONFIG_MAINBOARD_VENDOR +#error CONFIG_MAINBOARD_VENDOR not defined +#endif +#ifndef CONFIG_MAINBOARD_PART_NUMBER +#error CONFIG_MAINBOARD_PART_NUMBER not defined +#endif + +const char mainboard_vendor[] = CONFIG_MAINBOARD_VENDOR; +const char mainboard_part_number[] = CONFIG_MAINBOARD_PART_NUMBER; +const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; diff --git a/src/lib/version.c b/src/lib/version.c index 8471832..43d6a45 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -3,13 +3,6 @@ #include <version.h> #include <build.h> -#ifndef CONFIG_MAINBOARD_VENDOR -#error CONFIG_MAINBOARD_VENDOR not defined -#endif -#ifndef CONFIG_MAINBOARD_PART_NUMBER -#error CONFIG_MAINBOARD_PART_NUMBER not defined -#endif - #ifndef COREBOOT_VERSION #error COREBOOT_VERSION not defined #endif @@ -25,9 +18,6 @@ #define COREBOOT_EXTRA_VERSION "" #endif -const char mainboard_vendor[] = CONFIG_MAINBOARD_VENDOR; -const char mainboard_part_number[] = CONFIG_MAINBOARD_PART_NUMBER; - const char coreboot_version[] = COREBOOT_VERSION; const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION; const char coreboot_build[] = COREBOOT_BUILD; diff --git a/util/sconfig/main.c b/util/sconfig/main.c index aa79f1e..a246c01 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1965,6 +1965,7 @@ fprintf(f, "#include <device/device.h>\n"); fprintf(f, "#include <device/pci.h>\n"); fprintf(f, "#include <fw_config.h>\n"); + fprintf(f, "#include <identity.h>\n"); fprintf(f, "#include <%s>\n", static_header); emit_chip_headers(f, chip_header.next); emit_identifiers(f, "struct device_operations", device_operations); -- To view, visit https://review.coreboot.org/c/coreboot/+/74449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Gerrit-Change-Number: 74449 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb
by Felix Held (Code Review) 22 Apr '23

22 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74710 ) Change subject: include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74710/comment/09a0c266_80d5e18c PS1, Line 9: 'g' > nit: 'b' Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10 Gerrit-Change-Number: 74710 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sat, 22 Apr 2023 16:19:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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