coreboot-gerrit August 2022

coreboot-gerrit@coreboot.org

673 discussions

Change in coreboot[master]: pciexp: retrain PCIe link at lower speed if no link
by Jonathan Kollasch (Code Review) 10 Jun '23

10 Jun '23

Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42683 ) Change subject: pciexp: retrain PCIe link at lower speed if no link ...................................................................... pciexp: retrain PCIe link at lower speed if no link Needed for PCIe x4 dual-port Marvell NIC (sky2) on Sandy/Ivy Bridge and 6-series PCH (if not other chipsets), where the link will not come up at 5GT/s (or 8GT/s?), but will if explicitly trained at 2.5GT/s. Change-Id: I7ba15f7c13463356c6417f41b44d045aacfde4cc --- M src/device/pciexp_device.c M src/include/device/pci_def.h 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/42683/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f04d865..aeb44f7 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -112,6 +112,38 @@ } } +static void pciexp_limit_speed(struct device *dev, unsigned int cap) +{ + u16 x, y; + + x = pci_read_config16(dev, cap + PCI_EXP_FLAGS); + + /* is this new enough to support LNKCTL2? */ + if ((x & PCI_EXP_FLAGS_VERS) <= 1) + return; + + y = pci_read_config16(dev, cap + PCI_EXP_LNKCTL2); + y &= PCI_EXP_LNKCTL2_TLS; + + do { + /* link up? */ + x = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); + x = (x & PCI_EXP_LNKSTA_LW) >> 4; + if (x > 0) + return; + + printk(BIOS_INFO, "%s: link down; retraining at target link speed %u\n", + dev_path(dev), y); + + x = pci_read_config16(dev, cap + PCI_EXP_LNKCTL2); + x &= ~PCI_EXP_LNKCTL2_TLS; + x |= y & PCI_EXP_LNKCTL2_TLS; + pci_write_config16(dev, cap + PCI_EXP_LNKCTL2, x); + + pciexp_retrain_link(dev, cap); + } while (--y > 0); +} + static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap) { /* check if per port clk req is supported in device */ @@ -488,6 +520,12 @@ void pciexp_scan_bridge(struct device *dev) { + unsigned int cap; + + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (cap) + pciexp_limit_speed(dev, cap); + do_pci_scan_bridge(dev, pciexp_scan_bus); pciexp_enable_ltr(dev); } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 07ba4a2..b351e42 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -432,6 +432,7 @@ #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LW 0x3F0 /* Link Width */ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ @@ -446,6 +447,8 @@ #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTSTA 32 /* Root Status */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +#define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) -- To view, visit https://review.coreboot.org/c/coreboot/+/42683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ba15f7c13463356c6417f41b44d045aacfde4cc Gerrit-Change-Number: 42683 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41024 ) Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support ...................................................................... soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support Refer to https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilico… Include TCSS TBT PCIE Root Port 0/1/2/3 inside \_SB.PCIx (where x depends on PCI multiple segment support). Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/tigerlake/acpi/tcss.asl 3 files changed, 29 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41024/1 diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index a87c743..5997ccc 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -31,8 +31,8 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> - #include <soc/intel/tigerlake/acpi/tcss.asl> } + #include <soc/intel/tigerlake/acpi/tcss.asl> /* Mainboard hooks */ #include "mainboard.asl" } diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index c66e972..2576596 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -27,8 +27,8 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> - #include <soc/intel/tigerlake/acpi/tcss.asl> } + #include <soc/intel/tigerlake/acpi/tcss.asl> } #if CONFIG(CHROMEOS) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9f03aa9..86536bc 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -19,6 +19,10 @@ #define TCSS_XDCI 5 #define TCSS_DMA0 6 #define TCSS_DMA1 7 +#define TCSS_TBT_PCIE1_RP0 8 +#define TCSS_TBT_PCIE1_RP1 9 +#define TCSS_TBT_PCIE1_RP2 10 +#define TCSS_TBT_PCIE1_RP3 11 /* * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE @@ -681,7 +685,13 @@ } #include "tcss_dma.asl" } - +} +#if CONFIG_PCI_SEGMENT_GROUPS > 1 +Scope (\_SB.PCI1) +#else +Scope (\_SB.PCI0) +#endif +{ /* * TCSS PCIE Root Port #00 */ @@ -692,8 +702,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP0) +#else Name (DCPM, TCSS_TBT_PCIE0_RP0) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -717,8 +730,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP1) +#else Name (DCPM, TCSS_TBT_PCIE0_RP1) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -742,8 +758,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP2) +#else Name (DCPM, TCSS_TBT_PCIE0_RP2) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -767,8 +786,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP3) +#else Name (DCPM, TCSS_TBT_PCIE0_RP3) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) -- To view, visit https://review.coreboot.org/c/coreboot/+/41024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Gerrit-Change-Number: 41024 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/dg41wv: Inherit the subsystemid
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30470 Change subject: mb/intel/dg41wv: Inherit the subsystemid ...................................................................... mb/intel/dg41wv: Inherit the subsystemid Don't reprogram the same subsystemid for each PCI device. Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg41wv/devicetree.cb 1 file changed, 23 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30470/1 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad95..da91ea2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -24,14 +24,10 @@ end end device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x8086 0x5756 - end + subsystemid 0x8086 0x5756 inherit + device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG - device pci 2.0 on # Integrated graphics controller - subsystemid 0x8086 0x5756 - end + device pci 2.0 on end # Integrated graphics controller chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" @@ -66,39 +62,24 @@ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" - device pci 1b.0 on # Audio - subsystemid 0x8086 0x5756 + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2: NIC + device pci 00.0 on end end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2: NIC - device pci 00.0 on - subsystemid 0x8086 0x5756 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.1 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.2 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.3 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.7 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio Controller - device pci 1e.3 off end # AC'97 Modem Controller - device pci 1f.0 on # ISA bridge - subsystemid 0x8086 0x5756 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio Controller + device pci 1e.3 off end # AC'97 Modem Controller + device pci 1f.0 on # ISA bridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy # global @@ -155,12 +136,9 @@ end end device pci 1f.1 off end # PATA/IDE - device pci 1f.2 on # SATA - subsystemid 0x8086 0x5756 - end - device pci 1f.3 on # SMbus - subsystemid 0x8086 0x5756 - chip drivers/i2c/ck505 + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -173,7 +151,6 @@ 0x06, 0x00, 0xea }" device i2c 69 on end end - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Gerrit-Change-Number: 30470 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Enable ASPM for TBT PCIe root ports
by John Zhao (Code Review) 10 Jun '23

10 Jun '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47686 ) Change subject: device: Enable ASPM for TBT PCIe root ports ...................................................................... device: Enable ASPM for TBT PCIe root ports The virtual/generic device under TBT PCIe root ports has path type as DEVICE_PATH_GENERIC. While scanning the pcie bus, the generic device blocks its root ports configuration. This change adds device path type check and enables ASPM for TBT root ports. BUG=b:173207454 TEST=Built image and booted to kernel on Voxel board. Verified both of the TBT Root ports 00:07.0 and 00:07.1 ASPM are enabled. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I82ffaeb5a8821d9034d8dae9d98d3b5953a9608b --- M src/device/pciexp_device.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47686/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 8d4bb98..e85fe87 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -446,7 +446,7 @@ unsigned int root_cap, cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (!cap) + if ( !cap && (dev->path.type != DEVICE_PATH_GENERIC) ) return; root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE); @@ -480,7 +480,8 @@ pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { - if (child->path.type != DEVICE_PATH_PCI) + if ( (child->path.type != DEVICE_PATH_PCI) && + (child->path.type != DEVICE_PATH_GENERIC) ) continue; if ((child->path.pci.devfn < min_devfn) || (child->path.pci.devfn > max_devfn)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82ffaeb5a8821d9034d8dae9d98d3b5953a9608b Gerrit-Change-Number: 47686 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: force --divide for iPXE default build
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35820 ) Change subject: force --divide for iPXE default build ...................................................................... force --divide for iPXE default build Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35820/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 0c071fa..7005016 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -72,7 +72,7 @@ $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom WORKAROUND_ASFLAGS="--divide" endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) -- To view, visit https://review.coreboot.org/c/coreboot/+/35820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Gerrit-Change-Number: 35820 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]util/fsp-defaults: Add tool to extract FSP UPDs from binaries
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37674 ) Change subject: [WIP]util/fsp-defaults: Add tool to extract FSP UPDs from binaries ...................................................................... [WIP]util/fsp-defaults: Add tool to extract FSP UPDs from binaries Change-Id: Ia1174e2df7a6b0a634ea6f784abae65137ffc8f7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A util/fsp-defaults/.gitignore A util/fsp-defaults/Makefile A util/fsp-defaults/fspdef.awk A util/fsp-defaults/fspdef.h A util/fsp-defaults/main.c 5 files changed, 213 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/37674/1 diff --git a/util/fsp-defaults/.gitignore b/util/fsp-defaults/.gitignore new file mode 100644 index 0000000..1f5666f --- /dev/null +++ b/util/fsp-defaults/.gitignore @@ -0,0 +1,5 @@ +.fsp_inc +.udk_base +fspdef +fspm.c +fsps.c diff --git a/util/fsp-defaults/Makefile b/util/fsp-defaults/Makefile new file mode 100644 index 0000000..8adc0a9 --- /dev/null +++ b/util/fsp-defaults/Makefile @@ -0,0 +1,30 @@ +ifeq ($(UDK_BASE),) +$(warning Need to specify UDK_BASE=) +endif +$(shell if [ "$(UDK_BASE)" != "$$(cat .udk_base 2>/dev/null)" ]; then echo "$(UDK_BASE)" >.udk_base; fi) + +ifeq ($(FSP_INC),) +$(warning Need to specify FSP_INC=) +endif +$(shell if [ "$(FSP_INC)" != "$$(cat .fsp_inc 2>/dev/null)" ]; then echo "$(FSP_INC)" >.fsp_inc; fi) + +_CPPFLAGS = \ + -I../../src/commonlib/include/ \ + -I$(UDK_BASE)/MdePkg/Include/Ia32/ \ + -I$(UDK_BASE)/MdePkg/Include/ \ + -I$(UDK_BASE)/IntelFsp2Pkg/Include/ \ + -I$(FSP_INC)/ \ + +fspdef: main.c fspm.c fsps.c .fsp_inc .udk_base + gcc -m32 $(_CPPFLAGS) -o $@ $< fspm.c fsps.c + +fspm.c: $(FSP_INC)/FspmUpd.h fspdef.awk .fsp_inc .udk_base + gcc $(_CPPFLAGS) -E $< | gawk -f fspdef.awk > $@ + +fsps.c: $(FSP_INC)/FspsUpd.h fspdef.awk .fsp_inc .udk_base + gcc $(_CPPFLAGS) -E $< | gawk -f fspdef.awk > $@ + +clean: + rm -f fspm.c fsps.c fspdef + +.PHONY: clean diff --git a/util/fsp-defaults/fspdef.awk b/util/fsp-defaults/fspdef.awk new file mode 100644 index 0000000..07a9756 --- /dev/null +++ b/util/fsp-defaults/fspdef.awk @@ -0,0 +1,97 @@ +function process(field, width) { + printf("\tif (config->%s)\n", field); + printf("\t\tprintf(\"\\t\\t/* 0x%%04x */ .%s = 0x%%\"PRIx%s\",\\n\", offset + offsetof(typeof(*config), %s), config->%s);\n", + field, width, field, field); +} + +function process_array(field, width) { + printf("\tfor (i = 0; i < ARRAY_SIZE(config->%s); ++i) {\n", field); + printf("\t\tif (config->%s[i])\n", field); + printf("\t\t\tbreak;\n"); + printf("\t}\n"); + printf("\tif (i < ARRAY_SIZE(config->%s)) {\n", field); + printf("\t\tprintf(\"\\t\\t/* 0x%%04x */ .%s = {\", offset + offsetof(typeof(*config), %s));\n", + field, field); + printf("\t\tfor (i = 0; i < ARRAY_SIZE(config->%s); ++i) {\n", field); + printf("\t\t\tif (i % 8 == 0)\n"); + printf("\t\t\t\tprintf(\"\\n\\t\\t\\t\");\n"); + printf("\t\t\tprintf(\"0x%%\"PRIx%s\",\", config->%s[i]);\n", width, field); + printf("\t\t\tif ((i + 1) % 8 != 0 && i != ARRAY_SIZE(config->%s) - 1)\n", field); + printf("\t\t\t\tprintf(\" \");\n"); + printf("\t\t}\n"); + printf("\t\tprintf(\"\\n\\t\\t},\\n\");\n"); + printf("\t}\n"); +} + +function process_struct(cname, tname) { + printf("void process_%s(const size_t offset, const %s *const config)\n{\n", cname, tname); + printf("\tunsigned int i;\n"); + printf("\tprintf(\"\\tstatic const %s default_%s = {\\n\");\n\n", tname, cname); + for (field in fields) { + if (field in arrays) + process_array(fields[field], widths[field]); + else + process(fields[field], widths[field]); + printf("\n"); + } + printf("\tprintf(\"\\t};\\n\\n\");\n"); + printf("}\n\n"); +} + +BEGIN { + gather = 0; + + printf("#include <stdio.h>\n"); + printf("#include <stddef.h>\n"); + printf("#include <inttypes.h>\n"); + printf("#include <commonlib/helpers.h>\n"); + printf("#include <FspmUpd.h>\n"); + printf("#include <FspsUpd.h>\n\n"); + printf("#include \"fspdef.h\"\n\n"); +} + +/typedef struct {/ { + gather = 1; + field = 0; +} + +# match single identifiers +match($0, /(UINT|CHAR)([0-9]+) ([0-9a-zA-Z]+);/, matches) { + if (gather) { + fields[field] = matches[3]; + widths[field] = matches[2]; + ++field; + } +} + +# match array identifiers +match($0, /(UINT|CHAR)([0-9]+) ([0-9a-zA-Z]+)\[([0-9]+)\];/, matches) { + if (gather) { + fields[field] = matches[3]; + widths[field] = matches[2]; + arrays[field] = "dummy"; + ++field; + } +} + +/} FSP_M_CONFIG;/ { + process_struct("fsp_m_config", "FSP_M_CONFIG"); +} + +/} FSP_M_TEST_CONFIG;/ { + process_struct("fsp_m_tconfig", "FSP_M_TEST_CONFIG"); +} + +/} FSP_S_CONFIG;/ { + process_struct("fsp_s_config", "FSP_S_CONFIG"); +} + +/} FSP_S_TEST_CONFIG;/ { + process_struct("fsp_s_tconfig", "FSP_S_TEST_CONFIG"); +} + +/} .*;/ { + gather = 0; + delete fields; + delete arrays; +} diff --git a/util/fsp-defaults/fspdef.h b/util/fsp-defaults/fspdef.h new file mode 100644 index 0000000..72d99ad --- /dev/null +++ b/util/fsp-defaults/fspdef.h @@ -0,0 +1,12 @@ +#ifndef UTIL_FSP_DEFAULTS_FSPDEF_H +#define UTIL_FSP_DEFAULTS_FSPDEF_H + +#include <FspmUpd.h> +#include <FspsUpd.h> + +void process_fsp_m_config(size_t offset, const FSP_M_CONFIG *); +void process_fsp_m_tconfig(size_t offset, const FSP_M_TEST_CONFIG *); +void process_fsp_s_config(size_t offset, const FSP_S_CONFIG *); +void process_fsp_s_tconfig(size_t offset, const FSP_S_TEST_CONFIG *); + +#endif /* UTIL_FSP_DEFAULTS_FSPDEF_H */ diff --git a/util/fsp-defaults/main.c b/util/fsp-defaults/main.c new file mode 100644 index 0000000..eb4d2a9 --- /dev/null +++ b/util/fsp-defaults/main.c @@ -0,0 +1,69 @@ +#include <stdio.h> +#include <stddef.h> +#include <stdint.h> +#include <fcntl.h> +#include <unistd.h> +#include <sys/stat.h> +#include <sys/mman.h> +#include <FspUpd.h> +#include <FspmUpd.h> +#include <FspsUpd.h> + +#include "fspdef.h" + +int main(const int argc, const char *const argv[]) +{ + if (argc != 2) { + fprintf(stderr, "Usage: %s <path-to-FSP.fd>\n", argv[0]); + return 1; + } + + const int fd = open(argv[1], O_RDONLY); + if (fd == -1) { + perror("Failed to open FSP.fd"); + return 2; + } + + struct stat stat; + if (fstat(fd, &stat)) { + perror("Failed to stat FSP.fd"); + return 3; + } + + const void *const fsp = mmap(NULL, stat.st_size, PROT_READ, MAP_SHARED, fd, 0); + close(fd); + if (fsp == MAP_FAILED) { + perror("Failed to map FSP.fd"); + return 3; + } + + const uint8_t *it, *const end = (const uint8_t *)fsp + stat.st_size; + for (it = fsp; it < end; ++it) { + const uint64_t *const sig = (const uint64_t *)it; + const FSPM_UPD *fspm; + const FSPS_UPD *fsps; + switch (*sig) { + case FSPM_UPD_SIGNATURE: + fspm = (const FSPM_UPD *)sig; + process_fsp_m_config( + offsetof(FSPM_UPD, FspmConfig), + &fspm->FspmConfig); + process_fsp_m_tconfig( + offsetof(FSPM_UPD, FspmTestConfig), + &fspm->FspmTestConfig); + break; + case FSPS_UPD_SIGNATURE: + fsps = (const FSPS_UPD *)sig; + process_fsp_s_config( + offsetof(FSPS_UPD, FspsConfig), + &fsps->FspsConfig); + process_fsp_s_tconfig( + offsetof(FSPS_UPD, FspsTestConfig), + &fsps->FspsTestConfig); + break; + } + } + + munmap((void *)fsp, stat.st_size); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1174e2df7a6b0a634ea6f784abae65137ffc8f7 Gerrit-Change-Number: 37674 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: configs: Build test x86_64 on 3 Intel boards
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48452 ) Change subject: configs: Build test x86_64 on 3 Intel boards ...................................................................... configs: Build test x86_64 on 3 Intel boards Change-Id: I6d8497eafb486e2727a47ce546c3e2095280bc45 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A configs/config.intel_coffeelake_rvp11.x86_64 A configs/config.libretrend_lt1000.x86_64 A configs/config.up_squared.x86_64 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/48452/1 diff --git a/configs/config.intel_coffeelake_rvp11.x86_64 b/configs/config.intel_coffeelake_rvp11.x86_64 new file mode 100644 index 0000000..eea05cc --- /dev/null +++ b/configs/config.intel_coffeelake_rvp11.x86_64 @@ -0,0 +1,6 @@ +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_INTEL=y +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin" +CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y +CONFIG_PAYLOAD_NONE=y +CONFIG_EXP_ARCH_X86_64=y diff --git a/configs/config.libretrend_lt1000.x86_64 b/configs/config.libretrend_lt1000.x86_64 new file mode 100644 index 0000000..ec8babc --- /dev/null +++ b/configs/config.libretrend_lt1000.x86_64 @@ -0,0 +1,2 @@ +CONFIG_VENDOR_LIBRETREND=y +CONFIG_EXP_ARCH_X86_64=y diff --git a/configs/config.up_squared.x86_64 b/configs/config.up_squared.x86_64 new file mode 100644 index 0000000..6d942aa --- /dev/null +++ b/configs/config.up_squared.x86_64 @@ -0,0 +1,3 @@ +CONFIG_VENDOR_UP=y +CONFIG_PAYLOAD_NONE=y +CONFIG_EXP_ARCH_X86_64=y -- To view, visit https://review.coreboot.org/c/coreboot/+/48452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d8497eafb486e2727a47ce546c3e2095280bc45 Gerrit-Change-Number: 48452 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/google/dedede/var/metaknight: Add device settings
by Tim Chen (Code Review) 10 Jun '23

10 Jun '23

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47013 to review the following change. Change subject: mb/google/dedede/var/metaknight: Add device settings ...................................................................... mb/google/dedede/var/metaknight: Add device settings Add the configuration in device tree: 1. Add HDA,speaker codec and speaker amp setting 2. Add Elan, Raydium and Goodix touchscreen setting 3. Add user/world facing camera usb setting 4 Add Synaptics and Elan Touchpad setting 5. Add WiFi configuration 6. Add DPTF setting BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ie034724ea5c6edff6cdba694605d3238f66be910 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 175 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47013/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 404024b..af7de71 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -1,5 +1,9 @@ chip soc/intel/jasperlake + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -11,7 +15,7 @@ #| I2C0 | Trackpad | #| I2C1 | Digitizer | #| I2C2 | Touchscreen | - #| I2C3 | Camera | + #| I2C3 | TBD | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -36,7 +40,176 @@ }, }" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + device domain 0 on - device pci 15.0 on end + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 7000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 39 on end + end + end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN end end -- To view, visit https://review.coreboot.org/c/coreboot/+/47013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie034724ea5c6edff6cdba694605d3238f66be910 Gerrit-Change-Number: 47013 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: [WIP] [Don't Merge]: PO Safe Config
by Meera Ravindranath (Code Review) 10 Jun '23

10 Jun '23

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48527 to review the following change. Change subject: [WIP] [Don't Merge]: PO Safe Config ...................................................................... [WIP] [Don't Merge]: PO Safe Config Change-Id: I7cce423de924e7056e88b52a2443c554fd9123ac Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48527/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index a21ca4a..f176785 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -273,7 +273,7 @@ sizeof(config->PcieRpClkReqDetect)); params->PmSupport = 1; - params->Hwp = 1; + params->Hwp = 0; params->Cx = 1; params->PsOnEnable = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/48527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de924e7056e88b52a2443c554fd9123ac Gerrit-Change-Number: 48527 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/...
by Kevin Cody-Little (Code Review) 10 Jun '23

10 Jun '23

Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38207 ) Change subject: Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/intel/skylake/Kconfig to individual Skylake and Kaby Lake mainboard Kconfig's, to allow de-legacying on a per-board basis. ...................................................................... Move "select SOC_INTLE_COMMON_BLOCK_GPIO_LEGACY_MACROS" from src/soc/intel/skylake/Kconfig to individual Skylake and Kaby Lake mainboard Kconfig's, to allow de-legacying on a per-board basis. Change-Id: Idc756f65b1377d3f31507ff25424e8c898ae6f59 Signed-off-by: Kevin Cody <kcodyjr(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/soc/intel/skylake/Kconfig 13 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38207/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..165c440 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -16,6 +16,7 @@ select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 3261661..2dabb2b 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config CBFS_SIZE hex "CBFS_SIZE" diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index dcc5b38..34a0368 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE select SYSTEM_TYPE_CONVERTIBLE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index cafb855..9abf2bc 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -26,6 +26,7 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SPD_READ_BY_WORD + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index bc0c67b..e8f3e3e 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,7 @@ select SYSTEM_TYPE_LAPTOP select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_NO_FSP_GOP if !BOARD_GOOGLE_GLADOS + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_GLADOS diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 5a621bb..b2f28fa 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index afc510f..cd5f8a2 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LPC_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_KBLRVP8 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d7706d1..6bad7c8 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,6 +19,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_SKYLAKE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 315104e..f985cde 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -30,6 +30,7 @@ select SUPERIO_NUVOTON_NCT6776_COM_A select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index ca1582a..cfef895 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -11,6 +11,7 @@ select SPD_READ_BY_WORD select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_PURISM_BASEBOARD_LIBREM_SKL diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 903d7ba..4aa6669 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -16,6 +16,7 @@ select HAVE_ACPI_TABLES select ADD_FSP_BINARIES select FSP_USE_REPO + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS # For now no way to choose the correct the available RAM config BOARD_RAZER_BLADE_STEALTH_KBL_16GB diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 5a99f7a..27b4e44 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_NO_FSP_GOP select SUPERIO_ASPEED_HAS_UART_DELAY_WORKAROUND select NO_FADT_8042 + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d90fb6b..ab944b6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -57,7 +57,6 @@ select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT - select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/38207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc756f65b1377d3f31507ff25424e8c898ae6f59 Gerrit-Change-Number: 38207 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Cody-Little <kcodyjr(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2022