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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63375 )
Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage
......................................................................
Patch Set 3:
(6 comments)
File src/include/cbmem.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145631):
https://review.coreboot.org/c/coreboot/+/63375/comment/2f0d8b23_895b669d
PS3, Line 110: #define _CBMEM_INIT_HOOK_UNUSED(init_fn_) __attribute__((unused)) \
macros should not use a trailing semicolon
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145631):
https://review.coreboot.org/c/coreboot/+/63375/comment/653a8a29_32d9fc24
PS3, Line 113: #define _CBMEM_INIT_HOOK(init_fn_) \
macros should not use a trailing semicolon
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145631):
https://review.coreboot.org/c/coreboot/+/63375/comment/f699c833_2cca6369
PS3, Line 119: #define _CBMEM_INIT_HOOK_EARLY(init_fn_) \
macros should not use a trailing semicolon
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145631):
https://review.coreboot.org/c/coreboot/+/63375/comment/72c1ce6f_3fae2636
PS3, Line 124: #define CBMEM_CREATION_HOOK(x) _CBMEM_INIT_HOOK(x)
please, no space before tabs
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145631):
https://review.coreboot.org/c/coreboot/+/63375/comment/954a4574_b3218c9c
PS3, Line 126: #define CBMEM_CREATION_HOOK(x) _CBMEM_INIT_HOOK_UNUSED(x)
please, no space before tabs
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145631):
https://review.coreboot.org/c/coreboot/+/63375/comment/6d55958d_5da0f527
PS3, Line 130: #define CBMEM_INIT_HOOK(x) _CBMEM_INIT_HOOK(x)
please, no space before tabs
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Change subject: drivers/amd/agesa/romstage.c: Move timestamp and console init up
......................................................................
Patch Set 7: Code-Review+2
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Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage
......................................................................
Patch Set 3:
(1 comment)
File src/arch/x86/acpi_bert_storage.c:
https://review.coreboot.org/c/coreboot/+/63375/comment/0b0153ca_b236dbc3
PS2, Line 602: CBMEM_INIT_HOOK(bert_storage_setup);
> This does not have the characteristics of other CBMEM_INIT_HOOKS where something either migrates fro […]
Comments in CB:63415, please.
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Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63414 )
Change subject: lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks
......................................................................
lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks
Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/acpi/gnvs.c
M src/include/acpi/acpi_gnvs.h
M src/lib/hardwaremain.c
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/gnvs.c
5 files changed, 8 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/63414/2
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Hello Hung-Te Lin, build bot (Jenkins), Raul Rangel, Julius Werner, Arthur Heymans, Andrey Petrov, Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Fred Reitberger, Yu-Ping Wu, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage
......................................................................
[RFC] CBMEM: Have INIT_HOOKS in every stage
There are efforts to have bootflows that do not follow
a traditional bootblock-romstage-postcar-ramstage model.
As part of that CBMEM initialisation hooks will need to move
from romstage to bootblock.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/usb/ehci_debug.c
M src/drivers/vpd/vpd.c
M src/include/cbmem.h
M src/include/rules.h
M src/lib/cbfs.c
M src/lib/cbmem_console.c
M src/lib/ext_stage_cache.c
M src/lib/fmap.c
M src/lib/timestamp.c
M src/security/tpm/tspi/log.c
M src/security/vboot/common.c
M src/soc/amd/common/block/pm/chipset_state.c
M src/soc/amd/common/pi/heapmanager.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/broadwell/pch/power_state.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/quark/storage_test.c
M src/soc/mediatek/common/memory.c
M src/soc/qualcomm/common/qclib.c
22 files changed, 50 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63375/3
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Hello build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56794
to look at the new patch set (#55).
Change subject: libpayload/pci: Add pci_map_bus interface for MediaTek platform
......................................................................
libpayload/pci: Add pci_map_bus interface for MediaTek platform
Add 'pci_map_bus' interface for MediaTek platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
---
M payloads/libpayload/Kconfig
M payloads/libpayload/drivers/Makefile.inc
A payloads/libpayload/drivers/pcie_mediatek.c
3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/55
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