coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5257 discussions

Change in coreboot[master]: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps
by Nikolai Vyssotski (Code Review) 25 Oct '22

25 Oct '22

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45278 ) Change subject: WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps ...................................................................... WIP: Use SPDs from PSP BIOS table type 0x69 based on GPIO straps Use GPIOs mapping defined in APCB GET_SPD_FROM_GPIO to fetch correct SPD block from PSP BIOS table entry type 0x69 (BIOS_SPD_DATA). There is only one APCB now with no SPD data in it. No need for board ID getting method. This will save ROM space consumed by multiple APCB copies in the past. This is a working example of an implementation tested on Dalboz. It does not require patching with APCB_EDIT_TOOL. All SPDs are assembled in one type 0x69 blob and inserted into PSP BIOS directory. BUG=b:127505025 TEST=Dalboz with CABLRV20090300 and test CB and boot loader code BRANCH=Zork Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 42 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45278/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index eb2be50..e83e08d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -198,7 +198,7 @@ # # type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) +PSP_SPD_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/SPD_$(f).bin) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) @@ -262,6 +262,12 @@ # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 +# SPD data array blob (with SPDs for all possible memory IDs for this platform) +SPD_BLOB:=$(obj)/SPD_array.bin + +# APCB binary without SPD data +APCB_NO_SPD_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin + # Helper function to return a value with given bit set set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ @@ -304,9 +310,8 @@ OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) -OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ - $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) +OPT_PSP_APCB_FILE=$(call add_opt_prefix, $(APCB_NO_SPD_BLOB), --instance 0 --apcb) +OPT_SPD_BLOB=$(call add_opt_prefix, $(SPD_BLOB), --spd-data-blob) OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) @@ -341,7 +346,8 @@ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_APCB_FILE) \ + $(OPT_SPD_BLOB) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ @@ -383,6 +389,16 @@ --soc-name "Picasso" \ --flashsize $(CONFIG_ROM_SIZE) +# Copy prebuild APCBs if they exist +$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin + cp $< $@ + +$(obj)/SPD_%.bin: $$(SPD_SOURCES_DIR)/%.hex + xxd -r -p $< > $@ + +$(SPD_BLOB): $$(PSP_SPD_FILES) + cat $+ > $@ + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ @@ -418,12 +434,22 @@ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ - $$(PSP_APCB_FILES) \ + $(PSP_APCB_FILE) \ + $(SPD_BLOB) \ $(AMDFWTOOL) \ $(obj)/fmap.fmd $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + echo $(AMDFWTOOL) \ + $(OPT_PSPBTLDR_FILE) \ + $(AMDFW_COMMON_ARGS) \ + $(OPT_APOB0_NV_SIZE) \ + $(OPT_APOB0_NV_BASE) \ + $(OPT_VERSTAGE_FILE) \ + $(OPT_VERSTAGE_SIG_FILE) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --output $@ $(AMDFWTOOL) \ $(OPT_PSPBTLDR_FILE) \ $(AMDFW_COMMON_ARGS) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f385068..2192a04 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -215,6 +215,7 @@ printf("-q | --anywhere Use any 64-byte aligned addr for Directory\n"); printf("-R | --sharedmem Location of PSP/FW shared memory\n"); printf("-P | --sharedmem-size Maximum size of the PSP/FW shared memory area\n"); + printf("--spd-data-blob Add SPD array\n"); printf("-C | --soc-name <socname> Specify SOC name. Supported names are\n"); printf(" Stoneyridge, Raven, Picasso, Renoir or Lucienne"); printf("-h | --help show this help\n"); @@ -251,6 +252,7 @@ AMD_BIOS_PMUD = 0x65, AMD_BIOS_UCODE = 0x66, AMD_BIOS_APCB_BK = 0x68, + AMD_BIOS_SPD_DATA = 0x69, AMD_BIOS_MP2_CFG = 0x6a, AMD_BIOS_PSP_SHARED_MEM = 0x6b, AMD_BIOS_L2_PTR = 0x70, @@ -409,6 +411,7 @@ { .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH }, + { .type = AMD_BIOS_SPD_DATA, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, .reset = 1, .copy = 1, .zlib = 1, .level = BDT_BOTH }, @@ -1085,6 +1088,7 @@ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, LONGOPT_SPI_MICRON_FLAG = 258, + LONGOPT_SPD_DATA = 259, }; // Unused values: D @@ -1136,6 +1140,7 @@ {"mp2-config", required_argument, 0, 'X' }, {"apob-nv-base", required_argument, 0, 'F' }, {"apob-nv-size", required_argument, 0, 'H' }, + {"spd-data-blob", required_argument, 0, LONGOPT_SPD_DATA }, /* Embedded Firmware Structure items*/ {"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE }, {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, @@ -1450,6 +1455,11 @@ instance, optarg); sub = instance = 0; break; + case LONGOPT_SPD_DATA: + /* optional SPD data array outside of APCB */ + register_bdt_data(AMD_BIOS_SPD_DATA, sub, instance, optarg); + sub = instance = 0; + break; case 'Q': /* APOB destination */ register_fw_addr(AMD_BIOS_APOB, 0, optarg, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/45278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9adf7a016ee481214b47d8adc6d53fd8ce0c9bd4 Gerrit-Change-Number: 45278 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: arch/x86: x86_64 implies SSE2 support
by Patrick Rudolph (Code Review) 24 Oct '22

24 Oct '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44869 ) Change subject: arch/x86: x86_64 implies SSE2 support ...................................................................... arch/x86: x86_64 implies SSE2 support Enable SSE2 when compiling for x86_64. Tested on qemu. Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/Kconfig M src/arch/x86/bootblock_crt0.S 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44869/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index d906436..d0e4693 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -33,22 +33,27 @@ config ARCH_BOOTBLOCK_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_VERSTAGE_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_ROMSTAGE_X86_64 bool select ARCH_X86 + select SSE2 config ARCH_POSTCAR_X86_64 bool default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE + select SSE2 config ARCH_RAMSTAGE_X86_64 bool select ARCH_X86 + select SSE2 if ARCH_X86 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9f45413..9e17b7e 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -52,9 +52,15 @@ #if CONFIG(SSE) enable_sse: +#if ENV_X86_32 mov %cr4, %eax or $CR4_OSFXSR, %ax mov %eax, %cr4 +#else + mov %cr4, %rax + or $CR4_OSFXSR, %ax + mov %rax, %cr4 +#endif #endif /* CONFIG(SSE) */ /* We're done. Now it's up to platform-specific code */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Gerrit-Change-Number: 44869 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: arch/x86: Add option to compress postcar stage
by Arthur Heymans (Code Review) 21 Oct '22

21 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36674 ) Change subject: arch/x86: Add option to compress postcar stage ...................................................................... arch/x86: Add option to compress postcar stage The LZ4 decompressor was already linked in romstage. Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36674/1 diff --git a/src/Kconfig b/src/Kconfig index 0d56291..17bf545 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -158,6 +158,16 @@ that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI). +config COMPRESS_POSTCAR + bool "Compress postcar with LZ4" + depends on POSTCAR_STAGE + # Default value set at the end of the file + help + Compress postcar with LZ4 to save flash space and speed up boot, + since the time for reading the image from SPI (and in the vboot + case verifying it) is usually much greater than the time spent + decompressing. + config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) @@ -1203,6 +1213,9 @@ config COMPRESS_RAMSTAGE default y if !UNCOMPRESSED_RAMSTAGE +config COMPRESS_POSTCAR + default y + config COMPRESS_PRERAM_STAGES depends on !ARCH_X86 default y diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..8c35176 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -278,11 +278,16 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ +CBFS_POSTCAR_COMPRESS_FLAG := none +ifeq ($(CONFIG_COMPRESS_POSTCAR),y) +CBFS_POSTCAR_COMPRESS_FLAG := lz4 +endif + # Add postcar to CBFS cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage -$(CONFIG_CBFS_PREFIX)/postcar-compression := none +$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG) ############################################################################### # ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/36674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Gerrit-Change-Number: 36674 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

8 22

Change in coreboot[master]: [WIP]cpu/x86/cache: CLFLUSH programs to memory before running
by Arthur Heymans (Code Review) 21 Oct '22

21 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37196 ) Change subject: [WIP]cpu/x86/cache: CLFLUSH programs to memory before running ...................................................................... [WIP]cpu/x86/cache: CLFLUSH programs to memory before running When cbmem is initialized in romstage and postcar placed in the stage cache + cbmem where it is run, the assumption is made that this are all in UC memory such that calling invd in postcar is ok. For performance reasons (e.g. postcar decompression) it is desirable to cache cbmem and the stage cache during romstage. Another reason is that AGESA sets up MTRR during romstage to cache all dram, which is currently worked around by using additional MTRR to make that UC. TODO be nice to reviewers and spit some parts off. UNTESTED Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/postcar_loader.c M src/cpu/x86/cache/Makefile.inc M src/cpu/x86/cache/cache.c M src/include/cpu/x86/cache.h 4 files changed, 68 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37196/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b53cbf8..53ab4f9 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -208,6 +208,21 @@ MTRR_TYPE_WRBACK); } +/* + * POSTCAR will call invd so don't make assumptions on cbmem + * and external stage cache being UC. + */ +static void postcar_flush_cache(void) +{ + uintptr_t stage_cache_base; + size_t stage_cache_size; + prog_segment_loaded((uintptr_t)cbmem_top(), cbmem_overhead_size(), SEG_FINAL); + if (CONFIG(TSEG_STAGE_CACHE)) { + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + prog_segment_loaded(stage_cache_base, stage_cache_size, SEG_FINAL); + } +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = @@ -222,8 +237,10 @@ parameters between S3 resume and normal boot. On the platforms where the values are the same it's a nop. */ finalize_load(prog.arg, pcf->stack); - } else + } else { load_postcar_cbfs(&prog, pcf); + postcar_flush_cache(); + } /* As postcar exist, it's end of romstage here */ timestamp_add_now(TS_END_ROMSTAGE); diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc index b33b9ee..759488e 100644 --- a/src/cpu/x86/cache/Makefile.inc +++ b/src/cpu/x86/cache/Makefile.inc @@ -1 +1,2 @@ +romstage-y += cache.c ramstage-y += cache.c diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c index 2313c4d..ac2c45b 100644 --- a/src/cpu/x86/cache/cache.c +++ b/src/cpu/x86/cache/cache.c @@ -11,8 +11,11 @@ * GNU General Public License for more details. */ +#include <cbmem.h> +#include <program_loading.h> #include <console/console.h> #include <cpu/x86/cache.h> +#include <arch/cpu.h> void x86_enable_cache(void) { @@ -20,3 +23,47 @@ printk(BIOS_INFO, "Enabling cache\n"); enable_cache(); } + +int clflush_supported(void) +{ + return (cpuid_edx(1) >> 19) & 1; +} + +static void clflush_region(uintptr_t start, size_t size) +{ + uintptr_t addr; + size_t cl_size = (cpuid_ebx(1) >> 8) & 0xff; + if (!clflush_supported()) + return; + for (addr = (start / cl_size) * cl_size; addr < start + size; addr += cl_size) + clflush((void *)addr); +} + +static int dram_ready; + +/* + * For each segment of a program loaded this function is called + * to invalidate caches for the addresses of the loaded segment + */ +void arch_segment_loaded(uintptr_t start, size_t size, int flags) +{ + /* INVD is only called in postcar stage so we only need + to make sure that our things hit dram during romstage. */ + if (!ENV_ROMSTAGE) + return; + if (flags != SEG_FINAL) + return; + if (!dram_ready) + return; + + if (!clflush_supported()) + printk(BIOS_DEBUG, "Not flushing cache to ram, CLFLUSH not supported\n"); + clflush_region(start, size); +} + +static void set_dram_ready(int unused) +{ + dram_ready = 1; +} + +ROMSTAGE_CBMEM_INIT_HOOK(set_dram_ready); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 713ca32..2d2727f 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -55,6 +55,8 @@ asm volatile ("clflush (%0)"::"r" (addr)); } +int clflush_supported(void); + /* The following functions require the __always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as * RAM, the cache as RAM stack can no longer be used. Called -- To view, visit https://review.coreboot.org/c/coreboot/+/37196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b Gerrit-Change-Number: 37196 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 25

Change in coreboot[master]: arch/x86: Don't use .bss from car.ld if not running XIP
by Arthur Heymans (Code Review) 20 Oct '22

20 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48156 ) Change subject: arch/x86: Don't use .bss from car.ld if not running XIP ...................................................................... arch/x86: Don't use .bss from car.ld if not running XIP Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/rules.h M src/lib/program.ld 4 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48156/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..7d7d3fc 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -36,6 +36,7 @@ mov $_STACK_TOP, %esp /* clear .bss section as it is not shared */ +#if ENV_STAGE_XIP cld xor %eax, %eax movl $(_ebss), %ecx @@ -43,6 +44,7 @@ sub %edi, %ecx shrl $2, %ecx rep stosl +#endif #if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c291efb..38128d1 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -62,6 +62,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram. */ +#if ENV_STAGE_HAS_CAR_XIP_BSS . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; /* Allow global uninitialized variables for stages without CAR teardown. */ @@ -71,6 +72,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; +#endif #if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; diff --git a/src/include/rules.h b/src/include/rules.h index 6ebb37e..f503914 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -261,14 +261,21 @@ #if ENV_X86 /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) +/* Indicates if the stage runs XIP. */ +#define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ + !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 #define ENV_CACHE_AS_RAM 0 +#define ENV_STAGE_XIP 0 #endif +/* Indicates if the stages uses the _bss region defined in arch/x86/car.ld */ +#define ENV_STAGE_HAS_CAR_XIP_BSS ENV_STAGE_XIP + /* Currently rmodules, ramstage and smm have heap. */ #define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) diff --git a/src/lib/program.ld b/src/lib/program.ld index 3b6aa2e..ff3c672 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -103,7 +103,7 @@ } #endif -#if !ENV_CACHE_AS_RAM +#if !ENV_STAGE_HAS_CAR_XIP_BSS .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/48156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Gerrit-Change-Number: 48156 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

8 32

Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 04 Oct '22

04 Oct '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: include/rules.h: Allow .data section on non-XIP stages
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48157 ) Change subject: include/rules.h: Allow .data section on non-XIP stages ...................................................................... include/rules.h: Allow .data section on non-XIP stages This allows platform that don't run stage XIP to have a .data section. Change-Id: I40a651398dff374bf6ba75471b07662de96fb434 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/rules.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48157/1 diff --git a/src/include/rules.h b/src/include/rules.h index f503914..a7fc77f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -265,7 +265,7 @@ #define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ -#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +#define ENV_STAGE_HAS_DATA_SECTION !ENV_STAGE_XIP #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40a651398dff374bf6ba75471b07662de96fb434 Gerrit-Change-Number: 48157 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: Kconfig: Allow x86 to compress pre-ram stages if not run XIP
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36613 ) Change subject: Kconfig: Allow x86 to compress pre-ram stages if not run XIP ...................................................................... Kconfig: Allow x86 to compress pre-ram stages if not run XIP Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36613/1 diff --git a/src/Kconfig b/src/Kconfig index 793927a..df86246 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -160,7 +160,7 @@ config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" - depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) + depends on HAVE_ROMSTAGE || HAVE_VERSTAGE # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash @@ -1217,7 +1217,7 @@ default y if !UNCOMPRESSED_RAMSTAGE config COMPRESS_PRERAM_STAGES - depends on !ARCH_X86 + depends on NO_XIP_EARLY_STAGES default y config INCLUDE_CONFIG_FILE diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..db4f054 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -119,6 +119,7 @@ ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S +bootblock-y += memmove.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) -- To view, visit https://review.coreboot.org/c/coreboot/+/36613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac24d243c4bd4cb8c1db14a8e9fc43f508c2cd5d Gerrit-Change-Number: 36613 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: soc/intel/apollolake: LZ4 Compress FSP-M
by Arthur Heymans (Code Review) 20 Sep '22

20 Sep '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48158 ) Change subject: soc/intel/apollolake: LZ4 Compress FSP-M ...................................................................... soc/intel/apollolake: LZ4 Compress FSP-M FSP-M is not run XIP so it can be compressed. This more than halves the binary size. 364544 bytes -> 168616 bytes. On the up/squared this also results in a 83ms speedup. TESTED: up/squared boots. Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48158/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4f762a9..bf7cd0b 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,6 +46,7 @@ select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES + select FSP_COMPRESS_FSP_M_LZ4 select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEXP_ASPM -- To view, visit https://review.coreboot.org/c/coreboot/+/48158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Gerrit-Change-Number: 48158 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 12

Change in coreboot[master]: cpu/intel/haswell: add Crystal Well CPU IDs
by Iru Cai (vimacs) (Code Review) 11 Sep '22

11 Sep '22

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44066 to review the following change. Change subject: cpu/intel/haswell: add Crystal Well CPU IDs ...................................................................... cpu/intel/haswell: add Crystal Well CPU IDs Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44066/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index e621638..5f3debb 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -778,6 +778,8 @@ { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ + { X86_VENDOR_INTEL, 0x40660 }, /* Intel Crystal Well C0 */ + { X86_VENDOR_INTEL, 0x40661 }, /* Intel Crystal Well C1 */ { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4ae71fd977d32d7b11ee7e2a1a7e2ec3eec52f Gerrit-Change-Number: 44066 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

← Newer
1
2
3
4
5
6
7
...
526
Older →

Jump to page:

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022