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Change subject: soc/intel/elkhartlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Tested? Does it even support HT?
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Change subject: soc/intel/cannonlake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel Kconfig
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/60543/comment/6e7061d6_e9a54893
PS2, Line 141: bool "Enable Hyper-Threading"
The prompt, or the whole config, should be opt in unless you plan to
make it useful for all platforms that include this file (I don't think
all platforms support HT, so this would probably be futile).
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Change subject: soc/intel/skylake: Hook up FSP hyper-threading setting to option API
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60542/comment/eefd098b_e8ce5487
PS2, Line 15: obsolete now.
This board takes config FSP_HYPERTHREADING into account now. That's
ok, but the change in behavior should be mentioned.
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Change subject: lenovo/x230: introduce FHD variant
......................................................................
Patch Set 22:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/28950/comment/60345aca_7e50b5dc
PS22, Line 14: uses the same method of enabling the custom eDP panel.
If there was a single way a mod could do it or if this change
would document what mod in what configuration was tested, it
would have been merged years ago, AFAICT.
https://review.coreboot.org/c/coreboot/+/28950/comment/e1ea45b2_f107ec21
PS22, Line 18: brightness controls to work out of the box.
This seems misleading. Yes, it "allows" things to work OOB. But it
doesn't always work OOB. The nitrocaster mod in its default confi-
guration, for instance, is designed to work without firmware modi-
fications and doesn't work well if the firmware is adapted, AIUI.
https://review.coreboot.org/c/coreboot/+/28950/comment/2bbe726e_4a0ebd7c
PS22, Line 24: - Set the DP-3 as internally connected.
This part is missing in the libgfxinit configuration.
File src/mainboard/lenovo/x230/Kconfig:
https://review.coreboot.org/c/coreboot/+/28950/comment/adca0244_3401b880
PS19, Line 26: select GFX_GMA_PANEL_1_ON_EDP if BOARD_LENOVO_X230_EDP
> Done
`_EDP` here means the dedicated eDP port. I assume this needs a `DP3`
default for `config GFX_GMA_PANEL_1_PORT`.
File src/mainboard/lenovo/x230/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/28950/comment/fe1c3f04_a84348d5
PS22, Line 11: bool "ThinkPad X230 eDP Mod (2K/FHD)"
Please add a help text about tested mods and their configuration.
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Change subject: treewide/azalia: Fix 16-bit read and use common functions
......................................................................
Patch Set 9: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61845/comment/6c32b091_d3aab011
PS9, Line 9: Correct the codec mask and read only 16 bits.
: Use common codec_detect() and azalia_audio_init().
Please either format as a list, or do not wrap the line, just because the sentence ends.
https://review.coreboot.org/c/coreboot/+/61845/comment/08296994_787e81a8
PS9, Line 11:
Tested how?
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Change subject: cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
......................................................................
Patch Set 4: Code-Review+1
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Change subject: cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63925/comment/2a391c6a_335eda0c
PS3, Line 7: cbfstool: Add MediaTek fixup
> Maybe more specific: […]
Done
https://review.coreboot.org/c/coreboot/+/63925/comment/7a3dfd5e_2850aeac
PS3, Line 9: bootROM
> Is that the official spelling?
According to https://en.wikipedia.org/wiki/Boot_ROM both "boot ROM" or "bootROM" are valid.
File util/cbfstool/platform_fixups.c:
https://review.coreboot.org/c/coreboot/+/63925/comment/8947979a_8b79204f
PS3, Line 151: ERROR("fixups: MediaTek data size too small: %zu\n", data_size);
> Add a colon after MediaTek, so it doesn’t read as a sentence?
Done
https://review.coreboot.org/c/coreboot/+/63925/comment/a91b33fa_8ed65fde
PS3, Line 173: int
> bool?
Oops.
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Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
Patch Set 3:
(3 comments)
File src/soc/mediatek/mt8186/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/63924/comment/40a868ae_a9e29482
PS2, Line 25: TTB(0x00100000, 28K)
: DMA_COHERENT(0x00107000, 4K)
: TPM_TCPA_LOG(0x00108000, 2K)
: FMAP_CACHE(0x00108800, 2K)
: WATCHDOG_TOMBSTONE(0x00109000, 4)
: CBFS_MCACHE(0x00109004, 16K - 4)
: /* EMPTY(0x0010d000, 4K) */
: STACK(0x0010E000, 7K)
: TIMESTAMP(0x0010FC00, 1K)
: /* MT8186 has 64KB SRAM. */
Done, with slight adjustment.
> STACK 7k-4
From my experiments, the STACK size needs to be a multiple of 16. Neither `7K-4` nor `7K-8` work: the last log was `Jump to BL`, which means that the device got stuck somewhere in bootblock before `console_init()`. The device can boot with `7K-16` though.
ARM64's memlayout.h only requires the address to be 16-byte aligned. I'm not sure if we should also add an extra assertion for the size.
https://review.coreboot.org/c/coreboot/+/63924/comment/da136ef5_33562588
PS2, Line 44: /* 4K reserved for BOOTROM until BOOTBLOCK is started */
> Correction. […]
Done
https://review.coreboot.org/c/coreboot/+/63924/comment/7e5dbe11_6a2d2084
PS2, Line 50: 184K
> aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz […]
Yes, I've mentioned that in the commit message.
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63924
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
......................................................................
soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16K
The per-file hash for CBFS_VERIFICATION, stored as a CBFS file
attribute, would increase the total RO metadata size by 75% (3796->6656
for corsola). Therefore, in order to make RO metadata cache fit into
CBFS_MCACHE, enlarge it from 8K to 16K.
Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K
(only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also
shuffle the regions in SRAM with better comments.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel
BRANCH=none
Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8186/include/soc/memlayout.ld
1 file changed, 22 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63924/3
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