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Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > Practically speaking though, for almost all of these CPUs, the OS will use PATs anyway, and likely disregard the MTRRs.
>
> MTRR setup is already wrong/inefficient on soc/intel (sets up UC for ranges between cbmem_top and TSEG)... On some setups it might make the MTRR caching setup worse such that it slows down the payload a lot if it runs out MTRRs... I'd prefer to avoid possible regressions there.
Adding dedicated MTRR for BIOS/Ext BIOS region might drop a genuine MTRR due to not having sufficient BIOS MTRRs, which might have very bad impact on the boot performance for payload and OS.
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Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree_n.cb:
https://review.coreboot.org/c/coreboot/+/62662/comment/196fd8cf_1b4258f0
PS4, Line 288: device ref ufs on end
> UFS doesn't use a PCIe root port, hence it is not needed to enable the clk.
oh, sorry, I mean mt comment in the issue tracker. https://partnerissuetracker.corp.google.com/issues/228110908#comment2
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Change subject: mb/google/brask/variants/moli: update type-c setting in overridetree for moli
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63570/comment/e477417d_05ae9b69
PS4, Line 12:
any test?
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Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree_n.cb:
https://review.coreboot.org/c/coreboot/+/62662/comment/ac5ef740_47d2c448
PS4, Line 288: device ref ufs on end
> Never mind, please reply my comment.
UFS doesn't use a PCIe root port, hence it is not needed to enable the clk.
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Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62662/comment/1707d652_10971a21
PS1, Line 8:
> Thank you. Maybe also say in the commit message, what UFS is.
Done that in the base patch, hope that works.
Commit Message:
https://review.coreboot.org/c/coreboot/+/62662/comment/3404b864_3288398c
PS4, Line 7: mb/intel/adlrvp: Enable UFS for ADL-N RVP
> ISH should also be mentioned.
Done
https://review.coreboot.org/c/coreboot/+/62662/comment/a7088e50_23ea2d66
PS4, Line 12: Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
> Is this already tested? If so, please paste the excerpt from `lspci -t`.
Done
File src/mainboard/intel/adlrvp/devicetree_n.cb:
https://review.coreboot.org/c/coreboot/+/62662/comment/07a6a8af_5af56653
PS4, Line 288: device ref ufs on end
> as discussed offline, the ufs node should have child "ref_clk" node with the appropriate frequency […]
Sure, will take this up in another CL.
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Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
......................................................................
mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
To enable UFS controller (PCI device 12.7), the parent PCI device 12.0
also needs to be enabled. Hence, enabling ISH too.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1
---
M src/mainboard/intel/adlrvp/devicetree_n.cb
1 file changed, 2 insertions(+), 0 deletions(-)
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Change subject: mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VR
......................................................................
mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VR
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko.
BUG=none
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Change subject: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
......................................................................
mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis.
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Change subject: mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63110/comment/c00b7e43_1ca539b7
PS4, Line 9: Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC for drawcia.
> Do you mean: […]
Done
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