coreboot-gerrit April 2022

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Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Arthur Heymans. Michał Kopeć has uploaded a new patch set (#13) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52781 ) Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ...................................................................... cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution Create the correct MTRR solution based on the physical address space provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not account for lost C6 DRAM storage MTRR during postcar frame creation. The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and overlapping with usable DRAM WB MTRR. However this UC MTRR remained on APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR function to create correct MTRR solution that propagates to APs. This also fixes the inconsistent MTRRs warning. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/cpu/amd/agesa/family14/model_14_init.c 1 file changed, 20 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/52781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Gerrit-Change-Number: 52781 Gerrit-PatchSet: 13 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Arthur Heymans. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52781 ) Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ...................................................................... Patch Set 12: (2 comments) File src/cpu/amd/agesa/family14/model_14_init.c: https://review.coreboot.org/c/coreboot/+/52781/comment/971a5b6c_f3b7c064 PS7, Line 24: if (acpi_is_wakeup_s3()) { : restore_mtrr(); > This will result in different MTRR solutions at resume. It looks like the MTRRs are backed up in `BS_POST_DEVICE` (`amd_bs_post_device`), after they're initialized, so the same solution should be restored here, or am I missing something? https://review.coreboot.org/c/coreboot/+/52781/comment/8d685da1_a4ee4c2b PS7, Line 32: /* : * Enable ROM caching on BSP we just lost when creating MTRR solution, for : * faster execution : */ : if (boot_cpu()) { : mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, : MTRR_TYPE_WRPROT); : } > code is not executed from ROM at this point. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Gerrit-Change-Number: 52781 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 12 Apr 2022 09:37:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14: Enable PARALLEL_MP
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59807 to look at the new patch set (#12). Change subject: nb/amd/agesa/family14: Enable PARALLEL_MP ...................................................................... nb/amd/agesa/family14: Enable PARALLEL_MP Disable LEGACY_SMP_INIT and enable PARALLEL_MP. TEST=Boot Debian 11 on PC Engines apu1 Boot time reduced by ~3ms on average. Inspired by CB:59693 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: I39a0779bdf115eebe31290591152b920acde773e --- M src/cpu/amd/agesa/family14/model_14_init.c M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family14/northbridge.c 3 files changed, 23 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/59807/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/59807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a0779bdf115eebe31290591152b920acde773e Gerrit-Change-Number: 59807 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
by Michał Kopeć (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Michał Kopeć has uploaded a new patch set (#12) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/52781 ) Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ...................................................................... cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution Create the correct MTRR solution based on the physical address space provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not account for lost C6 DRAM storage MTRR during postcar frame creation. The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and overlapping with usable DRAM WB MTRR. However this UC MTRR remained on APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR function to create correct MTRR solution that propagates to APs. This also fixes the inconsistent MTRRs warning. TEST=boot Debian with Linux 4.14 on apu1 2GB Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/cpu/amd/agesa/family14/model_14_init.c 1 file changed, 22 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/52781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be Gerrit-Change-Number: 52781 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: set RFI Spread Spectrum to 6%
by Paul Menzel (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak, Robert Chen. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63440 ) Change subject: mb/google/brya/var/vell: set RFI Spread Spectrum to 6% ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63440/comment/a4389004_f1fb3185 PS6, Line 7: set Increase https://review.coreboot.org/c/coreboot/+/63440/comment/6400165f_f68a399b PS6, Line 10: The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard Please add a blank line above, or do not wrap the line only because it’s the end of the sentence. https://review.coreboot.org/c/coreboot/+/63440/comment/6752a873_a78f74c8 PS6, Line 14: TEST=emerge-brya coreboot and pass RF test Did it fail the RF test before? -- To view, visit https://review.coreboot.org/c/coreboot/+/63440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Gerrit-Change-Number: 63440 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 08:53:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: set RFI Spread Spectrum to 6%
by Robert Chen (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63440 to look at the new patch set (#6). Change subject: mb/google/brya/var/vell: set RFI Spread Spectrum to 6% ...................................................................... mb/google/brya/var/vell: set RFI Spread Spectrum to 6% Set RFI Spread Spectrum to 6% for Redrix as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63440/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Gerrit-Change-Number: 63440 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/vell: set RFI Spread Spectrum to 6%
by Robert Chen (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak, Robert Chen. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63440 ) Change subject: mb/google/brya/var/vell: set RFI Spread Spectrum to 6% ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/63440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Gerrit-Change-Number: 63440 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Apr 2022 08:50:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_c...
by Kevin Chiu (Code Review) 12 Apr '22

12 Apr '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63575 ) Change subject: mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_config ...................................................................... mb/google/guybrush/var/nipperkin: probe privacy screen device by fw_config BUG=b:228448327 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage check ACPI device "LCD" in SSDT Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377 --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63575/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 6d6285a..85581d2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -188,7 +188,9 @@ register "device[0].addr" = "0x80010400" register "device[0].privacy.enabled" = "1" register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_18)" - device generic 0.0 on end + device generic 0.0 on + probe KB_MAP KB_MAP_PRIVACY + end end end device ref acp on -- To view, visit https://review.coreboot.org/c/coreboot/+/63575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42c5abdbe3bfab72016d56399278a7aff9e33377 Gerrit-Change-Number: 63575 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr.c: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 2: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/63555/comment/f1190926_1bfb046c PS2, Line 912: memranges_teardown(&addr_space); this can't be happening either... -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 12 Apr 2022 08:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage
by Subrata Banik (Code Review) 12 Apr '22

12 Apr '22

Attention is currently required from: Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63550 ) Change subject: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > > > > I will test this CL once again. > > > > > > > > here is my feedback. > > > > > > > > 1. MTRR snapshot with this CL that uses `mtrr_use_temp_range` > > > > > > > > `mtrr_use_temp_range` function will clear the previous > > > > > > > > Every time BIOS calls mtrr_use_temp_range, it will get a fresh new addr_space see this https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… > > > > > > > > so `fast_spi_enable_cache_range` tries to allocate BIOS and ext BIOS region by using mtrr_use_temp_range, but eventually, only ext BIOS region is allocated in MTRR since mtrr_use_temp_range doesn't keep the addr_space last time it's called(for BIOS region) > > > > > > > > check this, only ext BIOS region is part of MTRR snapshot not the BIOS region unfortunately. > > > > > > > > [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB > > > > [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid > > > > [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC > > > > [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid > > > > [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC > > > > [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid > > > > [DEBUG] 0x00000000f9000005: PHYBASE3: Address = 0x00000000f9000000, WP > > > > [DEBUG] 0x00003fffff000800: PHYMASK3: Length = 0x0000000001000000, Valid > > > > [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB > > > > [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid > > > > [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB > > > > [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid > > > > [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC > > > > [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid > > > > [DEBUG] 0x0000000000000000: PHYBASE7 > > > > [DEBUG] 0x0000000000000000: PHYMASK7: Disabled > > > > [DEBUG] 0x0000000000000000: PHYBASE8 > > > > [DEBUG] 0x0000000000000000: PHYMASK8: Disabled > > > > [DEBUG] 0x0000000000000000: PHYBASE9 > > > > [DEBUG] 0x0000000000000000: PHYMASK9: Disabled > > > > > > > > 2. MTRR snapshot CB:63492 > > > > > > > > Before clearing the temp MTRRs, you can see those rom cache MTRRs are not applied. > > > > > > > > [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB > > > > [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid > > > > [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC > > > > [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid > > > > [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC > > > > [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid > > > > [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC > > > > [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid > > > > [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB > > > > [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid > > > > [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB > > > > [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid > > > > [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC > > > > [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid > > > > [DEBUG] 0x00000000ff000005: PHYBASE7: Address = 0x00000000ff000000, WP > > > > [DEBUG] 0x00003fffff000800: PHYMASK7: Length = 0x0000000001000000, Valid > > > > [DEBUG] 0x00000000f9000005: PHYBASE8: Address = 0x00000000f9000000, WP > > > > [DEBUG] 0x00003fffff000800: PHYMASK8: Length = 0x0000000001000000, Valid > > > > [DEBUG] 0x0000000000000000: PHYBASE9 > > > > [DEBUG] 0x0000000000000000: PHYMASK9: Disabled > > > > > > > > > > > > After clearing the temp MTRRs (prior to boot to payload) > > > > > > > > [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB > > > > [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid > > > > [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC > > > > [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid > > > > [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC > > > > [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid > > > > [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC > > > > [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid > > > > [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB > > > > [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid > > > > [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB > > > > [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid > > > > [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC > > > > [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid > > > > [DEBUG] 0x0000000000000000: PHYBASE7 > > > > [DEBUG] 0x0000000000000000: PHYMASK7: Disabled > > > > [DEBUG] 0x0000000000000000: PHYBASE8 > > > > [DEBUG] 0x0000000000000000: PHYMASK8: Disabled > > > > [DEBUG] 0x0000000000000000: PHYBASE9 > > > > [DEBUG] 0x0000000000000000: PHYMASK9: Disabled > > > > > > in summary, the boot time increased by several seconds with this CL. > > > > You are right. It resets the solution on each invocation. Can you see if CB:63555 fixes that? > > Sure, it's in my list for tomorrow. here is test result with CB:63555, result is not good. [DEBUG] 0x00000000f9000005: PHYBASE0: Address = 0x00000000f9000000, WP [DEBUG] 0x00003fffff000800: PHYMASK0: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000000000000: PHYBASE1 [DEBUG] 0x0000000000000000: PHYMASK1: Disabled [DEBUG] 0x0000000000000000: PHYBASE2 [DEBUG] 0x0000000000000000: PHYMASK2: Disabled [DEBUG] 0x0000000000000000: PHYBASE3 [DEBUG] 0x0000000000000000: PHYMASK3: Disabled [DEBUG] 0x0000000000000000: PHYBASE4 [DEBUG] 0x0000000000000000: PHYMASK4: Disabled [DEBUG] 0x0000000000000000: PHYBASE5 [DEBUG] 0x0000000000000000: PHYMASK5: Disabled [DEBUG] 0x0000000000000000: PHYBASE6 [DEBUG] 0x0000000000000000: PHYMASK6: Disabled [DEBUG] 0x0000000000000000: PHYBASE7 [DEBUG] 0x0000000000000000: PHYMASK7: Disabled [DEBUG] 0x0000000000000000: PHYBASE8 [DEBUG] 0x0000000000000000: PHYMASK8: Disabled [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled -- To view, visit https://review.coreboot.org/c/coreboot/+/63550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Gerrit-Change-Number: 63550 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 12 Apr 2022 07:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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