coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/common/../systemagent: Add sa_get_mchbar_base api
by Angel Pons (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Tim Wawrzynczak, Paul Menzel, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: I commented yesterday: > Oof, this sounds way too inefficient. What's wrong with enabling MCHBAR in bootblock? One could even have a `SOC_INTEL_COMMON_SA_MCHBAR_IN_BOOTBLOCK` Kconfig to decide when to enable MCHBAR. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 12 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 21 Apr 2022 18:01:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Fix buggy code tries to access DESC region
by Sridhar Siricilla (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Sridhar Siricilla, Arthur Heymans. Hello Arthur Heymans, build bot (Jenkins), Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63734 to look at the new patch set (#5). Change subject: soc/intel/common: Fix buggy code tries to access DESC region ...................................................................... soc/intel/common: Fix buggy code tries to access DESC region The patch fixes the buggy code which tries to access the Descriptor Region. The existing code doesn't use correct APIs to access the Descriptor Region. Hence, error message is getting displayed during the boot. BUG=b:229003612 TEST=Build and verify no errors seen while accessing the Descriptor Region. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87 --- M src/soc/intel/common/basecode/debug/debug_feature.c 1 file changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/63734/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87 Gerrit-Change-Number: 63734 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tpm: Allow separate handling of Google Ti50 TPM
by Tim Wawrzynczak (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Jes Klinke, Christian Walter, Angel Pons, Julius Werner, Jett Rink. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63158 ) Change subject: tpm: Allow separate handling of Google Ti50 TPM ...................................................................... Patch Set 16: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/63158/comment/74e6ecff_389e7bc7 PS14, Line 47: TI50 > I see. […] Seems like that would be the case, yes. Do you think it is worth the trouble to do dynamic detection? -- To view, visit https://review.coreboot.org/c/coreboot/+/63158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Gerrit-Change-Number: 63158 Gerrit-PatchSet: 16 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jett Rink <jettrink(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jett Rink <jettrink(a)google.com> Gerrit-Comment-Date: Thu, 21 Apr 2022 17:55:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jes Klinke <jbk(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Raptor Lake device IDs
by Bora Guvendik (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Tim Wawrzynczak, Nick Vaccaro. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 ) Change subject: soc/intel/common: Add Raptor Lake device IDs ...................................................................... Patch Set 2: (1 comment) File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/b30c773d_bcd9dd4f PS1, Line 62: #define CPUID_RAPTORLAKE_J0 0xb06a2 > Which naming convention are you referring to ? I am under the impression other definition preceding […] Ack, yes some do -- To view, visit https://review.coreboot.org/c/coreboot/+/63750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Gerrit-Change-Number: 63750 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 21 Apr 2022 17:46:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VR
by Karthik Ramasubramanian (Code Review) 21 Apr '22

21 Apr '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63111 ) Change subject: mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VR ...................................................................... mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VR Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Henry Sun <henrysun(a)google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/kracko/Makefile.inc A src/mainboard/google/dedede/variants/kracko/ramstage.c 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Henry Sun: Looks good to me, but someone else must approve Shou-Chieh Hsu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/kracko/Makefile.inc b/src/mainboard/google/dedede/variants/kracko/Makefile.inc index a722a06..d4d5a24 100644 --- a/src/mainboard/google/dedede/variants/kracko/Makefile.inc +++ b/src/mainboard/google/dedede/variants/kracko/Makefile.inc @@ -4,4 +4,6 @@ ramstage-y += gpio.c +ramstage-y += ramstage.c + smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/kracko/ramstage.c b/src/mainboard/google/dedede/variants/kracko/ramstage.c new file mode 100644 index 0000000..255e585 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/ramstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <fw_config.h> +#include <soc/soc_chip.h> + +static void ext_vr_update(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_ABSENT))) + cfg->disable_external_bypass_vr = 1; +} + +void variant_devtree_update(void) +{ + ext_vr_update(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef Gerrit-Change-Number: 63111 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR
by Karthik Ramasubramanian (Code Review) 21 Apr '22

21 Apr '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63110 ) Change subject: mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR ...................................................................... mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VR Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia. BUG=b:223687184 TEST=emerge-dedede coreboot Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Henry Sun <henrysun(a)google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/ramstage.c 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Henry Sun: Looks good to me, but someone else must approve Shou-Chieh Hsu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/drawcia/ramstage.c b/src/mainboard/google/dedede/variants/drawcia/ramstage.c index 26f1532..aed160e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/ramstage.c +++ b/src/mainboard/google/dedede/variants/drawcia/ramstage.c @@ -4,6 +4,15 @@ #include <boardid.h> #include <device/device.h> #include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <soc/soc_chip.h> + +static void ext_vr_update(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_ABSENT))) + cfg->disable_external_bypass_vr = 1; +} void variant_devtree_update(void) { @@ -21,4 +30,5 @@ config = config_of(lte_usb2); config->reset_gpio = lte_reset_gpio; + ext_vr_update(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Gerrit-Change-Number: 63110 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR
by Karthik Ramasubramanian (Code Review) 21 Apr '22

21 Apr '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63112 ) Change subject: mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR ...................................................................... mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VR Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- A src/mainboard/google/dedede/variants/lantis/Makefile.inc A src/mainboard/google/dedede/variants/lantis/ramstage.c 2 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Shou-Chieh Hsu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/lantis/Makefile.inc b/src/mainboard/google/dedede/variants/lantis/Makefile.inc new file mode 100644 index 0000000..2a9206c --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += ramstage.c diff --git a/src/mainboard/google/dedede/variants/lantis/ramstage.c b/src/mainboard/google/dedede/variants/lantis/ramstage.c new file mode 100644 index 0000000..255e585 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/ramstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <fw_config.h> +#include <soc/soc_chip.h> + +static void ext_vr_update(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_ABSENT))) + cfg->disable_external_bypass_vr = 1; +} + +void variant_devtree_update(void) +{ + ext_vr_update(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Gerrit-Change-Number: 63112 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/smbus: Add `finalize` operation for smbus
by Subrata Banik (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Lean Sheng Tan, Eric Lai, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63640 ) Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/smbus/smbus.c: https://review.coreboot.org/c/coreboot/+/63640/comment/a71f2f19_2ea5b33a PS5, Line 77: tco_lockdown(); > > > > t's important to ensure that TCO base address is locked before running 3rd party code > > > > > > Then it's already too late? running option ROMs happens during PCI device initialization (.init), so by .final, it's already happened. > > > > Valid point Tim, IMO, we should bind this with a bootstate which is equivalent to (.enable) entry. WDYT ? > > That would be an ubiquitous problem in coreboot... Option roms from external PCI devices are just an insecure setup and should be disabled by default. CB:63763 Thats very nice @Arthur, but can we say, `no` to launching option rom, atleast few DGPU I have worked during my time at Intel, I have to use Option ROM for pre-os display. Reg this CL, are you suggesting, we don't need to protect TCOBASE from 3rd party code, then we don't need to worry? -- To view, visit https://review.coreboot.org/c/coreboot/+/63640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie945680049514e6c5d797790a381a6946e836926 Gerrit-Change-Number: 63640 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 21 Apr 2022 17:37:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Raptor Lake device IDs
by Jérémy Compostella (Code Review) 21 Apr '22

21 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Tim Wawrzynczak, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 ) Change subject: soc/intel/common: Add Raptor Lake device IDs ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63750/comment/15cf8103_b1999c67 PS2, Line 7: soc/intel/common: Add Raptor Lake device IDs Considering the wideness of this patch, I believe `soc/intel` as the header prefix is more appropriate. File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/fffeb297_10fb4170 PS1, Line 62: #define CPUID_RAPTORLAKE_J0 0xb06a2 > I followed the naming convention but CPUID_RAPTORLAKE_P_J0 maybe good idea. […] Which naming convention are you referring to ? I am under the impression other definition preceding this one also include a SKU letter. -- To view, visit https://review.coreboot.org/c/coreboot/+/63750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Gerrit-Change-Number: 63750 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 21 Apr 2022 17:03:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nipperkin: Fix WLAN to GEN2 speed
by Karthik Ramasubramanian (Code Review) 21 Apr '22

21 Apr '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63722 ) Change subject: mb/google/nipperkin: Fix WLAN to GEN2 speed ...................................................................... mb/google/nipperkin: Fix WLAN to GEN2 speed Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing the PSP to hang when resuming from S0ix suspend. The root cause is still under investigation. Just disabling PSPP fixes the hang but causes poor PLT performance. BUG=b:228830362 BRANCH=guybrush TEST=suspend_stress_test on AC and DC Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/nipperkin/variant.c 1 file changed, 9 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kevin Chiu: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index b70545e..48e768d 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -7,7 +7,13 @@ { dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false; - /* Disable PSPP to avoid S0ix hangs - b/228830362 */ - memset(dxio_descriptors[WLAN].port_params, 0, - sizeof(dxio_descriptors[WLAN].port_params)); + + /* Fix link speed to GEN2 - b/228830362 */ + dxio_descriptors[WLAN].link_speed_capability = GEN2; + dxio_descriptors[WLAN].port_params[0] = PP_PSPP_AC; + /* AC_DirectIndirect[11:8], AC_MaxPreferredSpeed[7:4], AC_MinPreferredSpeed[3:0] */ + dxio_descriptors[WLAN].port_params[1] = 0x122; + dxio_descriptors[WLAN].port_params[2] = PP_PSPP_DC; + /* DC_DirectIndirect[11:8], DC_MaxPreferredSpeed[7:4], DC_MinPreferredSpeed[3:0] */ + dxio_descriptors[WLAN].port_params[3] = 0x122; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30 Gerrit-Change-Number: 63722 Gerrit-PatchSet: 5 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Nein <finaljason(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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