coreboot-gerrit April 2022

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Change in coreboot[master]: {arch,cpu}: Remove redundant <arch/cpu.h>
by Elyes Haouas (Code Review) 24 Apr '22

24 Apr '22

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60931 to look at the new patch set (#3). Change subject: {arch,cpu}: Remove redundant <arch/cpu.h> ...................................................................... {arch,cpu}: Remove redundant <arch/cpu.h> <arch/cpu.h> is chain included through <cpu/cpu.h>. Change-Id: I54a837394f67ac2a759907c7212ab947d07338dc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/mpspec.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/x86/mp_init.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60931/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/60931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a837394f67ac2a759907c7212ab947d07338dc Gerrit-Change-Number: 60931 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: northbridge/intel: Remove unused <acpi/acpi.h>
by Elyes Haouas (Code Review) 24 Apr '22

24 Apr '22

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Change in coreboot[master]: mainboard/intel: Remove unused <acpi/acpi.h>
by Elyes Haouas (Code Review) 24 Apr '22

24 Apr '22

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Change in coreboot[master]: soc/intel/common: Disable all HECI Interfaces
by Sridhar Siricilla (Code Review) 24 Apr '22

24 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Balaji Manigandan. Hello Subrata Banik, Tim Wawrzynczak, Balaji Manigandan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63806 to look at the new patch set (#2). Change subject: soc/intel/common: Disable all HECI Interfaces ...................................................................... soc/intel/common: Disable all HECI Interfaces The patch disables all the HECI interfaces if system boots in the CrOS recovery mode. When CSE boots in Soft Temporary Disable mode, BIOS is expected to disable all the HECI interfaces. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I452512f01ade7668a9ed1aad8666d04ee7672892 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/63806/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I452512f01ade7668a9ed1aad8666d04ee7672892 Gerrit-Change-Number: 63806 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Disable all HECI Interface
by Sridhar Siricilla (Code Review) 24 Apr '22

24 Apr '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63806 ) Change subject: soc/intel/common: Disable all HECI Interface ...................................................................... soc/intel/common: Disable all HECI Interface The patch disables all the HECI interfaces if system boots in the CrOS recovery mode. When CSE boots in Soft Temporary Disable mode, BIOS is expected to disable all the HECI interfaces. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I452512f01ade7668a9ed1aad8666d04ee7672892 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/63806/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 64fd041..f84a457 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1013,7 +1013,7 @@ { for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { pci_devfn_t devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); - if (!is_cse_devfn_visible(devfn)) + if (!vboot_recovery_mode_enabled() && !is_cse_devfn_visible(devfn)) continue; set_cse_device_state(devfn, DEV_IDLE); -- To view, visit https://review.coreboot.org/c/coreboot/+/63806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I452512f01ade7668a9ed1aad8666d04ee7672892 Gerrit-Change-Number: 63806 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Move services page to infrastructure section
by Felix Singer (Code Review) 24 Apr '22

24 Apr '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62442 ) Change subject: Documentation: Move services page to infrastructure section ...................................................................... Documentation: Move services page to infrastructure section The services page documents various services and tools which are provided by the project. It's more related to the infrastructure and less related to the community section. Thus, move it to the infrastructure section. Change-Id: I0ca2aba8ae817cf874367fa17e567065aec99a93 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62442 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M Documentation/community/index.md M Documentation/infrastructure/index.md R Documentation/infrastructure/services.md 3 files changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/Documentation/community/index.md b/Documentation/community/index.md index 30420ae..1363eb0 100644 --- a/Documentation/community/index.md +++ b/Documentation/community/index.md @@ -3,5 +3,4 @@ * [Code of Conduct](code_of_conduct.md) * [Language style](language_style.md) * [Community forums](forums.md) -* [Project services](services.md) * [coreboot at conferences](conferences.md) diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md index 755709e..744809f 100644 --- a/Documentation/infrastructure/index.md +++ b/Documentation/infrastructure/index.md @@ -2,6 +2,11 @@ This section contains documentation about our infrastructure +## Services + +* [Project services](services.md) + + ## Jenkins builders and builds * [Setting up Jenkins build machines](builders.md) * [Coverity Scan integration](coverity.md) diff --git a/Documentation/community/services.md b/Documentation/infrastructure/services.md similarity index 100% rename from Documentation/community/services.md rename to Documentation/infrastructure/services.md 14 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca2aba8ae817cf874367fa17e567065aec99a93 Gerrit-Change-Number: 62442 Gerrit-PatchSet: 16 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Rename infrastructure section
by Felix Singer (Code Review) 24 Apr '22

24 Apr '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62441 ) Change subject: Documentation: Rename infrastructure section ...................................................................... Documentation: Rename infrastructure section In preparation for CB:62442, rename the section for infrastructure related things to "Project infrastructure & services". Change-Id: I1ba8a2e2070a79d8c9e955133203f9bb9f58cb8e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62441 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M Documentation/index.md M Documentation/infrastructure/index.md 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/Documentation/index.md b/Documentation/index.md index 342ef68..aae7861 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -188,6 +188,6 @@ * [SuperIO](superio/index.md) * [Vendorcode](vendorcode/index.md) * [Utilities](util.md) -* [coreboot infrastructure](infrastructure/index.md) +* [Project infrastructure & services](infrastructure/index.md) * [Release notes](releases/index.md) * [Documentation License](documentation_license.md) diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md index 3007bbe..755709e 100644 --- a/Documentation/infrastructure/index.md +++ b/Documentation/infrastructure/index.md @@ -1,6 +1,6 @@ -# coreboot infrastructure +# Project infrastructure & services -This section contains documentation about coreboot infrastructure +This section contains documentation about our infrastructure ## Jenkins builders and builds * [Setting up Jenkins build machines](builders.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/62441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba8a2e2070a79d8c9e955133203f9bb9f58cb8e Gerrit-Change-Number: 62441 Gerrit-PatchSet: 15 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Rename infrastructure section
by Michael Niewöhner (Code Review) 24 Apr '22

24 Apr '22

Attention is currently required from: Felix Singer, Martin L Roth, Thomas Heijligen, Paul Menzel. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62441 ) Change subject: Documentation: Rename infrastructure section ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Patchset: PS14: > Well, didn't help. […] Weeeeell, there's a good reason why it doesn't work that way :P -- To view, visit https://review.coreboot.org/c/coreboot/+/62441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ba8a2e2070a79d8c9e955133203f9bb9f58cb8e Gerrit-Change-Number: 62441 Gerrit-PatchSet: 14 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 24 Apr 2022 18:39:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/psp_verstage: Add platform_report_boot_mode API
by Martin L Roth (Code Review) 24 Apr '22

24 Apr '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63730 ) Change subject: soc/amd/sabrina/psp_verstage: Add platform_report_boot_mode API ...................................................................... soc/amd/sabrina/psp_verstage: Add platform_report_boot_mode API PSP verstage uses this API to report PSP regarding the platform boot mode. PSP in turn uses the boot mode to either maintain or clean DRM credentials. BUG=None TEST=Build Skyrim BIOS image with PSP verstage enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ie13b42b349f5c77322d904b68d5f53a3aed58fc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63730 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/psp_verstage/chipset.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/psp_verstage/chipset.c b/src/soc/amd/sabrina/psp_verstage/chipset.c index e82a132..7f86dbf 100644 --- a/src/soc/amd/sabrina/psp_verstage/chipset.c +++ b/src/soc/amd/sabrina/psp_verstage/chipset.c @@ -3,6 +3,7 @@ /* TODO: Check if this is still correct */ #include <bl_uapp/bl_syscall_public.h> +#include <console/console.h> #include <psp_verstage.h> uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) @@ -44,3 +45,13 @@ { return 0; } + +void platform_report_mode(int developer_mode_enabled) +{ + printk(BIOS_INFO, "Reporting %s mode\n", + developer_mode_enabled ? "Developer" : "Normal"); + if (developer_mode_enabled) + svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_DEVELOPER); + else + svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie13b42b349f5c77322d904b68d5f53a3aed58fc5 Gerrit-Change-Number: 63730 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/psp_verstage: Unify SVC ID
by Martin L Roth (Code Review) 24 Apr '22

24 Apr '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63729 ) Change subject: soc/amd/sabrina/psp_verstage: Unify SVC ID ...................................................................... soc/amd/sabrina/psp_verstage: Unify SVC ID In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands. Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command ID) with individual subcommands and the corresponding parameters. BUG=b:220848545, b:217414563 TEST=Build the Skyrim BIOS image with PSP verstage enabled. Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/psp_verstage/svc.c M src/soc/amd/sabrina/psp_verstage/svc.h M src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h 3 files changed, 220 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/psp_verstage/svc.c b/src/soc/amd/sabrina/psp_verstage/svc.c index bf1a106..370481c 100644 --- a/src/soc/amd/sabrina/psp_verstage/svc.c +++ b/src/soc/amd/sabrina/psp_verstage/svc.c @@ -1,13 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #include "svc.h" #include <assert.h> #include <bl_uapp/bl_syscall_public.h> #include <psp_verstage.h> #include <stddef.h> +#include <string.h> void svc_exit(uint32_t status) { @@ -18,33 +17,52 @@ void svc_debug_print(const char *string) { uint32_t unused = 0; - SVC_CALL1(SVC_DEBUG_PRINT, (uint32_t)string, unused); + struct cmd_param_debug param = { + .debug_buffer = (char *)string, + .debug_buffer_len = strlen(string), + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT, (void *)&param, unused); } void svc_debug_print_ex(uint32_t dword0, uint32_t dword1, uint32_t dword2, uint32_t dword3) { uint32_t unused = 0; - SVC_CALL4(SVC_DEBUG_PRINT_EX, dword0, dword1, dword2, dword3, unused); + struct cmd_param_debug_ex param = { + .word0 = dword0, + .word1 = dword1, + .word2 = dword2, + .word3 = dword3, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DEBUG_PRINT_EX, (void *)&param, unused); } uint32_t svc_get_boot_mode(uint32_t *boot_mode) { uint32_t retval = 0; - SVC_CALL1(SVC_GET_BOOT_MODE, boot_mode, retval); + struct cmd_param_get_boot_mode param = { + .ptr_boot_mode = boot_mode, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_BOOT_MODE, (void *)&param, retval); return retval; } void svc_delay_in_usec(uint32_t delay) { uint32_t unused = 0; - SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused); + struct cmd_param_delay_in_micro_second param = { + .delay = delay, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_DELAY_IN_MICRO_SECONDS, (void *)&param, unused); } uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info) { uint32_t retval = 0; - SVC_CALL1(SVC_GET_SPI_INFO, (uint32_t)spi_rom_info, retval); + struct cmd_param_spirom_info param = { + .ptr_spirom_info = spi_rom_info, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_SPI_INFO, (void *)&param, retval); return retval; } @@ -52,18 +70,26 @@ uint32_t arg1, uint32_t arg2, void **io_device_axi_addr) { uint32_t retval = 0; + struct cmd_param_map_fch_io_device param = { + .io_device = io_device, + .arg1 = arg1, + .arg2 = arg2, + .pptr_io_device_addr_axi = io_device_axi_addr, + }; assert(io_device < FCH_IO_DEVICE_END); - SVC_CALL4(SVC_MAP_FCH_IO_DEVICE, io_device, arg1, arg2, - (uint32_t)io_device_axi_addr, retval); + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_FCH_IO_DEVICE, (void *)&param, retval); return retval; } uint32_t svc_unmap_fch_dev(enum fch_io_device io_device, void *io_device_axi_addr) { uint32_t retval = 0; + struct cmd_param_unmap_fch_io_device param = { + .io_device = io_device, + .ptr_io_device_addr_axi = io_device_axi_addr, + }; assert(io_device < FCH_IO_DEVICE_END); - SVC_CALL2(SVC_UNMAP_FCH_IO_DEVICE, (uint32_t)io_device, - (uint32_t)io_device_axi_addr, retval); + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_FCH_IO_DEVICE, (void *)&param, retval); return retval; } @@ -71,15 +97,22 @@ uint32_t size, void **spi_rom_axi_addr) { uint32_t retval = 0; - SVC_CALL3(SVC_MAP_SPIROM_DEVICE, spi_rom_addr, size, - (uint32_t)spi_rom_axi_addr, retval); + struct cmd_param_map_spirom param = { + .spirom_addr = (uintptr_t)spi_rom_addr, + .size = size, + .ppspirom_addr_axi = spi_rom_axi_addr, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MAP_SPIROM_DEVICE, (void *)&param, retval); return retval; } uint32_t svc_unmap_spi_rom(void *spi_rom_addr) { uint32_t retval = 0; - SVC_CALL1(SVC_UNMAP_SPIROM_DEVICE, (uint32_t)spi_rom_addr, retval); + struct cmd_param_unmap_spirom param = { + .ptr_spirom_addr_axi = spi_rom_addr, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UNMAP_SPIROM_DEVICE, (void *)&param, retval); return retval; } @@ -87,51 +120,86 @@ uint32_t *bios_dir_offset) { uint32_t retval = 0; - SVC_CALL2(SVC_UPDATE_PSP_BIOS_DIR, (uint32_t)psp_dir_offset, - (uint32_t)bios_dir_offset, retval); + struct cmd_param_psp_update param = { + .ptr_psp_dir_addr = psp_dir_offset, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_UPDATE_PSP_BIOS_DIR, (void *)&param, retval); return retval; } uint32_t svc_save_uapp_data(void *address, uint32_t size) { uint32_t retval = 0; - SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval); + struct cmd_param_copy_data_from_uapp param = { + .address = (uintptr_t)address, + .size = size, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_COPY_DATA_FROM_UAPP, (void *)&param, retval); return retval; } uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value) { unsigned int retval = 0; + struct cmd_param_read_timer_val param = { + .timer_type = type, + .ptr_counter_value = counter_value, + }; assert(type < PSP_TIMER_TYPE_MAX); - SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval); + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_READ_TIMER_VAL, (void *)&param, retval); return retval; } uint32_t svc_reset_system(enum reset_type reset_type) { unsigned int retval = 0; + struct cmd_param_reset_system param = { + .reset_type = reset_type, + }; assert(reset_type < RESET_TYPE_MAX); - SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval); + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_RESET_SYSTEM, (void *)&param, retval); return retval; } uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode) { uint32_t retval = 0; - SVC_CALL2(SVC_SHA, sha_op, sha_mode, retval); + struct cmd_param_sha param = { + .ptr_sha_op = sha_op, + .sha_mode = sha_mode, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SHA, (void *)&param, retval); return retval; } uint32_t svc_modexp(struct mod_exp_params *mod_exp_param) { uint32_t retval = 0; - SVC_CALL1(SVC_MODEXP, mod_exp_param, retval); + struct cmd_param_modexp param = { + .ptr_modexp = mod_exp_param, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_MODEXP, (void *)&param, retval); return retval; } uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size) { uint32_t retval = 0; - SVC_CALL3(SVC_CCP_DMA, spi_rom_offset, dest, size, retval); + struct cmd_param_ccp_dma param = { + .spi_offset = spi_rom_offset, + .dst_addr = (uintptr_t)dest, + .size = size, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_CCP_DMA, (void *)&param, retval); + return retval; +} + +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode) +{ + uint32_t retval = 0; + struct cmd_param_set_platform_boot_mode param = { + .boot_mode = boot_mode, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_PLATFORM_BOOT_MODE, (void *)&param, retval); return retval; } diff --git a/src/soc/amd/sabrina/psp_verstage/svc.h b/src/soc/amd/sabrina/psp_verstage/svc.h index 86e533a..40dbc3e 100644 --- a/src/soc/amd/sabrina/psp_verstage/svc.h +++ b/src/soc/amd/sabrina/psp_verstage/svc.h @@ -5,6 +5,9 @@ #ifndef PSP_VERSTAGE_SVC_H #define PSP_VERSTAGE_SVC_H +#include <bl_uapp/bl_syscall_public.h> +#include <types.h> + #define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ __asm__ __volatile__ ( \ "mov r0, %[reg0]\n\t" \ @@ -56,4 +59,87 @@ : [id] "I" (SVC_ID) /* input(s) */ \ : "memory", "cc" /* list of clobbered registers */) +struct cmd_param_sha { + struct sha_generic_data *ptr_sha_op; + enum sha_operation_mode sha_mode; +}; + +struct cmd_param_debug { + char *debug_buffer; + uint32_t debug_buffer_len; +}; + +struct cmd_param_debug_ex { + uint32_t word0; + uint32_t word1; + uint32_t word2; + uint32_t word3; +}; + +struct cmd_param_modexp { + struct mod_exp_params *ptr_modexp; +}; + +struct cmd_param_psp_update { + unsigned int *ptr_psp_dir_addr; +}; + +struct cmd_param_spirom_info { + struct spirom_info *ptr_spirom_info; +}; + +struct cmd_param_map_spirom { + unsigned int spirom_addr; + unsigned int size; + void **ppspirom_addr_axi; +}; + +struct cmd_param_unmap_spirom { + void *ptr_spirom_addr_axi; +}; + +struct cmd_param_read_timer_val { + enum psp_timer_type timer_type; + uint64_t *ptr_counter_value; +}; + +struct cmd_param_delay_in_micro_second { + uint32_t delay; +}; + +struct cmd_param_reset_system { + enum reset_type reset_type; +}; + +struct cmd_param_get_boot_mode { + unsigned int *ptr_boot_mode; +}; + +struct cmd_param_copy_data_from_uapp { + unsigned int address; + unsigned int size; +}; + +struct cmd_param_map_fch_io_device { + enum fch_io_device io_device; + unsigned int arg1; + unsigned int arg2; + void **pptr_io_device_addr_axi; +}; + +struct cmd_param_unmap_fch_io_device { + enum fch_io_device io_device; + void *ptr_io_device_addr_axi; +}; + +struct cmd_param_ccp_dma { + uint32_t spi_offset; + uint32_t dst_addr; + uint32_t size; +}; + +struct cmd_param_set_platform_boot_mode { + uint32_t boot_mode; +}; + #endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h index 06e9def..48c35e5 100644 --- a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h @@ -32,24 +32,29 @@ #include <stdint.h> -#define SVC_EXIT 0x00 -#define SVC_ENTER 0x02 -#define SVC_DEBUG_PRINT 0x06 -#define SVC_MODEXP 0x0C -#define SVC_DEBUG_PRINT_EX 0x1A -#define SVC_GET_BOOT_MODE 0x1C -#define SVC_DELAY_IN_MICRO_SECONDS 0x2F -#define SVC_GET_SPI_INFO 0x60 -#define SVC_MAP_SPIROM_DEVICE 0x61 -#define SVC_UNMAP_SPIROM_DEVICE 0x62 -#define SVC_MAP_FCH_IO_DEVICE 0x63 -#define SVC_UNMAP_FCH_IO_DEVICE 0x64 -#define SVC_UPDATE_PSP_BIOS_DIR 0x65 -#define SVC_COPY_DATA_FROM_UAPP 0x66 -#define SVC_RESET_SYSTEM 0x67 -#define SVC_READ_TIMER_VAL 0x68 -#define SVC_SHA 0x69 -#define SVC_CCP_DMA 0x6A +#define SVC_EXIT 0x00 +#define SVC_ENTER 0x02 +#define SVC_VERSTAGE_CMD 0x3A + +enum verstage_cmd_id { + CMD_SHA = 1, + CMD_MODEXP, + CMD_DEBUG_PRINT, + CMD_DEBUG_PRINT_EX, + CMD_UPDATE_PSP_BIOS_DIR, + CMD_GET_SPI_INFO, + CMD_MAP_SPIROM_DEVICE, + CMD_UNMAP_SPIROM_DEVICE, + CMD_READ_TIMER_VAL, + CMD_DELAY_IN_MICRO_SECONDS, + CMD_RESET_SYSTEM, + CMD_GET_BOOT_MODE, + CMD_COPY_DATA_FROM_UAPP, + CMD_MAP_FCH_IO_DEVICE, + CMD_UNMAP_FCH_IO_DEVICE, + CMD_CCP_DMA, + CMD_SET_PLATFORM_BOOT_MODE, +}; struct mod_exp_params { char *pExponent; // Exponent address @@ -86,7 +91,6 @@ FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, - FCH_IO_DEVICE_END, }; @@ -136,6 +140,19 @@ }; /* + * This is state that PSP manages internally. + * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_NORMAL in verstage. + */ +enum chrome_platform_boot_mode +{ + NON_CHROME_BOOK_BOOT_MODE = 0x0, + CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE = 0x1, + CHROME_BOOK_BOOT_MODE_NORMAL = 0x2, + CHROME_BOOK_BOOT_MODE_DEVELOPER = 0x3, + CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT = 0x4, // used for boundary check +}; + +/* * Exit to the main Boot Loader. This does not return back to user application. * * Parameters: @@ -313,6 +330,14 @@ */ uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size); +/* + * Get the Platform boot mode from verstage. Normal or developer + * + * Parameters: + * - boot mode + -----------------------------------------------------------------------------*/ +uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/63729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db Gerrit-Change-Number: 63729 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Mohan Viswanathan Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2022