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Change subject: src: Remove unused <console/cbmem_console.h>
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Patch Set 3: Code-Review+2
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Change subject: src: Remove unused <cf9_reset.h>
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Patch Set 2: Code-Review+2
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Change subject: southbridge/intel: Remove unused <acpi/acpi.h>
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Patch Set 4: Code-Review+2
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Change subject: mainboard/intel: Remove unused <acpi/acpi.h>
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Patch Set 5: Code-Review+2
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63807 )
Change subject: util/crossgcc: Update to GCC 11.3
......................................................................
util/crossgcc: Update to GCC 11.3
The GNU Compiler Collection version 11.3 has been released.
GCC 11.3 is a bug-fix release from the GCC 11 branch containing important
fixes for regressions and serious bugs in GCC 11.2 with more than 189 bugs
fixed since the previous release.
coreboot will switch to GCC 12 when everything is stabilized, but in the
meantime, we'll stay on GCC 11.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I1c0aa0952f85afee59a955593c63fcfac756cc60
---
M util/crossgcc/buildgcc
D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum
A util/crossgcc/sum/gcc-11.3.0.tar.xz.cksum
3 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63807/1
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b25b260..26326d8 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -35,7 +35,7 @@
GMP_VERSION=6.2.1
MPFR_VERSION=4.1.0
MPC_VERSION=1.2.1
-GCC_VERSION=11.2.0
+GCC_VERSION=11.3.0
BINUTILS_VERSION=2.37
IASL_VERSION=20220331
# CLANG version number
diff --git a/util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum
deleted file mode 100644
index 071c352..0000000
--- a/util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-f902ccacecf8949978d6261e9f1d034cff73ffdb tarballs/gcc-11.2.0.tar.xz
diff --git a/util/crossgcc/sum/gcc-11.3.0.tar.xz.cksum b/util/crossgcc/sum/gcc-11.3.0.tar.xz.cksum
new file mode 100644
index 0000000..a4d2bd5
--- /dev/null
+++ b/util/crossgcc/sum/gcc-11.3.0.tar.xz.cksum
@@ -0,0 +1 @@
+cf86a48278f9a6f4b03d4390550577b20353b4e9 tarballs/gcc-11.3.0.tar.xz
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63806 )
Change subject: soc/intel/common: Disable all HECI Interfaces
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63806/comment/293cff1c_d93de40a
PS2, Line 7: soc/intel/common: Disable all HECI Interfaces
commit msg and code changes are not matching
heci_set_to_d0i3 is used to put heci devices into D0i3 prior booting to OS. I don't see where its being disabled in this cl?
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