coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Subrata Banik (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Felix Singer, Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62064 ) Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/62064/comment/8a993a6b_06473e77 PS9, Line 634: && (GEN_PMCON_A <= 0xff) > > Trying to avoid SoC name in common code, once added then it will become as a trend like Intel FSP, where common code does the SoC check 😞 > > Agreed > > > I'm trying to add new Kconfig due to maintenance and added the big comment section to explain what is the reason for this additional check. > > I guess you meant `avoid`? yes 😊 > > Is it really that much maintenance? Not sure, I agree. Let see, I have attempted to create one, let me know your feedback. -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 09:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Subrata Banik (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Felix Singer, Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. Hello Felix Singer, build bot (Jenkins), Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Nick Vaccaro, siemens-bot, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62064 to look at the new patch set (#12). Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. And, the PMC device is visible over the PCI bus, so the SoC user selects `SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE` Kconfig. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. And, the PMC device is not visible over the PCI bus and hidden by the FSP. SoC users to select `SOC_INTEL_MEM_MAPPED_GEN_PMCON_A` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c 31 files changed, 63 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62064/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/crota: set up gpio
by Terry Chen (Code Review) 16 Mar '22

16 Mar '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62854 ) Change subject: mb/google/brya/variants/crota: set up gpio ...................................................................... mb/google/brya/variants/crota: set up gpio Set the GPIO configuration of crota BUG=b: Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a --- A src/mainboard/google/brya/variants/crota/Makefile.inc A src/mainboard/google/brya/variants/crota/gpio.c 2 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62854/1 diff --git a/src/mainboard/google/brya/variants/crota/Makefile.inc b/src/mainboard/google/brya/variants/crota/Makefile.inc new file mode 100644 index 0000000..6c29346 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c new file mode 100644 index 0000000..3b7a6f3 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* C3 : SML0CLK ==> SML0_SMBCLK */ + PAD_CFG_GPO(GPP_C3, 0, DEEP), + /* C4 : SML0DATA ==> SML0_SMBDATA */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : I2S_MCLK1_OUT ==> NC */ + PAD_NC(GPP_D19, NONE), + + /* E3 : PROC_GP0 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E7 : PROC_GP1 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_STRAP_P */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + + /* H21 : IMGCLKOUT2 ==> VPRO_STRAP */ + PAD_CFG_GPI(GPP_H21, NONE, DEEP), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + + /* R4 : HDA_RST# ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE,), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* T2 : GPP_T2 ==> eMMC_CFG */ + PAD_CFG_GPI(GPP_T2, NONE, DEEP), + + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_NC(GPP_H13, UP_20K), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a Gerrit-Change-Number: 62854 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp/z220_series: Add Z220 CMT Workstation variant
by Damien Zammit (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Edward O'Callaghan. Damien Zammit has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62809 ) Change subject: mb/hp/z220_series: Add Z220 CMT Workstation variant ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62809/comment/4631db39_a652252d PS2, Line 13: > ad 2.) Yes, an overview of the differences. Done Patchset: PS3: Done File src/mainboard/hp/z220_series/Kconfig: https://review.coreboot.org/c/coreboot/+/62809/comment/e08c45b5_dea37030 PS2, Line 48: default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION > Let’s see what the others say. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Gerrit-Change-Number: 62809 Gerrit-PatchSet: 3 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Wed, 16 Mar 2022 09:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Damien Zammit Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/z220_series: Add Z220 CMT Workstation variant
by Damien Zammit (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Damien Zammit. Hello build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62809 to look at the new patch set (#3). Change subject: mb/hp/z220_series: Add Z220 CMT Workstation variant ...................................................................... mb/hp/z220_series: Add Z220 CMT Workstation variant This is based on previous work done by a good friend of mine. The notable differences between this board and the SFF variant is that: - CMT has 4 more PCI/PCIe ports than SFF. - CMT has 2 more SATA ports than SFF. This commit needs to be boot tested on a Z220 CMT Workstation, (but I suspect it boots to linux). Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/hp/z220_series/Kconfig M src/mainboard/hp/z220_series/Kconfig.name A src/mainboard/hp/z220_series/variants/z220_cmt_workstation/gpio.c A src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb 4 files changed, 199 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/62809/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Gerrit-Change-Number: 62809 Gerrit-PatchSet: 3 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO
by Yu-Ping Wu (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Hung-Te Lin, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Get dram size from CBMEM_ID_MEMINFO ...................................................................... Patch Set 14: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62065/comment/d36a3d65_e38aafa4 PS14, Line 10: should update from calculate it from the mem chip info stored in https://review.coreboot.org/c/coreboot/+/62065/comment/947f3959_8395b2e5 PS14, Line 13: TEST=Build pass on Kingler Did you see the correct "dram size: ..." log? File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/2d034a75_e2fd2bfa PS14, Line 16: p channel https://review.coreboot.org/c/coreboot/+/62065/comment/7c7c7da2_05d7e98c PS14, Line 17: uint64_t size_t https://review.coreboot.org/c/coreboot/+/62065/comment/b9a6b76f_44268625 PS14, Line 20: != NULL Remove -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 14 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 09:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Yu-Ping Wu (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 21: (9 comments) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/e9a2ca56_77251de2 PS21, Line 29: curr_dram_info Please remove this. https://review.coreboot.org/c/coreboot/+/61334/comment/0c403337_d9e96d36 PS21, Line 108: p channel https://review.coreboot.org/c/coreboot/+/61334/comment/18b0236b_0d1a9a65 PS21, Line 110: MEM_CHIP_LPDDR4X Do we use LPDDR4X for all MTK platforms? https://review.coreboot.org/c/coreboot/+/61334/comment/a4ae491a_c4f75970 PS21, Line 117: total_density / mc->num_channels What is this for? https://review.coreboot.org/c/coreboot/+/61334/comment/1647b4bd_85359856 PS21, Line 129: void *mem_region_base struct mem_chip_info *mc; https://review.coreboot.org/c/coreboot/+/61334/comment/32a56b6e_5254ed2d PS21, Line 131: Check if curr_ddr_info is NULL. https://review.coreboot.org/c/coreboot/+/61334/comment/885dd169_444460b7 PS21, Line 132: curr_dram_info *mc https://review.coreboot.org/c/coreboot/+/61334/comment/ad41f79b_0d259688 PS21, Line 134: ASSERT assert(mc); https://review.coreboot.org/c/coreboot/+/61334/comment/098f4ac0_9099c444 PS21, Line 217: ddr_info 1. Why do we want to rename this? 2. The renaming seems unrelated to the cbmem thing. -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 21 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 08:58:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add struct name "channel" for external access
by Hung-Te Lin (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Julius Werner, Xixi Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62850 ) Change subject: libpayload: Add struct name "channel" for external access ...................................................................... Patch Set 2: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/62850/comment/f8240165_0cd4dd0e PS2, Line 18: channel > In C, the struct name will exist in the global scope, so it's better to have a proper prefix. […] I vote for mem_chip_channel, or even mem_chip_info_channel. Longer name, but more clear (and less conflict) due to this is in global scope - especially this is in libpayload that every payloads would include. -- To view, visit https://review.coreboot.org/c/coreboot/+/62850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543 Gerrit-Change-Number: 62850 Gerrit-PatchSet: 2 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 08:45:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add struct name "channel" for external access
by Yu-Ping Wu (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Julius Werner, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62850 ) Change subject: libpayload: Add struct name "channel" for external access ...................................................................... Patch Set 2: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/62850/comment/2a44caf6_53666a0d PS2, Line 18: channel > Maybe the name "channel" is shorter? And the structure is in "mem_chip_info", i think we can ignore […] In C, the struct name will exist in the global scope, so it's better to have a proper prefix. How about mem_channel, which is shorter? -- To view, visit https://review.coreboot.org/c/coreboot/+/62850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543 Gerrit-Change-Number: 62850 Gerrit-PatchSet: 2 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 08:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/z220_series: Add Z220 CMT Workstation variant
by Paul Menzel (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Damien Zammit. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62809 ) Change subject: mb/hp/z220_series: Add Z220 CMT Workstation variant ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62809/comment/9b4ba17e_aa760e77 PS2, Line 13: > 1. It's a new variant. […] ad 2.) Yes, an overview of the differences. File src/mainboard/hp/z220_series/Kconfig: https://review.coreboot.org/c/coreboot/+/62809/comment/f26c824e_d0ba6e04 PS2, Line 48: default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION > All 2 entries? Not worth pushing again IMHO. […] Let’s see what the others say. -- To view, visit https://review.coreboot.org/c/coreboot/+/62809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Gerrit-Change-Number: 62809 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Comment-Date: Wed, 16 Mar 2022 08:29:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Damien Zammit Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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