coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/banshee: Add mic mute switch setting
by Frank Wu (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: John Su, YH Lin, Dtrain Hsu, Ian Feng, Paul Menzel, Nick Vaccaro, Amanda Hwang, Ricky Chang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62804 ) Change subject: mb/google/brya/var/banshee: Add mic mute switch setting ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Hi Google, Would you help merge the CL? Then we can verify the function with CPFE FW. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/62804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Gerrit-Change-Number: 62804 Gerrit-PatchSet: 8 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 09:36:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h>
by Hsuan-ting Chen (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Jack Rosenthal. Hello build bot (Jenkins), Hsuan Ting Chen, Jack Rosenthal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63113 to look at the new patch set (#3). Change subject: commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h> ...................................................................... commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h> The header file <inttypes.h> includes <stdint.h> and defines some additional PRI* macros. Since elog.h and elog.c do not use any of the PRI* macro, we should include <stdint.h> directly. Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/63113/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4 Gerrit-Change-Number: 63113 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h>
by build bot (Jenkins) (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Hsuan-ting Chen, Jack Rosenthal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63113 ) Change subject: commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h> ...................................................................... Patch Set 2: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4 Gerrit-Change-Number: 63113 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Comment-Date: Fri, 25 Mar 2022 09:32:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: support max98390 audio amp
by Rex-BC Chen (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Trevor Wu, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63083 ) Change subject: mb/google/cherry: support max98390 audio amp ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/cherry/chromeos.c: https://review.coreboot.org/c/coreboot/+/63083/comment/8c7164ff_22486c5e PS4, Line 26: > Search "endchoice" in coreboot. is this ok? choice prompt "Speaker AMP for Cherry" default CHERRY_USE_RT1019 config CHERRY_USE_RT1011 bool default n config CHERRY_USE_RT1019 bool default y if BOARD_GOOGLE_CHERRY || BOARD_GOOGLE_TOMATO default n config CHERRY_USE_MAX98390 bool default y if BOARD_GOOGLE_DOJO default n endchoice -- To view, visit https://review.coreboot.org/c/coreboot/+/63083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Gerrit-Change-Number: 63083 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Trevor Wu <trevor.wu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Trevor Wu <trevor.wu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 09:31:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/snb_ivb_workstations: Add Precision T1650 support
by Michał Żygowski (Code Review) 25 Mar '22

25 Mar '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62212 ) Change subject: mb/dell/snb_ivb_workstations: Add Precision T1650 support ...................................................................... mb/dell/snb_ivb_workstations: Add Precision T1650 support Precision is a Mid Tower chassis platform with very similar mainboard to OptiPlex 9010. It has one more PCIe port and a PCI port. It also incorporates C216 chipset instead of Q77 and enables DRAM ECC support. Other changes are related to subsystem ID and fan control initialization. TEST=Boot Dell Precision T1650 and launch Debian 10. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/mainboard/dell/snb_ivb_workstations/Kconfig.name A src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/data.vbt A src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c A src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/include/variant/sch5545_ec_tables.h A src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb 6 files changed, 300 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig index 5d64fd7..8416a0f 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -28,9 +28,11 @@ config MAINBOARD_PART_NUMBER default "OptiPlex 9010" if BOARD_DELL_OPTIPLEX_9010 + default "Precision T1650" if BOARD_DELL_PRECISION_T1650 config VARIANT_DIR default "optiplex_9010_sff" if BOARD_DELL_OPTIPLEX_9010 + default "precision_t1650" if BOARD_DELL_PRECISION_T1650 config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig.name b/src/mainboard/dell/snb_ivb_workstations/Kconfig.name index 51b7030..1176f6a 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig.name @@ -2,3 +2,8 @@ bool "OptiPlex 9010 SFF" select BOARD_DELL_SNB_IVB_WORKSTATIONS select SOUTHBRIDGE_INTEL_BD82X6X + +config BOARD_DELL_PRECISION_T1650 + bool "Dell Precision T1650" + select BOARD_DELL_SNB_IVB_WORKSTATIONS + select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/data.vbt b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/data.vbt new file mode 100644 index 0000000..d1a95e8 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c new file mode 100644 index 0000000..983b7e4 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x1028053a, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x1028053a), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x99130110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a19830), + AZALIA_PIN_CFG(0, 0x19, 0x01a19840), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x01014020), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0221402f), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/include/variant/sch5545_ec_tables.h b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/include/variant/sch5545_ec_tables.h new file mode 100644 index 0000000..7705deb --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/include/variant/sch5545_ec_tables.h @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SCH5545_BOARD_EC_TABLE_H +#define SCH5545_BOARD_EC_TABLE_H + +#include <baseboard/sch5545_ec.h> + +static const ec_chassis_tdp_t ec_hwm_chassis3[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x96, 0x0085, TDP_16 }, + { 0x41, 0x0086, TDP_16 }, + { 0x66, 0x008a, TDP_16 }, + { 0x6b, 0x008b, TDP_16 }, + { 0x65, 0x0090, TDP_COMMON }, + { 0x5c, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0e, 0x00a0, TDP_COMMON }, + { 0x0e, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x86, 0x00af, TDP_COMMON }, + { 0x95, 0x00b0, TDP_COMMON }, + { 0x9a, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x94, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_16 }, + { 0x11, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0x68, 0x0288, TDP_16 }, + { 0x10, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis4[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x99, 0x0085, TDP_32 }, + { 0x96, 0x0085, TDP_16 }, + { 0xbc, 0x0086, TDP_32 }, + { 0x1c, 0x0086, TDP_16 }, + { 0x41, 0x008a, TDP_32 }, + { 0x3d, 0x008a, TDP_16 }, + { 0x63, 0x008b, TDP_32 }, + { 0x6b, 0x008b, TDP_16 }, + { 0x68, 0x0090, TDP_COMMON }, + { 0x5c, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0c, 0x00a0, TDP_COMMON }, + { 0x0c, 0x00a1, TDP_COMMON }, + { 0x72, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x9a, 0x00b0, TDP_COMMON }, + { 0x7c, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x90, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_32 }, + { 0x11, 0x0281, TDP_32 }, + { 0x68, 0x0280, TDP_16 }, + { 0x10, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0xa0, 0x0288, TDP_32 }, + { 0x0f, 0x0289, TDP_32 }, + { 0xd8, 0x0288, TDP_16 }, + { 0x0e, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis5[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x96, 0x0085, TDP_COMMON }, + { 0xbc, 0x0086, TDP_16 }, + { 0x9c, 0x0086, TDP_32 }, + { 0x39, 0x008a, TDP_32 }, + { 0x41, 0x008a, TDP_16 }, + { 0x63, 0x008b, TDP_32 }, + { 0x6b, 0x008b, TDP_16 }, + { 0x5c, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x08, 0x00a0, TDP_COMMON }, + { 0x0c, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x9a, 0x00b0, TDP_COMMON }, + { 0x7c, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x90, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_32 }, + { 0x11, 0x0281, TDP_32 }, + { 0x3c, 0x0280, TDP_16 }, + { 0x0f, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0x28, 0x0288, TDP_32 }, + { 0x0a, 0x0289, TDP_32 }, + { 0x60, 0x0288, TDP_16 }, + { 0x09, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis6[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x99, 0x0085, TDP_32 }, + { 0x96, 0x0085, TDP_16 }, + { 0xec, 0x0086, TDP_32 }, + { 0x9c, 0x0086, TDP_16 }, + { 0x39, 0x008a, TDP_32 }, + { 0x41, 0x008a, TDP_16 }, + { 0x63, 0x008b, TDP_32 }, + { 0x6b, 0x008b, TDP_16 }, + { 0x6d, 0x0090, TDP_COMMON }, + { 0x5c, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0e, 0x00a0, TDP_COMMON }, + { 0x0e, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x98, 0x00b0, TDP_32 }, + { 0x9a, 0x00b0, TDP_16 }, + { 0x9a, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x97, 0x01be, TDP_32 }, + { 0x95, 0x01be, TDP_16 }, + { 0x68, 0x0280, TDP_32 }, + { 0x10, 0x0281, TDP_32 }, + { 0xd8, 0x0280, TDP_16 }, + { 0x0e, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0xe4, 0x0288, TDP_32 }, + { 0x0c, 0x0289, TDP_32 }, + { 0x10, 0x0288, TDP_16 }, + { 0x0e, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +#endif // SCH5545_BOARD_EC_TABLE_H diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb new file mode 100644 index 0000000..9452279 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb @@ -0,0 +1,21 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1028 0x053a inherit + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "sata_port_map" = "0xf" + device pci 1c.2 on # PCIe Port #3 + smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X" + end + device pci 1c.4 on # PCIe Port #5 + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X" + end + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1e.0 on # PCI bridge + smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit" + end + end + end +end 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516 Gerrit-Change-Number: 62212 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload: Add commonlib/bsd/elog dependency
by Hsuan-ting Chen (Code Review) 25 Mar '22

25 Mar '22

Hsuan-ting Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63115 ) Change subject: libpayload: Add commonlib/bsd/elog dependency ...................................................................... libpayload: Add commonlib/bsd/elog dependency Add commonlib/bsd/elog dependency in libpayload. This will allow other payloads (e.g. depthcharge) to implement their own eventlog read and write utilities. Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 --- M payloads/libpayload/include/libpayload.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63115/1 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 8d8336f..6a3d950 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -45,6 +45,7 @@ #include <stdbool.h> #include <libpayload-config.h> #include <cbgfx.h> +#include <commonlib/bsd/elog.h> #include <commonlib/bsd/fmap_serialized.h> #include <ctype.h> #include <die.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/63115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7 Gerrit-Change-Number: 63115 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/dell: Convert OptiPlex 9010 into directory with variants
by Michał Żygowski (Code Review) 25 Mar '22

25 Mar '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62211 ) Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants ...................................................................... mb/dell: Convert OptiPlex 9010 into directory with variants New boards like Dell Precision T1650 will be added as variants, in subsequent commit. They share most of the code, except some EC initialization tables, PCIe port configuration and subsystem ID. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- D src/mainboard/dell/optiplex_9010/Kconfig.name R src/mainboard/dell/snb_ivb_workstations/Kconfig A src/mainboard/dell/snb_ivb_workstations/Kconfig.name R src/mainboard/dell/snb_ivb_workstations/Makefile.inc R src/mainboard/dell/snb_ivb_workstations/acpi/ec.asl R src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl R src/mainboard/dell/snb_ivb_workstations/acpi/superio.asl R src/mainboard/dell/snb_ivb_workstations/board_info.txt R src/mainboard/dell/snb_ivb_workstations/cmos.default R src/mainboard/dell/snb_ivb_workstations/cmos.layout R src/mainboard/dell/snb_ivb_workstations/dsdt.asl R src/mainboard/dell/snb_ivb_workstations/early_init.c R src/mainboard/dell/snb_ivb_workstations/gma-mainboard.ads R src/mainboard/dell/snb_ivb_workstations/gpio.c C src/mainboard/dell/snb_ivb_workstations/hda_verb.c R src/mainboard/dell/snb_ivb_workstations/mainboard.c R src/mainboard/dell/snb_ivb_workstations/romstage.c R src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c R src/mainboard/dell/snb_ivb_workstations/sch5545_ec_early.c R src/mainboard/dell/snb_ivb_workstations/smihandler.c R src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb R src/mainboard/dell/snb_ivb_workstations/variants/baseboard/include/baseboard/sch5545_ec.h R src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/data.vbt R src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c A src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/include/variant/sch5545_ec_tables.h A src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb 26 files changed, 317 insertions(+), 268 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9010/Kconfig.name b/src/mainboard/dell/optiplex_9010/Kconfig.name deleted file mode 100644 index 96707c2..0000000 --- a/src/mainboard/dell/optiplex_9010/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_DELL_OPTIPLEX_9010 - bool "OptiPlex 9010 SFF" diff --git a/src/mainboard/dell/optiplex_9010/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig similarity index 76% rename from src/mainboard/dell/optiplex_9010/Kconfig rename to src/mainboard/dell/snb_ivb_workstations/Kconfig index 01edd24..5d64fd7 100644 --- a/src/mainboard/dell/optiplex_9010/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -1,17 +1,11 @@ -if BOARD_DELL_OPTIPLEX_9010 - -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_DELL_SNB_IVB_WORKSTATIONS + def_bool n select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_C216 select USE_NATIVE_RAMINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 @@ -24,11 +18,25 @@ select PCIEXP_L1_SUB_STATE select DRIVERS_UART_8250IO +if BOARD_DELL_SNB_IVB_WORKSTATIONS + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config MAINBOARD_DIR - default "dell/optiplex_9010" + default "dell/snb_ivb_workstations" config MAINBOARD_PART_NUMBER - default "OptiPlex 9010" + default "OptiPlex 9010" if BOARD_DELL_OPTIPLEX_9010 + +config VARIANT_DIR + default "optiplex_9010_sff" if BOARD_DELL_OPTIPLEX_9010 + +config DEVICETREE + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig.name b/src/mainboard/dell/snb_ivb_workstations/Kconfig.name new file mode 100644 index 0000000..51b7030 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_DELL_OPTIPLEX_9010 + bool "OptiPlex 9010 SFF" + select BOARD_DELL_SNB_IVB_WORKSTATIONS + select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/dell/optiplex_9010/Makefile.inc b/src/mainboard/dell/snb_ivb_workstations/Makefile.inc similarity index 63% rename from src/mainboard/dell/optiplex_9010/Makefile.inc rename to src/mainboard/dell/snb_ivb_workstations/Makefile.inc index 964a7af..a53d8c1 100644 --- a/src/mainboard/dell/optiplex_9010/Makefile.inc +++ b/src/mainboard/dell/snb_ivb_workstations/Makefile.inc @@ -9,12 +9,20 @@ bootblock-y += sch5545_ec_early.c romstage-y += sch5545_ec.c - ramstage-y += sch5545_ec.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + ifeq ($(CONFIG_INCLUDE_SMSC_SCH5545_EC_FW),y) cbfs-files-y += sch5545_ecfw.bin sch5545_ecfw.bin-file := $(call strip_quotes,$(CONFIG_SMSC_SCH5545_EC_FW_FILE)) sch5545_ecfw.bin-type := raw endif + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/dell/optiplex_9010/acpi/ec.asl b/src/mainboard/dell/snb_ivb_workstations/acpi/ec.asl similarity index 100% rename from src/mainboard/dell/optiplex_9010/acpi/ec.asl rename to src/mainboard/dell/snb_ivb_workstations/acpi/ec.asl diff --git a/src/mainboard/dell/optiplex_9010/acpi/platform.asl b/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl similarity index 100% rename from src/mainboard/dell/optiplex_9010/acpi/platform.asl rename to src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl diff --git a/src/mainboard/dell/optiplex_9010/acpi/superio.asl b/src/mainboard/dell/snb_ivb_workstations/acpi/superio.asl similarity index 100% rename from src/mainboard/dell/optiplex_9010/acpi/superio.asl rename to src/mainboard/dell/snb_ivb_workstations/acpi/superio.asl diff --git a/src/mainboard/dell/optiplex_9010/board_info.txt b/src/mainboard/dell/snb_ivb_workstations/board_info.txt similarity index 100% rename from src/mainboard/dell/optiplex_9010/board_info.txt rename to src/mainboard/dell/snb_ivb_workstations/board_info.txt diff --git a/src/mainboard/dell/optiplex_9010/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default similarity index 100% rename from src/mainboard/dell/optiplex_9010/cmos.default rename to src/mainboard/dell/snb_ivb_workstations/cmos.default diff --git a/src/mainboard/dell/optiplex_9010/cmos.layout b/src/mainboard/dell/snb_ivb_workstations/cmos.layout similarity index 100% rename from src/mainboard/dell/optiplex_9010/cmos.layout rename to src/mainboard/dell/snb_ivb_workstations/cmos.layout diff --git a/src/mainboard/dell/optiplex_9010/dsdt.asl b/src/mainboard/dell/snb_ivb_workstations/dsdt.asl similarity index 100% rename from src/mainboard/dell/optiplex_9010/dsdt.asl rename to src/mainboard/dell/snb_ivb_workstations/dsdt.asl diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/snb_ivb_workstations/early_init.c similarity index 96% rename from src/mainboard/dell/optiplex_9010/early_init.c rename to src/mainboard/dell/snb_ivb_workstations/early_init.c index 2ffdf16..4a381df 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/snb_ivb_workstations/early_init.c @@ -7,7 +7,7 @@ #include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545_emi.h> -#include "sch5545_ec.h" +#include <baseboard/sch5545_ec.h> const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 6, 0 }, diff --git a/src/mainboard/dell/optiplex_9010/gma-mainboard.ads b/src/mainboard/dell/snb_ivb_workstations/gma-mainboard.ads similarity index 100% rename from src/mainboard/dell/optiplex_9010/gma-mainboard.ads rename to src/mainboard/dell/snb_ivb_workstations/gma-mainboard.ads diff --git a/src/mainboard/dell/optiplex_9010/gpio.c b/src/mainboard/dell/snb_ivb_workstations/gpio.c similarity index 100% rename from src/mainboard/dell/optiplex_9010/gpio.c rename to src/mainboard/dell/snb_ivb_workstations/gpio.c diff --git a/src/mainboard/dell/optiplex_9010/acpi/ec.asl b/src/mainboard/dell/snb_ivb_workstations/hda_verb.c similarity index 100% copy from src/mainboard/dell/optiplex_9010/acpi/ec.asl copy to src/mainboard/dell/snb_ivb_workstations/hda_verb.c diff --git a/src/mainboard/dell/optiplex_9010/mainboard.c b/src/mainboard/dell/snb_ivb_workstations/mainboard.c similarity index 97% rename from src/mainboard/dell/optiplex_9010/mainboard.c rename to src/mainboard/dell/snb_ivb_workstations/mainboard.c index 25f9196..c321211 100644 --- a/src/mainboard/dell/optiplex_9010/mainboard.c +++ b/src/mainboard/dell/snb_ivb_workstations/mainboard.c @@ -9,7 +9,7 @@ #include <southbridge/intel/common/gpio.h> #include <superio/smsc/sch5545/sch5545.h> -#include "sch5545_ec.h" +#include <baseboard/sch5545_ec.h> #define SIO_PORT 0x2e @@ -64,13 +64,16 @@ printk(BIOS_DEBUG, "Chassis type: "); switch (pin_sts) { case 0: - case 4: printk(BIOS_DEBUG, "MT\n"); break; case 3: case 11: printk(BIOS_DEBUG, "USFF\n"); break; + case 4: + /* As per table in schematics, but don't know what this is */ + printk(BIOS_DEBUG, "Comoros\n"); + break; case 1: case 9: case 5: diff --git a/src/mainboard/dell/optiplex_9010/romstage.c b/src/mainboard/dell/snb_ivb_workstations/romstage.c similarity index 98% rename from src/mainboard/dell/optiplex_9010/romstage.c rename to src/mainboard/dell/snb_ivb_workstations/romstage.c index 889b06d..83c00c7 100644 --- a/src/mainboard/dell/optiplex_9010/romstage.c +++ b/src/mainboard/dell/snb_ivb_workstations/romstage.c @@ -10,7 +10,7 @@ #include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545_emi.h> -#include "sch5545_ec.h" +#include <baseboard/sch5545_ec.h> void mainboard_late_rcba_config(void) { diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c similarity index 64% rename from src/mainboard/dell/optiplex_9010/sch5545_ec.c rename to src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c index 9aa0038..a68f285 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c @@ -10,25 +10,14 @@ #include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545_emi.h> -#include "sch5545_ec.h" +#include <baseboard/sch5545_ec.h> +#include <variant/sch5545_ec_tables.h> #define GPIO_CHASSIS_ID0 1 #define GPIO_CHASSIS_ID1 17 #define GPIO_CHASSIS_ID2 37 #define GPIO_FRONT_PANEL_CHASSIS_DET_L 70 -enum { - TDP_16 = 0x10, - TDP_32 = 0x20, - TDP_COMMON = 0xff, -}; - -typedef struct ec_val_reg_tdp { - uint8_t val; - uint16_t reg; - uint8_t tdp; -} ec_chassis_tdp_t; - static const struct ec_val_reg ec_hwm_init_seq[] = { { 0xa0, 0x02fc }, { 0x32, 0x02fd }, @@ -105,234 +94,6 @@ { 0x03, 0x0071 }, }; -static const ec_chassis_tdp_t ec_hwm_chassis3[] = { - { 0x33, 0x0005, TDP_COMMON }, - { 0x2f, 0x0018, TDP_COMMON }, - { 0x2f, 0x0019, TDP_COMMON }, - { 0x2f, 0x001a, TDP_COMMON }, - { 0x00, 0x0080, TDP_COMMON }, - { 0x00, 0x0081, TDP_COMMON }, - { 0xbb, 0x0083, TDP_COMMON }, - { 0x8a, 0x0085, TDP_16 }, - { 0x2c, 0x0086, TDP_16 }, - { 0x66, 0x008a, TDP_16 }, - { 0x5b, 0x008b, TDP_16 }, - { 0x65, 0x0090, TDP_COMMON }, - { 0x70, 0x0091, TDP_COMMON }, - { 0x86, 0x0092, TDP_COMMON }, - { 0xa4, 0x0096, TDP_COMMON }, - { 0xa4, 0x0097, TDP_COMMON }, - { 0xa4, 0x0098, TDP_COMMON }, - { 0xa4, 0x009b, TDP_COMMON }, - { 0x0e, 0x00a0, TDP_COMMON }, - { 0x0e, 0x00a1, TDP_COMMON }, - { 0x7c, 0x00ae, TDP_COMMON }, - { 0x86, 0x00af, TDP_COMMON }, - { 0x95, 0x00b0, TDP_COMMON }, - { 0x9a, 0x00b3, TDP_COMMON }, - { 0x08, 0x00b6, TDP_COMMON }, - { 0x08, 0x00b7, TDP_COMMON }, - { 0x64, 0x00ea, TDP_COMMON }, - { 0xff, 0x00ef, TDP_COMMON }, - { 0x15, 0x00f8, TDP_COMMON }, - { 0x00, 0x00f9, TDP_COMMON }, - { 0x30, 0x00f0, TDP_COMMON }, - { 0x01, 0x00fd, TDP_COMMON }, - { 0x88, 0x01a1, TDP_COMMON }, - { 0x08, 0x01a2, TDP_COMMON }, - { 0x08, 0x01b1, TDP_COMMON }, - { 0x94, 0x01be, TDP_COMMON }, - { 0x94, 0x0280, TDP_16 }, - { 0x11, 0x0281, TDP_16 }, - { 0x03, 0x0282, TDP_COMMON }, - { 0x0a, 0x0283, TDP_COMMON }, - { 0x80, 0x0284, TDP_COMMON }, - { 0x03, 0x0285, TDP_COMMON }, - { 0x68, 0x0288, TDP_16 }, - { 0x10, 0x0289, TDP_16 }, - { 0x03, 0x028a, TDP_COMMON }, - { 0x0a, 0x028b, TDP_COMMON }, - { 0x80, 0x028c, TDP_COMMON }, - { 0x03, 0x028d, TDP_COMMON }, -}; - -static const ec_chassis_tdp_t ec_hwm_chassis4[] = { - { 0x33, 0x0005, TDP_COMMON }, - { 0x2f, 0x0018, TDP_COMMON }, - { 0x2f, 0x0019, TDP_COMMON }, - { 0x2f, 0x001a, TDP_COMMON }, - { 0x00, 0x0080, TDP_COMMON }, - { 0x00, 0x0081, TDP_COMMON }, - { 0xbb, 0x0083, TDP_COMMON }, - { 0x99, 0x0085, TDP_32 }, - { 0x98, 0x0085, TDP_16 }, - { 0xbc, 0x0086, TDP_32 }, - { 0x1c, 0x0086, TDP_16 }, - { 0x39, 0x008a, TDP_32 }, - { 0x3d, 0x008a, TDP_16 }, - { 0x40, 0x008b, TDP_32 }, - { 0x43, 0x008b, TDP_16 }, - { 0x68, 0x0090, TDP_COMMON }, - { 0x5e, 0x0091, TDP_COMMON }, - { 0x86, 0x0092, TDP_COMMON }, - { 0xa4, 0x0096, TDP_COMMON }, - { 0xa4, 0x0097, TDP_COMMON }, - { 0xa4, 0x0098, TDP_COMMON }, - { 0xa4, 0x009b, TDP_COMMON }, - { 0x0c, 0x00a0, TDP_COMMON }, - { 0x0c, 0x00a1, TDP_COMMON }, - { 0x72, 0x00ae, TDP_COMMON }, - { 0x7c, 0x00af, TDP_COMMON }, - { 0x9a, 0x00b0, TDP_COMMON }, - { 0x7c, 0x00b3, TDP_COMMON }, - { 0x08, 0x00b6, TDP_COMMON }, - { 0x08, 0x00b7, TDP_COMMON }, - { 0x64, 0x00ea, TDP_COMMON }, - { 0xff, 0x00ef, TDP_COMMON }, - { 0x15, 0x00f8, TDP_COMMON }, - { 0x00, 0x00f9, TDP_COMMON }, - { 0x30, 0x00f0, TDP_COMMON }, - { 0x01, 0x00fd, TDP_COMMON }, - { 0x88, 0x01a1, TDP_COMMON }, - { 0x08, 0x01a2, TDP_COMMON }, - { 0x08, 0x01b1, TDP_COMMON }, - { 0x90, 0x01be, TDP_COMMON }, - { 0x94, 0x0280, TDP_32 }, - { 0x11, 0x0281, TDP_32 }, - { 0x68, 0x0280, TDP_16 }, - { 0x10, 0x0281, TDP_16 }, - { 0x03, 0x0282, TDP_COMMON }, - { 0x0a, 0x0283, TDP_COMMON }, - { 0x80, 0x0284, TDP_COMMON }, - { 0x03, 0x0285, TDP_COMMON }, - { 0xa0, 0x0288, TDP_32 }, - { 0x0f, 0x0289, TDP_32 }, - { 0xd8, 0x0288, TDP_16 }, - { 0x0e, 0x0289, TDP_16 }, - { 0x03, 0x028a, TDP_COMMON }, - { 0x0a, 0x028b, TDP_COMMON }, - { 0x80, 0x028c, TDP_COMMON }, - { 0x03, 0x028d, TDP_COMMON }, -}; - -static const ec_chassis_tdp_t ec_hwm_chassis5[] = { - { 0x33, 0x0005, TDP_COMMON }, - { 0x2f, 0x0018, TDP_COMMON }, - { 0x2f, 0x0019, TDP_COMMON }, - { 0x2f, 0x001a, TDP_COMMON }, - { 0x00, 0x0080, TDP_COMMON }, - { 0x00, 0x0081, TDP_COMMON }, - { 0xbb, 0x0083, TDP_COMMON }, - { 0x89, 0x0085, TDP_32 }, - { 0x99, 0x0085, TDP_16 }, - { 0x9c, 0x0086, TDP_COMMON }, - { 0x39, 0x008a, TDP_32 }, - { 0x42, 0x008a, TDP_16 }, - { 0x6b, 0x008b, TDP_32 }, - { 0x74, 0x008b, TDP_16 }, - { 0x5e, 0x0091, TDP_COMMON }, - { 0x86, 0x0092, TDP_COMMON }, - { 0xa4, 0x0096, TDP_COMMON }, - { 0xa4, 0x0097, TDP_COMMON }, - { 0xa4, 0x0098, TDP_COMMON }, - { 0xa4, 0x009b, TDP_COMMON }, - { 0x0c, 0x00a0, TDP_COMMON }, - { 0x0c, 0x00a1, TDP_COMMON }, - { 0x7c, 0x00ae, TDP_COMMON }, - { 0x7c, 0x00af, TDP_COMMON }, - { 0x9a, 0x00b0, TDP_COMMON }, - { 0x7c, 0x00b3, TDP_COMMON }, - { 0x08, 0x00b6, TDP_COMMON }, - { 0x08, 0x00b7, TDP_COMMON }, - { 0x64, 0x00ea, TDP_COMMON }, - { 0xff, 0x00ef, TDP_COMMON }, - { 0x15, 0x00f8, TDP_COMMON }, - { 0x00, 0x00f9, TDP_COMMON }, - { 0x30, 0x00f0, TDP_COMMON }, - { 0x01, 0x00fd, TDP_COMMON }, - { 0x88, 0x01a1, TDP_COMMON }, - { 0x08, 0x01a2, TDP_COMMON }, - { 0x08, 0x01b1, TDP_COMMON }, - { 0x90, 0x01be, TDP_COMMON }, - { 0x94, 0x0280, TDP_32 }, - { 0x11, 0x0281, TDP_32 }, - { 0x3c, 0x0280, TDP_16 }, - { 0x0f, 0x0281, TDP_16 }, - { 0x03, 0x0282, TDP_COMMON }, - { 0x0a, 0x0283, TDP_COMMON }, - { 0x80, 0x0284, TDP_COMMON }, - { 0x03, 0x0285, TDP_COMMON }, - { 0x60, 0x0288, TDP_32 }, - { 0x09, 0x0289, TDP_32 }, - { 0x98, 0x0288, TDP_16 }, - { 0x08, 0x0289, TDP_16 }, - { 0x03, 0x028a, TDP_COMMON }, - { 0x0a, 0x028b, TDP_COMMON }, - { 0x80, 0x028c, TDP_COMMON }, - { 0x03, 0x028d, TDP_COMMON }, -}; - -static const ec_chassis_tdp_t ec_hwm_chassis6[] = { - { 0x33, 0x0005, TDP_COMMON }, - { 0x2f, 0x0018, TDP_COMMON }, - { 0x2f, 0x0019, TDP_COMMON }, - { 0x2f, 0x001a, TDP_COMMON }, - { 0x00, 0x0080, TDP_COMMON }, - { 0x00, 0x0081, TDP_COMMON }, - { 0xbb, 0x0083, TDP_COMMON }, - { 0x99, 0x0085, TDP_32 }, - { 0x98, 0x0085, TDP_16 }, - { 0xdc, 0x0086, TDP_32 }, - { 0x9c, 0x0086, TDP_16 }, - { 0x3d, 0x008a, TDP_32 }, - { 0x43, 0x008a, TDP_16 }, - { 0x4e, 0x008b, TDP_32 }, - { 0x47, 0x008b, TDP_16 }, - { 0x6d, 0x0090, TDP_COMMON }, - { 0x5f, 0x0091, TDP_32 }, - { 0x61, 0x0091, TDP_16 }, - { 0x86, 0x0092, TDP_COMMON }, - { 0xa4, 0x0096, TDP_COMMON }, - { 0xa4, 0x0097, TDP_COMMON }, - { 0xa4, 0x0098, TDP_COMMON }, - { 0xa4, 0x009b, TDP_COMMON }, - { 0x0e, 0x00a0, TDP_COMMON }, - { 0x0e, 0x00a1, TDP_COMMON }, - { 0x7c, 0x00ae, TDP_COMMON }, - { 0x7c, 0x00af, TDP_COMMON }, - { 0x98, 0x00b0, TDP_32 }, - { 0x9a, 0x00b0, TDP_16 }, - { 0x9a, 0x00b3, TDP_COMMON }, - { 0x08, 0x00b6, TDP_COMMON }, - { 0x08, 0x00b7, TDP_COMMON }, - { 0x64, 0x00ea, TDP_COMMON }, - { 0xff, 0x00ef, TDP_COMMON }, - { 0x15, 0x00f8, TDP_COMMON }, - { 0x00, 0x00f9, TDP_COMMON }, - { 0x30, 0x00f0, TDP_COMMON }, - { 0x01, 0x00fd, TDP_COMMON }, - { 0x88, 0x01a1, TDP_COMMON }, - { 0x08, 0x01a2, TDP_COMMON }, - { 0x08, 0x01b1, TDP_COMMON }, - { 0x97, 0x01be, TDP_32 }, - { 0x95, 0x01be, TDP_16 }, - { 0x68, 0x0280, TDP_32 }, - { 0x10, 0x0281, TDP_32 }, - { 0xd8, 0x0280, TDP_16 }, - { 0x0e, 0x0281, TDP_16 }, - { 0x03, 0x0282, TDP_COMMON }, - { 0x0a, 0x0283, TDP_COMMON }, - { 0x80, 0x0284, TDP_COMMON }, - { 0x03, 0x0285, TDP_COMMON }, - { 0xe4, 0x0288, TDP_32 }, - { 0x0c, 0x0289, TDP_32 }, - { 0x10, 0x0288, TDP_16 }, - { 0x0e, 0x0289, TDP_16 }, - { 0x03, 0x028a, TDP_COMMON }, - { 0x0a, 0x028b, TDP_COMMON }, - { 0x80, 0x028c, TDP_COMMON }, - { 0x03, 0x028d, TDP_COMMON }, -}; static uint8_t send_mbox_msg_with_int(uint8_t mbox_message) { @@ -617,12 +378,14 @@ ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); val |= 0x02; ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); ec_read_write_reg(EC_HWM_LDN, 0x0042, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, READ_OP); val |= 0x04; ec_read_write_reg(EC_HWM_LDN, 0x0048, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP); ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); @@ -672,6 +435,7 @@ ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP); + if (chassis_type == 4 || chassis_type == 5) { ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); if (val == 0) { diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec_early.c b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec_early.c similarity index 98% rename from src/mainboard/dell/optiplex_9010/sch5545_ec_early.c rename to src/mainboard/dell/snb_ivb_workstations/sch5545_ec_early.c index 70b7de6..fd5fbca 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec_early.c +++ b/src/mainboard/dell/snb_ivb_workstations/sch5545_ec_early.c @@ -4,7 +4,7 @@ #include <superio/smsc/sch5545/sch5545.h> #include <superio/smsc/sch5545/sch5545_emi.h> -#include "sch5545_ec.h" +#include <baseboard/sch5545_ec.h> static uint16_t emi_bar; diff --git a/src/mainboard/dell/optiplex_9010/smihandler.c b/src/mainboard/dell/snb_ivb_workstations/smihandler.c similarity index 100% rename from src/mainboard/dell/optiplex_9010/smihandler.c rename to src/mainboard/dell/snb_ivb_workstations/smihandler.c diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb similarity index 88% rename from src/mainboard/dell/optiplex_9010/devicetree.cb rename to src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index ef0a0e3..e614f1e 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -10,11 +10,10 @@ end end device domain 0 on - subsystemid 0x1028 0x052c inherit device pci 00.0 on end # Host bridge Host bridge device pci 01.0 on # PEG1 (blue slot1) - smbios_slot_desc "0xB6" "4" "SLOT1" "0x0D" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X" end device pci 02.0 on end # Internal graphics VGA controller device pci 06.0 off end # PEG2 @@ -30,7 +29,6 @@ register "gen4_dec" = "0x001c0901" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x7" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" @@ -48,12 +46,10 @@ device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 - smbios_slot_desc "0xB6" "4" "SLOT2" "0x0A" - end - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.h b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/include/baseboard/sch5545_ec.h similarity index 72% rename from src/mainboard/dell/optiplex_9010/sch5545_ec.h rename to src/mainboard/dell/snb_ivb_workstations/variants/baseboard/include/baseboard/sch5545_ec.h index 0ca589f..80d978e 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.h +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/include/baseboard/sch5545_ec.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SCH5545_BOARD_EC_H +#define SCH5545_BOARD_EC_H + #include <stdint.h> #define READ_OP 0 @@ -21,8 +24,22 @@ uint16_t reg; }; +enum { + TDP_16 = 0x10, + TDP_32 = 0x20, + TDP_COMMON = 0xff, +}; + +typedef struct ec_val_reg_tdp { + uint8_t val; + uint16_t reg; + uint8_t tdp; +} ec_chassis_tdp_t; + uint16_t sch5545_get_ec_fw_version(void); void sch5545_update_ec_firmware(uint16_t ec_version); void sch5545_ec_early_init(void); void sch5545_ec_hwm_early_init(void); void sch5545_ec_hwm_init(void *unused); + +#endif // SCH5545_BOARD_EC_H diff --git a/src/mainboard/dell/optiplex_9010/data.vbt b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/data.vbt similarity index 100% rename from src/mainboard/dell/optiplex_9010/data.vbt rename to src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/data.vbt Binary files differ diff --git a/src/mainboard/dell/optiplex_9010/hda_verb.c b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c similarity index 100% rename from src/mainboard/dell/optiplex_9010/hda_verb.c rename to src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/include/variant/sch5545_ec_tables.h b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/include/variant/sch5545_ec_tables.h new file mode 100644 index 0000000..02096b7 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/include/variant/sch5545_ec_tables.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SCH5545_BOARD_EC_TABLE_H +#define SCH5545_BOARD_EC_TABLE_H + +#include <baseboard/sch5545_ec.h> + +static const ec_chassis_tdp_t ec_hwm_chassis3[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x8a, 0x0085, TDP_16 }, + { 0x2c, 0x0086, TDP_16 }, + { 0x66, 0x008a, TDP_16 }, + { 0x5b, 0x008b, TDP_16 }, + { 0x65, 0x0090, TDP_COMMON }, + { 0x70, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0e, 0x00a0, TDP_COMMON }, + { 0x0e, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x86, 0x00af, TDP_COMMON }, + { 0x95, 0x00b0, TDP_COMMON }, + { 0x9a, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x94, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_16 }, + { 0x11, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0x68, 0x0288, TDP_16 }, + { 0x10, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis4[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x99, 0x0085, TDP_32 }, + { 0x98, 0x0085, TDP_16 }, + { 0xbc, 0x0086, TDP_32 }, + { 0x1c, 0x0086, TDP_16 }, + { 0x39, 0x008a, TDP_32 }, + { 0x3d, 0x008a, TDP_16 }, + { 0x40, 0x008b, TDP_32 }, + { 0x43, 0x008b, TDP_16 }, + { 0x68, 0x0090, TDP_COMMON }, + { 0x5e, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0c, 0x00a0, TDP_COMMON }, + { 0x0c, 0x00a1, TDP_COMMON }, + { 0x72, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x9a, 0x00b0, TDP_COMMON }, + { 0x7c, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x90, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_32 }, + { 0x11, 0x0281, TDP_32 }, + { 0x68, 0x0280, TDP_16 }, + { 0x10, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0xa0, 0x0288, TDP_32 }, + { 0x0f, 0x0289, TDP_32 }, + { 0xd8, 0x0288, TDP_16 }, + { 0x0e, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis5[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x89, 0x0085, TDP_32 }, + { 0x99, 0x0085, TDP_16 }, + { 0x9c, 0x0086, TDP_COMMON }, + { 0x39, 0x008a, TDP_32 }, + { 0x42, 0x008a, TDP_16 }, + { 0x6b, 0x008b, TDP_32 }, + { 0x74, 0x008b, TDP_16 }, + { 0x5e, 0x0091, TDP_COMMON }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0c, 0x00a0, TDP_COMMON }, + { 0x0c, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x9a, 0x00b0, TDP_COMMON }, + { 0x7c, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x90, 0x01be, TDP_COMMON }, + { 0x94, 0x0280, TDP_32 }, + { 0x11, 0x0281, TDP_32 }, + { 0x3c, 0x0280, TDP_16 }, + { 0x0f, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0x60, 0x0288, TDP_32 }, + { 0x09, 0x0289, TDP_32 }, + { 0x98, 0x0288, TDP_16 }, + { 0x08, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +static const ec_chassis_tdp_t ec_hwm_chassis6[] = { + { 0x33, 0x0005, TDP_COMMON }, + { 0x2f, 0x0018, TDP_COMMON }, + { 0x2f, 0x0019, TDP_COMMON }, + { 0x2f, 0x001a, TDP_COMMON }, + { 0x00, 0x0080, TDP_COMMON }, + { 0x00, 0x0081, TDP_COMMON }, + { 0xbb, 0x0083, TDP_COMMON }, + { 0x99, 0x0085, TDP_32 }, + { 0x98, 0x0085, TDP_16 }, + { 0xdc, 0x0086, TDP_32 }, + { 0x9c, 0x0086, TDP_16 }, + { 0x3d, 0x008a, TDP_32 }, + { 0x43, 0x008a, TDP_16 }, + { 0x4e, 0x008b, TDP_32 }, + { 0x47, 0x008b, TDP_16 }, + { 0x6d, 0x0090, TDP_COMMON }, + { 0x5f, 0x0091, TDP_32 }, + { 0x61, 0x0091, TDP_16 }, + { 0x86, 0x0092, TDP_COMMON }, + { 0xa4, 0x0096, TDP_COMMON }, + { 0xa4, 0x0097, TDP_COMMON }, + { 0xa4, 0x0098, TDP_COMMON }, + { 0xa4, 0x009b, TDP_COMMON }, + { 0x0e, 0x00a0, TDP_COMMON }, + { 0x0e, 0x00a1, TDP_COMMON }, + { 0x7c, 0x00ae, TDP_COMMON }, + { 0x7c, 0x00af, TDP_COMMON }, + { 0x98, 0x00b0, TDP_32 }, + { 0x9a, 0x00b0, TDP_16 }, + { 0x9a, 0x00b3, TDP_COMMON }, + { 0x08, 0x00b6, TDP_COMMON }, + { 0x08, 0x00b7, TDP_COMMON }, + { 0x64, 0x00ea, TDP_COMMON }, + { 0xff, 0x00ef, TDP_COMMON }, + { 0x15, 0x00f8, TDP_COMMON }, + { 0x00, 0x00f9, TDP_COMMON }, + { 0x30, 0x00f0, TDP_COMMON }, + { 0x01, 0x00fd, TDP_COMMON }, + { 0x88, 0x01a1, TDP_COMMON }, + { 0x08, 0x01a2, TDP_COMMON }, + { 0x08, 0x01b1, TDP_COMMON }, + { 0x97, 0x01be, TDP_32 }, + { 0x95, 0x01be, TDP_16 }, + { 0x68, 0x0280, TDP_32 }, + { 0x10, 0x0281, TDP_32 }, + { 0xd8, 0x0280, TDP_16 }, + { 0x0e, 0x0281, TDP_16 }, + { 0x03, 0x0282, TDP_COMMON }, + { 0x0a, 0x0283, TDP_COMMON }, + { 0x80, 0x0284, TDP_COMMON }, + { 0x03, 0x0285, TDP_COMMON }, + { 0xe4, 0x0288, TDP_32 }, + { 0x0c, 0x0289, TDP_32 }, + { 0x10, 0x0288, TDP_16 }, + { 0x0e, 0x0289, TDP_16 }, + { 0x03, 0x028a, TDP_COMMON }, + { 0x0a, 0x028b, TDP_COMMON }, + { 0x80, 0x028c, TDP_COMMON }, + { 0x03, 0x028d, TDP_COMMON }, +}; + +#endif // SCH5545_BOARD_EC_TABLE_H diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb new file mode 100644 index 0000000..30167f9 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb @@ -0,0 +1,14 @@ +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1028 0x052c inherit + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "sata_port_map" = "0x7" + device pci 1c.4 on # PCIe Port #5 + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X" + end + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/62211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Gerrit-Change-Number: 62211 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Add a configurate "FILL_DRAM_INFO_FROM_BLOB"
by Hung-Te Lin (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63109 ) Change subject: soc/mediatek: Add a configurate "FILL_DRAM_INFO_FROM_BLOB" ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/common/Kconfig: https://review.coreboot.org/c/coreboot/+/63109/comment/8e97af52_e4074f00 PS2, Line 53: FILL_DRAM_INFO_FROM_BLOB no need to mention blob? Just USE_FILL_DRAM_INFO or HAS_FILL_DRAM_INFO or HAS_CBMEM_DRAM_INFO USE_CBMEM_DRAM_INFO etc -- To view, visit https://review.coreboot.org/c/coreboot/+/63109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Gerrit-Change-Number: 63109 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 09:25:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Add a configurate "FILL_DRAM_INFO_FROM_BLOB"
by Hung-Te Lin (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63109 ) Change subject: soc/mediatek: Add a configurate "FILL_DRAM_INFO_FROM_BLOB" ...................................................................... Patch Set 2: (3 comments) File src/soc/mediatek/common/Kconfig: https://review.coreboot.org/c/coreboot/+/63109/comment/7f4a2a14_15861900 PS2, Line 54: fill filling https://review.coreboot.org/c/coreboot/+/63109/comment/fa17a5b5_64aa63c1 PS2, Line 56: , and the DRAM : information is passed from DRAM blob. I think blob or not is not that important; it's more like if the mem-ref code has it or not. help The DRAM initialization will keep and return DRAM information (size, geometry and other DDR info) so we can fill that into the CBMEM. File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/63109/comment/93a7010f_c94cfffc PS2, Line 138: CONFIG !CONFIG ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Gerrit-Change-Number: 63109 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 09:23:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: support max98390 audio amp
by Yu-Ping Wu (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel, Trevor Wu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63083 ) Change subject: mb/google/cherry: support max98390 audio amp ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/cherry/chromeos.c: https://review.coreboot.org/c/coreboot/+/63083/comment/e0c4077e_9dfa3dba PS4, Line 26: > is there any example for this? Search "endchoice" in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/63083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Gerrit-Change-Number: 63083 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Trevor Wu <trevor.wu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Trevor Wu <trevor.wu(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 09:19:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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