coreboot-gerrit February 2022

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Change in coreboot[master]: doc/mb/hp/z220_sff.md: Add some information
by Ao Zhong (Code Review) 07 Aug '23

07 Aug '23

Ao Zhong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48010 ) Change subject: doc/mb/hp/z220_sff.md: Add some information ...................................................................... doc/mb/hp/z220_sff.md: Add some information Added some test results about this mainboard and the way to disable SPI flash write protection. Signed-off-by: Ao Zhong <hacc1225(a)gmail.com> Change-Id: I3ec61557c9c800db66b3b7db78ea6120c109d84a --- M Documentation/mainboard/hp/z220_sff.md A Documentation/mainboard/hp/z220_sff_pin1.jpg A Documentation/mainboard/hp/z220_sff_pin2.jpg 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48010/1 diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md index 0dfa653..7ebe446 100644 --- a/Documentation/mainboard/hp/z220_sff.md +++ b/Documentation/mainboard/hp/z220_sff.md @@ -11,6 +11,35 @@ - Advanced LED control - Advanced power configuration in S3 +## Working + +- USB 3.0 and USB 2.0 +- S3 suspend/resume (Tested with Arch Linux 2020.11.25 and resume with power button) +- SATA +- Onboard audio +- Front headphone jack +- Rear headphone jack +- Internal audio speaker +- Onboard network (Working with Gigabit Ethernet Firmware blob) +- PCIe x16 Gen3 (Tested with Nvidia Quadro 600) +- PCIe x4 Gen2 / x16 connector (Tested with WD SN550 SSD) +- Boot from NVMe SSD (Tested with Tianocore, M.2-to-PCIe adapter and WD SN550 SSD) +- CPU Temp sensors (Tested with lm-sensors in Arch Linux) +- Native raminit (Tested with Xeon-E3 1240v2, 4x4G Hynix ECC DDR3 RAM) +- Automatic fan control +- 1x PCIe GPU in PCIe x16 Gen3 slot (Tested with Nvidia Quadro 600) +- using `me_cleaner` +- using `flashrom` + +## Untested + +- Integrated graphics +- PS/2 port +- TPM +- Parallel port +- PCI slot +- PCIe x1 gen2 slot + ## Flashing coreboot ```eval_rst @@ -39,6 +68,20 @@ The SPI flash can be accessed using [flashrom]. +When you flash from stock firmware, you may need to short ME/AMT flash override pins to make the whole SPI flash accessible. + +**Position of ME/AMT flash override pins** + +![][z220_sff_pin1] + +[z220_sff_pin1]: z220_sff_pin1.jpg + +**Closeup view of ME/AMT flash override pins** + +![][z220_sff_pin2] + +[z220_sff_pin2]: z220_sff_pin2.jpg + ### External programming External programming with an SPI adapter and [flashrom] does work, but it powers the diff --git a/Documentation/mainboard/hp/z220_sff_pin1.jpg b/Documentation/mainboard/hp/z220_sff_pin1.jpg new file mode 100644 index 0000000..b20a475 --- /dev/null +++ b/Documentation/mainboard/hp/z220_sff_pin1.jpg Binary files differ diff --git a/Documentation/mainboard/hp/z220_sff_pin2.jpg b/Documentation/mainboard/hp/z220_sff_pin2.jpg new file mode 100644 index 0000000..dfe8ad5 --- /dev/null +++ b/Documentation/mainboard/hp/z220_sff_pin2.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/48010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec61557c9c800db66b3b7db78ea6120c109d84a Gerrit-Change-Number: 48010 Gerrit-PatchSet: 1 Gerrit-Owner: Ao Zhong <hacc1225(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redun...
by Name of user not set (Code Review) 07 Aug '23

07 Aug '23

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36001 ) Change subject: vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redundant FIS code ...................................................................... vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze: Remove redundant FIS code From looking at neighboring code, disabling FIS based switching appears intentional, possibly due to errata. Clean and comment code so it is apparent. Change-Id: I4529716e951a9e7b63bdee11611dd78f2d41b464 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> --- M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c 1 file changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36001/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c index 9f526d8..293ea57 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c @@ -367,11 +367,8 @@ AndMaskDword |= BIT12; } - if ( FchSataFisBasedSwitching ) { - AndMaskDword |= BIT10; - } else { - AndMaskDword |= BIT10; - } + // FchSataFisBasedSwitching + AndMaskDword |= BIT10; if ( FchSataAggrLinkPmCap ) { OrMaskDword |= BIT11; @@ -431,11 +428,8 @@ RwMem ((Bar5 + 0x0FC), AccessWidth32, (UINT32)~(BIT20), 0x00); } - if ( FchSataFisBasedSwitching ) { - RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00); - } else { - RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00); - } + // FchSataFisBasedSwitching + RwMem ((Bar5 + 0x0F8), AccessWidth32, 0x00FFFFFF, 0x00); if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) { RwMem ((Bar5 + 0x24), AccessWidth8, (UINT32)~BIT0, BIT0); -- To view, visit https://review.coreboot.org/c/coreboot/+/36001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4529716e951a9e7b63bdee11611dd78f2d41b464 Gerrit-Change-Number: 36001 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mainboard/pcengines/apu1.md: Document recent issues
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41230 ) Change subject: Documentation/mainboard/pcengines/apu1.md: Document recent issues ...................................................................... Documentation/mainboard/pcengines/apu1.md: Document recent issues Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie79af9ad5b8e6198ad9ba8ce9b41b22319dbf87c --- M Documentation/mainboard/pcengines/apu1.md 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/41230/1 diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md index ccadd63..f9d3cd7 100644 --- a/Documentation/mainboard/pcengines/apu1.md +++ b/Documentation/mainboard/pcengines/apu1.md @@ -95,3 +95,11 @@ [apu1c1_flash]: apu1c1.jpg [spi_header]: apu1_spi.jpg [flashrom]: https://flashrom.org/Flashrom + +### Known issues + +- platform does not reliably POST after power failure, it hangs at + sbPowerOnInit (src/vendorcode/amd/cimx/sb800/SBPort.c:296) unable to perform + reset via CF9 port, issue is present since C bootblock migration +- AmdInitLate reports ASSERTION_ERRORs during DMI table creation enabled in + CB:38343 -- To view, visit https://review.coreboot.org/c/coreboot/+/41230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79af9ad5b8e6198ad9ba8ce9b41b22319dbf87c Gerrit-Change-Number: 41230 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]Documentation: Add Intel microcode update mechanism
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36539 ) Change subject: [WIP]Documentation: Add Intel microcode update mechanism ...................................................................... [WIP]Documentation: Add Intel microcode update mechanism Document microcode updates and how secure microcode updates are done in GNU/Linux. Propose how to do microcode updates in coreboot. Change-Id: I78350fc81cb0de7b0b2d9cbd8537e6b3815916c0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/microcode/index.md 2 files changed, 111 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36539/1 diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index f30ff9a..1cf8548 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -2,6 +2,10 @@ This section contains documentation about coreboot on specific Intel SOCs. +## Common + +- [Microcode updates](microcode/index.md) + ## Platforms - [Common code development strategy](code_development_model/code_development_model.md) diff --git a/Documentation/soc/intel/microcode/index.md b/Documentation/soc/intel/microcode/index.md new file mode 100644 index 0000000..b7f5949 --- /dev/null +++ b/Documentation/soc/intel/microcode/index.md @@ -0,0 +1,107 @@ +# Microcode updates on Intel CPUs + +## What are microcodes? + +```eval_rst +Microcode is a computer hardware technique that interposes a layer of +organisation between the CPU hardware and the programmer-visible +instruction set architecture of the computer. [#1]_ +``` + +In coreboot the microcode updates are stored in files in the CBFS and +are used to update the CPU microcode at runtime using a special instruction. + +## How does a microcode update look like? + +The microcode update is a binary provided by Intel consisting out of +a header and data. +The header holds the processor signature for which the update is +intented and additional metadata. +For detailed information check the [Intel SDM] 253668-060US Chapter 9.11.1 + +## When are mirocode updates done? + +Microcode updates are stored in the CPU's SRAM and thus needs to be loaded +after a hard reset. However loading microcode updates is done multiple times +in coreboot's boot sequence. + +On some CPUs it's neccessary to do an microcode update before: +* Cache-As-RAM is enabled +* Legacy Intel TXT FIT boot is run +* MultiProcessor-Init is run + +On some CPUs it's neccessary to do an microcode update after: +* SMM setup was done +* SGX setup was done + +## How to do microcode updates? + +The following chapter is based multiple sources and testing due to lack of clear +documentation. + +In order to safely update microcode on any generation the GNU/Linux kernel +"late loading mechanism" takes a conservative approach and obeys the following +rules: + +```eval_rst +* All physical CPU cores must be updated with the same microcode version [#2]_ +* Caches need to be flushed on certain CPUs prior to microcode update [#3]_ +* The sibling thread must be idle while a microcode update is ongoing [#4]_ +* All other APs on the same package should be idle (or in Wait-for-SIPI) [#5]_ +* The microcode update is done sequentially [#6]_ +``` + +The downside of this approach is that it's very slow. + +It seems to be possible to run microcode updates in parallel on APs on specific +CPUs. + +## How to do microcode updates in coreboot ramstage? + +*TBD* + +Proposal: +1. Run microcode update sequential by default +2. Flush caches in non CAR environment before running a microcode update +3. Switch to parallel microcode update after extensive testing (10000 boot cycles) + +For parallel microcde update: +1. On Intel HT enabled CPUs spinlock the slibing thread of a logical core +2. On Intel HT enabled CPUs only update one thread of a physical core +3. Synchronize microcode loading. This will make sure no other computational work + is being done while an update occurs (thus no Wait-for-SIPI). + +## Intel Hyper-Threading enabled CPUs + +```eval_rst +According to Intel SDM a Hyper-Threading enabled core shares the microcode unit +between the logical CPU cores [#4]_. Intel NetBurst CPUs must not attempt to +update the microcode on both logical cores at the same time, this is safe for +newer CPU generations. +``` + +## Where to obtain the microcode updates? + +The microcode update files can be found on Intel's [Github Microcode]. + +## References +- [Wikipedia microcode] +- [Github Microcode] +- [Intel SDM] + +------------- +```eval_rst +.. [#1] Kent, Allen; Williams, James G. (April 5, 1993). `Encyclopedia of Computer Science and Technology: Volume 28 <http://https://books.google.com/books?id=EjWV8J8CQEYC>`_ +.. [#2] `Intel SDM Document 253668-060US`_ Chapter 9.11.6.3 "Update in a System Supporting Intel Hyper-Threading Technology" +.. [#3] GNU/Linux commit by Ashok Raj `<https://lore.kernel.org/patchwork/patch/890717/>`_ +.. [#4] `Intel SDM Document 253668-060US`_ Chapter 8.8.5 "Microcode Update Resources" +.. [#5] GNU/Linux commit by Ashok Raj `<https://lore.kernel.org/patchwork/patch/890713/>`_ +.. [#6] `Intel SDM Document 253668-060US`_ Chapter 9.11.6.3 "Update in a System Supporting Intel Hyper-Threading Technology" + +.. _Intel SDM Document 253668-060US: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-… + +``` + +[Wikipedia microcode]: https://en.wikipedia.org/wiki/Microcode +[Github Microcode]: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files +[Intel SDM]: https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-… -- To view, visit https://review.coreboot.org/c/coreboot/+/36539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78350fc81cb0de7b0b2d9cbd8537e6b3815916c0 Gerrit-Change-Number: 36539 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lib.h: Add convenient memcpy() variants
by Nico Huber (Code Review) 07 Aug '23

07 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32740 Change subject: lib.h: Add convenient memcpy() variants ...................................................................... lib.h: Add convenient memcpy() variants Add two macros that should help in cases where the arguments are objects (not pointers) and the count of bytes to be copied is the size of one of them (or both). * memcpy_dlen(dst, src) copies `sizeof(dst)` bytes (destination length). * memcpy_elen(dst, src) asserts that both sizes match and copies as many bytes (equal length). Change-Id: I2b23066b3bcc29ff679e620f723ce1da5057aa03 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/lib.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32740/1 diff --git a/src/include/lib.h b/src/include/lib.h index 098d62d..6cbe6f3 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -18,6 +18,7 @@ #ifndef __LIB_H__ #define __LIB_H__ #include <stdint.h> +#include <string.h> #include <types.h> /* Defined in src/lib/lzma.c. Returns decompressed size or 0 on error. */ @@ -69,4 +70,18 @@ /* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } +/* memcpy destination length (memcpy_dlen) copies `sizeof(dst)` bytes. */ +#define memcpy_dlen(dst, src) memcpy(dst, src, sizeof(dst)) + +/* + * memcpy equal length (memcpy_elen) + * Asserts that both objects `dst` and `src` + * have the same size and copies as many bytes. + */ +#define memcpy_elen(dst, src) do { \ + _Static_assert(sizeof(dst) == sizeof(src), \ + "`dst` and `src` need equal length!"); \ + memcpy_dlen(dst, src); \ +} while (0) + #endif /* __LIB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b23066b3bcc29ff679e620f723ce1da5057aa03 Gerrit-Change-Number: 32740 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: Add complete board list with libre/blobby status
by Damien Zammit (Code Review) 07 Aug '23

07 Aug '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32237 Change subject: WIP: Add complete board list with libre/blobby status ...................................................................... WIP: Add complete board list with libre/blobby status Please comment on the list so we can remove the third '?' category Change-Id: I526b453ca30d8bcb6a55b40f4e53c6852f7cf4c7 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A Documentation/libre-boards.csv 1 file changed, 219 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32237/1 diff --git a/Documentation/libre-boards.csv b/Documentation/libre-boards.csv new file mode 100644 index 0000000..94c87ca --- /dev/null +++ b/Documentation/libre-boards.csv @@ -0,0 +1,219 @@ +Manufacturer/Model,Fully libre?,Reason for exclusion +amd/samba,?,Should be deleted from tree +cavium/cn8100_sff_evb,?,cavium +cubietech/cubieboard,?, +google/cheza,?,Qualcomm +google/daisy,?,Exynos +google/foster,?,Nvidia Tegra210 +google/gale,?,Qualcomm +google/gru,?,RockChip rk3399 +google/kukui,?,Mediatek mt8183 soc +google/mistral,?,Qualcomm +google/nyan,?,Nvidia Tegra124 +google/nyan_big,?,Nvidia Tegra124 +google/nyan_blaze,?,Nvidia Tegra124 +google/oak,?,Mediatek mt8173 soc +google/storm,?,Qualcomm +google/veyron,?,RockChip rk3288 +google/veyron_mickey,?,RockChip rk3288 +google/veyron_rialto,?,RockChip rk3288 +opencellular/elgon,?,cavium +sifive/hifive-unleashed,?,Sifive soc +adi/rcc-dff,n,Needs FSP for RAM init +adlink/cExpress-GFR,n,Needs VGA-ROM +adlink/CM2-GF,n,Needs VGA-ROM +advansus/a785e-i,n,Needs VGA-ROM +amd/bettong,n,Needs AMD PI for initialisation +amd/bimini_fam10,n,Needs VGA-ROM +amd/db-ft3b-lc,n,Needs AMD PI for initialisation +amd/gardenia,n,Needs AMD PI for initialisation +amd/inagua,n,Needs VGA-ROM +amd/lamar,n,Needs AMD PI for initialisation +amd/mahogany_fam10,n,Needs VGA-ROM +amd/olivehill,n,Needs VGA-ROM +amd/olivehillplus,n,Needs AMD PI for initialisation +amd/parmer,n,Needs VGA-ROM +amd/persimmon,n,Needs VGA-ROM +amd/serengeti_cheetah_fam10,n,Needs VGA-ROM +amd/south_station,n,Needs VGA-ROM +amd/thatcher,n,Needs VGA-ROM +amd/tilapia_fam10,n,Needs VGA-ROM +amd/torpedo,n,Needs VGA-ROM +amd/union_station,n,Needs VGA-ROM +aopen/dxplplusu,n,Needs VGA-ROM +asrock/e350m1,n,Needs VGA-ROM +asrock/h110m,n,Needs FSP for RAM init +asrock/h81m-hds,n,Needs FSP for RAM init +asrock/imb-a180,n,Needs VGA-ROM +asus/am1i-a,n,Needs VGA-ROM +asus/f2a85-m,n,Needs VGA-ROM +asus/f2a85-m_fam10,n,Needs VGA-ROM +asus/kcma-d8,n,Needs VGA-ROM +asus/kfsn4-dre,n,Needs VGA-ROM +asus/kfsn4-dre_k8,n,Needs VGA-ROM +asus/kgpe-d16,n,Needs VGA-ROM +asus/m4a78-em,n,Needs VGA-ROM +asus/m4a785-m,n,Needs VGA-ROM +asus/m4a785t-m,n,Needs VGA-ROM +asus/m5a88-v,n,Needs VGA-ROM +avalue/eax-785e,n,Needs VGA-ROM +bap/ode_e20XX,n,Needs VGA-ROM +bap/ode_e21XX,n,Needs AMD PI for initialisation +biostar/a68n_5200,n,Needs VGA-ROM +biostar/am1ml,n,Needs VGA-ROM +elmex/pcm205400,n,Needs VGA-ROM +elmex/pcm205401,n,Needs VGA-ROM +esd/atom15,n,Needs FSP for RAM init +facebook/watson,n,Needs FSP for RAM init +gigabyte/ma785gm,n,Needs VGA-ROM +gigabyte/ma785gmt,n,Needs VGA-ROM +gigabyte/ma78gm,n,Needs VGA-ROM +gizmosphere/gizmo,n,Needs VGA-ROM +gizmosphere/gizmo2,n,Needs VGA-ROM +google/auron,n,Needs FSP for RAM init +google/beltino,n,Needs FSP for RAM init +google/butterfly,n,Sandy/Ivy unported +google/cyan,n,Needs blob for Braswell SOC +google/dragonegg,n,Needs blob for Icelake SOC +google/eve,n,Needs FSP for RAM init +google/fizz,n,Needs FSP for RAM init +google/glados,n,Needs FSP for RAM init +google/hatch,n,Needs Blob for Cannonlake SOC +google/jecht,n,Needs FSP for RAM init +google/kahlee,n,Needs AMD PI for initialisation +google/link,n,Sandy/Ivy unported +google/octopus,n,Needs blob for GLK soc +google/parrot,n,Sandy/Ivy unported +google/poppy,n,Needs FSP for RAM init +google/rambi,n,Needs FSP for RAM init +google/reef,n,Needs FSP for RAM init +google/sarien,n,Needs blob for Whiskeylake SOC +google/slippy,n,Needs FSP for RAM init +google/stout,n,Sandy/Ivy unported +hp/abm,n,Needs VGA-ROM +hp/dl165_g6_fam10,n,Needs VGA-ROM +hp/pavilion_m6_1035dx,n,Needs VGA-ROM +ibase/mb899,n,Needs VGA-ROM +iei/kino-780am2-fam10,n,Needs VGA-ROM +intel/apollolake_rvp,n,Needs FSP for RAM init +intel/baskingridge,n,Needs FSP for RAM init +intel/bayleybay_fsp,n,Needs FSP for RAM init +intel/camelbackmountain_fsp,n,Needs FSP for RAM init +intel/cannonlake_rvp,n,Needs FSP for RAM init +intel/coffeelake_rvp,n,Needs FSP for RAM init +intel/emeraldlake2,n,Sandy/Ivy unported +intel/galileo,n,Needs FSP for RAM init +intel/glkrvp,n,Needs FSP for RAM init +intel/harcuvar,n,Needs blob for Denverton SOC +intel/icelake_rvp,n,Needs FSP for RAM init +intel/kblrvp,n,Needs FSP for RAM init +intel/kunimitsu,n,Needs FSP for RAM init +intel/leafhill,n,Needs FSP for RAM init +intel/littleplains,n,Needs FSP for RAM init +intel/minnow3,n,Needs FSP for RAM init +intel/minnowmax,n,Needs FSP for RAM init +intel/mohonpeak,n,Needs FSP for RAM init +intel/saddlebrook,n,Needs FSP for RAM init +intel/strago,n,Needs blob for Braswell SOC +intel/wtm2,n,Needs FSP for RAM init +jetway/pa78vm5,n,Needs VGA-ROM +kontron/986lcd-m,n,Needs VGA-ROM +lenovo/g505s,n,Needs VGA-ROM +lippert/frontrunner-af,n,Needs VGA-ROM +lippert/toucan-af,n,Needs VGA-ROM +msi/ms7721,n,Needs VGA-ROM +msi/ms9652_fam10,n,Needs VGA-ROM +ocp/monolake,n,Needs FSP for RAM init +ocp/wedge100s,n,Needs FSP for RAM init +opencellular/rotundu,n,Needs FSP for RAM init +pcengines/apu1,n,Needs VGA-ROM +pcengines/apu2,n,Needs AMD PI for initialisation +purism/librem_bdw,n,Needs FSP for RAM init +purism/librem_skl,n,Needs FSP for RAM init +roda/rk886ex,n,Needs VGA-ROM +roda/rk9,n,Needs VGA-ROM +samsung/lumpy,n,Sandy/Ivy unported +samsung/stumpy,n,Sandy/Ivy unported +scaleway/tagada,n,Needs blob for Denverton SOC +siemens/mc_apl1,n,Needs FSP for RAM init +siemens/mc_bdx1,n,Needs FSP for RAM init +siemens/mc_tcu3,n,Needs FSP for RAM init +supermicro/h8dmr_fam10,n,Needs VGA-ROM +supermicro/h8qme_fam10,n,Needs VGA-ROM +supermicro/h8scm_fam10,n,Needs VGA-ROM +supermicro/x10slm-f,n,Needs FSP for RAM init +tyan/s2912_fam10,n,Needs VGA-ROM +via/epia-m850,n,Needs VGA-ROM +apple/macbook21,Y, +apple/macbookair4_2,Y, +asrock/b75pro3-m,Y, +asrock/g41c-gs,Y, +asus/h61m-cs,Y, +asus/maximus_iv_gene-z,Y, +asus/p2b,Y, +asus/p2b-d,Y, +asus/p2b-ds,Y, +asus/p2b-f,Y, +asus/p2b-ls,Y, +asus/p3b-f,Y, +asus/p5gc-mx,Y, +asus/p5qc,Y, +asus/p5qpl-am,Y, +asus/p8h61-m_lx,Y, +asus/p8h61-m_pro,Y, +compulab/intense_pc,Y, +emulation/qemu-armv7,Y, +emulation/qemu-i440fx,Y, +emulation/qemu-power8,Y, +emulation/qemu-q35,Y, +emulation/qemu-riscv,Y, +emulation/spike-riscv,Y, +foxconn/d41s,Y, +foxconn/g41s-k,Y, +getac/p470,Y, +gigabyte/ga-945gcm-s2l,Y, +gigabyte/ga-b75m-d3h,Y, +gigabyte/ga-b75m-d3v,Y, +gigabyte/ga-g41m-es2l,Y, +gigabyte/ga-h61m-s2pv,Y, +google/peach_pit,Y,Needs confirmation +google/smaug,Y,Needs confirmation +google/urara,Y,Needs confirmation +hp/2570p,Y, +hp/2760p,Y, +hp/8460p,Y, +hp/8470p,Y, +hp/8770w,Y, +hp/compaq_8200_elite_sff,Y, +hp/folio_9470m,Y, +hp/revolve_810_g1,Y, +intel/d510mo,Y, +intel/d945gclf,Y, +intel/dcp847ske,Y, +intel/dg41wv,Y, +intel/dg43gt,Y, +jetway/nf81-t56n-lf,Y, +kontron/ktqm77,Y, +lenovo/l520,Y, +lenovo/s230u,Y, +lenovo/t400,Y, +lenovo/t420,Y, +lenovo/t420s,Y, +lenovo/t430,Y, +lenovo/t430s,Y, +lenovo/t520,Y, +lenovo/t530,Y, +lenovo/t60,Y, +lenovo/thinkcentre_a58,Y, +lenovo/x1_carbon_gen1,Y, +lenovo/x131e,Y, +lenovo/x200,Y, +lenovo/x201,Y, +lenovo/x220,Y, +lenovo/x230,Y, +lenovo/x60,Y, +lenovo/z61t,Y, +packardbell/ms2290,Y, +roda/rv11,Y, +sapphire/pureplatinumh61,Y, +ti/beaglebone,Y, -- To view, visit https://review.coreboot.org/c/coreboot/+/32237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I526b453ca30d8bcb6a55b40f4e53c6852f7cf4c7 Gerrit-Change-Number: 32237 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Apply clang-format with new changes
by Philipp Deppenwiese (Code Review) 07 Aug '23

07 Aug '23

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31816 Change subject: security/tpm: Apply clang-format with new changes ...................................................................... security/tpm: Apply clang-format with new changes * Fix 80 lines length issues as expected Change-Id: Ieeb675e96b95f6bf2d6a5b9d2be3ca8fd4ed6946 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/tpm/tspi/log.c 1 file changed, 16 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31816/1 diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 18ab288..dc8a1e4 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -33,8 +33,9 @@ if (cbmem_possibly_online()) { tclt = cbmem_find(CBMEM_ID_TCPA_LOG); if (!tclt) { - size_t tcpa_log_len = sizeof(struct tcpa_table) + - MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); + size_t tcpa_log_len = + sizeof(struct tcpa_table) + + MAX_TCPA_LOG_ENTRIES * sizeof(struct tcpa_entry); tclt = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_log_len); if (tclt) { tclt->max_entries = MAX_TCPA_LOG_ENTRIES; @@ -51,11 +52,9 @@ /* We are dealing here with pre CBMEM environment. * If cbmem isn't available use CAR or SRAM */ - if (!cbmem_possibly_online() && - !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) + if (!cbmem_possibly_online() && !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) return (struct tcpa_table *)_vboot2_tpm_log; - else if (ENV_ROMSTAGE && - !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) { + else if (ENV_ROMSTAGE && !IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE)) { tclt = tcpa_cbmem_init(); if (!tclt) return (struct tcpa_table *)_vboot2_tpm_log; @@ -84,17 +83,15 @@ for (j = 0; j < tce->digest_length; j++) printk(BIOS_INFO, "%02x", tce->digest[j]); - printk(BIOS_INFO, " %s [%s]\n", - tce->digest_type, tce->name); + printk(BIOS_INFO, " %s [%s]\n", tce->digest_type, tce->name); } } printk(BIOS_INFO, "\n"); } void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - enum vb2_hash_algorithm digest_algo, - const uint8_t *digest, - const size_t digest_len) + enum vb2_hash_algorithm digest_algo, const uint8_t *digest, + const size_t digest_len) { struct tcpa_table *tclt = tcpa_log_init(); if (!tclt) { @@ -121,9 +118,8 @@ return; } - strncpy(tce->digest_type, - vb2_get_hash_algorithm_name(digest_algo), - TCPA_PCR_HASH_LEN - 1); + strncpy(tce->digest_type, vb2_get_hash_algorithm_name(digest_algo), + TCPA_PCR_HASH_LEN - 1); tce->digest_length = digest_len; memcpy(tce->digest, digest, tce->digest_length); } @@ -144,7 +140,8 @@ int i; if (preram_log->num_entries > MAX_PRERAM_TCPA_LOG_ENTRIES) { - printk(BIOS_WARNING, "TCPA: Pre-RAM TCPA log is too full, possible corruption\n"); + printk(BIOS_WARNING, + "TCPA: Pre-RAM TCPA log is too full, possible corruption\n"); return; } @@ -164,8 +161,10 @@ return; } - strncpy(tce->digest_type, preram_log->entries[i].digest_type, TCPA_PCR_HASH_LEN - 1); - tce->digest_length = MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); + strncpy(tce->digest_type, preram_log->entries[i].digest_type, + TCPA_PCR_HASH_LEN - 1); + tce->digest_length = + MIN(preram_log->entries[i].digest_length, TCPA_DIGEST_MAX_LENGTH); memcpy(tce->digest, preram_log->entries[i].digest, tce->digest_length); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/31816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeb675e96b95f6bf2d6a5b9d2be3ca8fd4ed6946 Gerrit-Change-Number: 31816 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: southbridge/amd/pi/hudson : Revert partially commit bfb5c807e720761f4...
by Jorge Fernandez (Code Review) 07 Aug '23

07 Aug '23

Jorge Fernandez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37617 ) Change subject: southbridge/amd/pi/hudson : Revert partially commit bfb5c807e720761f4457d5106bb919f2aacb5535 ...................................................................... southbridge/amd/pi/hudson : Revert partially commit bfb5c807e720761f4457d5106bb919f2aacb5535 For AMD Bettong board to boot these changes should be reverted. The three options must be enabled to boot. Change-Id: Ied530563f5ff961b50213ffad874351bbd0d3ae3 Signed-off-by: Jorge Fernandez <jorgefm(a)cirsa.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37617/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 33f59c7..29cf6d0 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -85,10 +85,10 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -- To view, visit https://review.coreboot.org/c/coreboot/+/37617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied530563f5ff961b50213ffad874351bbd0d3ae3 Gerrit-Change-Number: 37617 Gerrit-PatchSet: 1 Gerrit-Owner: Jorge Fernandez Gerrit-MessageType: newchange

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Change in coreboot[master]: src/southbridge/amd/pi/hudson/Makefile.inc: fix AMDFW outside CBFS
by Michał Żygowski (Code Review) 07 Aug '23

07 Aug '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35853 ) Change subject: src/southbridge/amd/pi/hudson/Makefile.inc: fix AMDFW outside CBFS ...................................................................... src/southbridge/amd/pi/hudson/Makefile.inc: fix AMDFW outside CBFS The amdfwtool expects firmware location to be passed in hexadecimal format. When CONFIG_AMDFW_OUTSIDE_CBFS the firmware location is calculated by int-add call which produces decimal output. Use shell printf to generate a hexadecimal value of HUDSON_FWM_POSITION. TEST=prepare simple FMD file with AMD_FW region at 0x20000, select CONFIG_AMDFW_OUTSIDE_CBFS and build PC Engines apu2 board Change-Id: Ib4b03f971b88acbc3392b66e084babe738659ea6 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/35853/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 4b4b138..9b543ec 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -194,7 +194,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(HUDSON_FWM_POSITION) \ + --location $(shell printf "0x%x" $(HUDSON_FWM_POSITION)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/35853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4b03f971b88acbc3392b66e084babe738659ea6 Gerrit-Change-Number: 35853 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: drivers/ipmi: Increase BMC timeout message level from INFO to ERR
by Paul Menzel (Code Review) 07 Aug '23

07 Aug '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41997 ) Change subject: drivers/ipmi: Increase BMC timeout message level from INFO to ERR ...................................................................... drivers/ipmi: Increase BMC timeout message level from INFO to ERR If the system is configured with a BMC, the user expects the BMC to be functional. If the initialization times out, than possible expected management features won’t work, so inform the user about that error. It could also be debated, to make it a warning, but I chose to make it an error. Change-Id: I282ea7547e0f5b3cf3b44e4d42977a825180393a Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/41997/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 0b90fb2..a5a963e 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -96,7 +96,7 @@ mdelay(100); } if (stopwatch_expired(&sw)) { - printk(BIOS_INFO, "IPMI: Waiting for BMC timed out\n"); + printk(BIOS_WARN, "IPMI: Waiting for BMC timed out\n"); /* Don't write tables if communication failed */ dev->enabled = 0; return; -- To view, visit https://review.coreboot.org/c/coreboot/+/41997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282ea7547e0f5b3cf3b44e4d42977a825180393a Gerrit-Change-Number: 41997 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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