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Change in ...coreboot[master]: arch/riscv: Fix arch timer timebase
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33797 Change subject: arch/riscv: Fix arch timer timebase ...................................................................... arch/riscv: Fix arch timer timebase The arch timer uses a platform specific clock source. Add a Kconfig that holds this clock frequency and use it to calculate the time passed by. Tested on qemu-system-riscv: Fixes delays being ten times shorter as expected. Change-Id: I2588149e2ee32130a2c41695c4c723b57d4fa827 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/arch_timer.c M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33797/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 25a3980..6b12ff0 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -72,5 +72,9 @@ bool default n +config RISCV_ARCH_TIMER_FREQ + int + depends on RISCV_USE_ARCH_TIMER + config RISCV_WORKING_HARTID int diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 55b1f72..71b9771 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -20,9 +20,18 @@ #include <timer.h> #include <mcall.h> +/* mtime is clocked by platform specific clock source */ +static const uint32_t clocks_per_usec = CONFIG_RISCV_ARCH_TIMER_FREQ/1000000; + void timer_monotonic_get(struct mono_time *mt) { + uint64_t raw; + if (HLS()->time == NULL) die("time not set in HLS"); - mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time))); + if (!clocks_per_usec) + die("Unsupported mtime clock frequency"); + + raw = read64((void *)(HLS()->time)); + mono_time_set_usecs(mt, (long)(raw / clocks_per_usec)); } diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..a10a146 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,8 @@ int default 0 +config RISCV_ARCH_TIMER_FREQ + int + default 1000000 + endif diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index ad48c1c..49887a4 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -14,6 +14,10 @@ if SOC_UCB_RISCV +config RISCV_ARCH_TIMER_FREQ + int + default 10000000 + if ARCH_RISCV_RV64 config RISCV_ARCH -- To view, visit https://review.coreboot.org/c/coreboot/+/33797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2588149e2ee32130a2c41695c4c723b57d4fa827 Gerrit-Change-Number: 33797 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: RFC: smbios: allow setting BIOS-version string from VPD variable
by Łukasz Siudut (Code Review) 09 Jun '23

09 Jun '23

Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32905 Change subject: RFC: smbios: allow setting BIOS-version string from VPD variable ...................................................................... RFC: smbios: allow setting BIOS-version string from VPD variable As in the title. Such approach allows for convenient setting of the firmware version and keep it in partition that is easily readable from both - coreboot binary and already running operating system. vpd_find is used directly as it returns pointer to vpd value which, by spec, is terminated by 0x00 (VPD_TYPE_TERMINATOR) anyway. This way we avoid copying string around and coming up with temporary buffer. Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Signed-off-by: Lukasz Siudut <lsiudut(a)gmail.com> --- M src/arch/x86/smbios.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32905/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 589f4f0..2ffd2dd 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,9 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> +#if CONFIG(VPD) +#include <drivers/vpd/vpd.h> +#endif #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -347,6 +350,15 @@ const char *__weak smbios_mainboard_bios_version(void) { +#if CONFIG(VPD) + /* size is unused for now */ + int size; + const char *coreboot_vpd_version = vpd_find("version", &size, VPD_RO); + + /* if found, vpd value will be terminated by 0x00 (VPD_TYPE_TERMINATOR) */ + if(coreboot_vpd_version) + return coreboot_vpd_version; +#endif if (strlen(CONFIG_LOCALVERSION)) return CONFIG_LOCALVERSION; else -- To view, visit https://review.coreboot.org/c/coreboot/+/32905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458 Gerrit-Change-Number: 32905 Gerrit-PatchSet: 1 Gerrit-Owner: Łukasz Siudut Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: chromeos/cr50_enable_update.c: Fix comment with rename
by Edward O'Callaghan (Code Review) 09 Jun '23

09 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42272 ) Change subject: chromeos/cr50_enable_update.c: Fix comment with rename ...................................................................... chromeos/cr50_enable_update.c: Fix comment with rename Rename VB2_RECOVERY_TRAIN_AND_REBOOT to VB2_RECOVERY_FORCE_REBOOT. BUG=b:154071064 BRANCH=none TEST=none Change-Id: Ie354feba8343fcccaa228351aa0b446a0a49b1b0 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/vendorcode/google/chromeos/cr50_enable_update.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42272/1 diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index e30fe2a..af30379 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -74,7 +74,7 @@ /** * Never update during manually-triggered recovery to ensure update - * cannot interfere. Non-manual VB2_RECOVERY_TRAIN_AND_REBOOT + * cannot interfere. Non-manual VB2_RECOVERY_FORCE_REBOOT * sometimes used to update in factory. */ if (vboot_get_context()->flags & VB2_CONTEXT_FORCE_RECOVERY_MODE) -- To view, visit https://review.coreboot.org/c/coreboot/+/42272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie354feba8343fcccaa228351aa0b446a0a49b1b0 Gerrit-Change-Number: 42272 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/dedede: disable HD Audio Link
by Yong Zhi (Code Review) 09 Jun '23

09 Jun '23

Yong Zhi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42396 ) Change subject: mb/google/dedede: disable HD Audio Link ...................................................................... mb/google/dedede: disable HD Audio Link AudioLinkHda is not used on dedede and defaults to 0x01 in fsp, so explicitly disable it. BUG=None TEST=Build the coreboot and sanity check audio. Signed-off-by: Yong Zhi <yong.zhi(a)intel.com> Change-Id: I82972e44b171f9f8cbd39b6157ffe2a49b9d3a4f --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42396/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 8b68beb..271ed14 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -105,7 +105,7 @@ # Audio related configurations register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkSspEnable[0]" = "1" register "PchHdaAudioLinkSspEnable[1]" = "1" register "PchHdaAudioLinkDmicEnable[0]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82972e44b171f9f8cbd39b6157ffe2a49b9d3a4f Gerrit-Change-Number: 42396 Gerrit-PatchSet: 1 Gerrit-Owner: Yong Zhi <yong.zhi(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/{apl,cnl,icl,jsl,tgl}: print CSME SKU type
by Rizwan Qureshi (Code Review) 09 Jun '23

09 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41870 ) Change subject: soc/intel/{apl,cnl,icl,jsl,tgl}: print CSME SKU type ...................................................................... soc/intel/{apl,cnl,icl,jsl,tgl}: print CSME SKU type print CSME SKU type part of the status dump. TEST=Build for puff mainboard and verfied the SKU information with Consumer and Lite SKU. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I48a0752929eeac8660d33347ba552ba1af559a00 --- M src/soc/intel/apollolake/cse.c M src/soc/intel/cannonlake/me.c M src/soc/intel/icelake/me.c M src/soc/intel/jasperlake/me.c M src/soc/intel/tigerlake/me.c 5 files changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41870/1 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index fef98e3..ed90695 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -167,17 +167,31 @@ static void dump_cse_state(void) { uint32_t fwsts1; + union me_hfsts3 hfsts3; if (!is_cse_enabled()) return; fwsts1 = dump_status(1, PCI_ME_HFSTS1); dump_status(2, PCI_ME_HFSTS2); - dump_status(3, PCI_ME_HFSTS3); + hfsts3 = dump_status(3, PCI_ME_HFSTS3); dump_status(4, PCI_ME_HFSTS4); dump_status(5, PCI_ME_HFSTS5); dump_status(6, PCI_ME_HFSTS6); + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3.fields.fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", + hfs3.fields.fw_sku); + } + /* Minimal decoding is done here in order to call out most important pieces. Manufacturing mode needs to be locked down prior to shipping the product so it's called out explicitly. */ diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index a51b702..6dfe73f 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -126,6 +126,22 @@ printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.raw); + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3.fields.fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + case ME_HFS3_FW_SKU_LITE: + printk(BIOS_DEBUG, "Lite\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", + hfs3.fields.fw_sku); + } + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", hfsts1.fields.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", diff --git a/src/soc/intel/icelake/me.c b/src/soc/intel/icelake/me.c index c494fa5..a36c9d3 100644 --- a/src/soc/intel/icelake/me.c +++ b/src/soc/intel/icelake/me.c @@ -116,6 +116,20 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3.fields.fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", + hfs3.fields.fw_sku); + } + + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", hfsts1.fields.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index e4dc93f..501dbdc 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -32,6 +32,22 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3.fields.fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + case ME_HFS3_FW_SKU_LITE: + printk(BIOS_DEBUG, "Lite\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", + hfs3.fields.fw_sku); + } + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", hfsts1.fields.mfg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index da1a299..7100d75 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -116,6 +116,22 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + printk(BIOS_DEBUG, "ME: Firmware SKU : "); + switch (hfs3.fields.fw_sku) { + case ME_HFS3_FW_SKU_CONSUMER: + printk(BIOS_DEBUG, "Consumer\n"); + break; + case ME_HFS3_FW_SKU_CORPORATE: + printk(BIOS_DEBUG, "Corporate\n"); + break; + case ME_HFS3_FW_SKU_LITE: + printk(BIOS_DEBUG, "Lite\n"); + break; + default: + printk(BIOS_DEBUG, "Unknown (0x%x)\n", + hfs3.fields.fw_sku); + } + /* * Lock Descriptor, and Fuses must be programmed on a * production system to indicate ME Manufacturing mode is disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/41870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48a0752929eeac8660d33347ba552ba1af559a00 Gerrit-Change-Number: 41870 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Consolidate mainboard.c for Puff
by Edward O'Callaghan (Code Review) 09 Jun '23

09 Jun '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42241 ) Change subject: mb/google/hatch: Consolidate mainboard.c for Puff ...................................................................... mb/google/hatch: Consolidate mainboard.c for Puff Puff and it's variants share a rather common mainboard.c implementation. Avoid further divergence by sharing a common implementation when the Puff baseboard is selected by the variants. BUG=b:154071868 BRANCH=none TEST=equiv images. Change-Id: I9cb11cf0e3ef13a1517a91f93a4b4c53a3e01a44 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Makefile.inc R src/mainboard/google/hatch/mainboard.c M src/mainboard/google/hatch/variants/duffy/Makefile.inc D src/mainboard/google/hatch/variants/duffy/mainboard.c M src/mainboard/google/hatch/variants/kaisa/Makefile.inc D src/mainboard/google/hatch/variants/kaisa/mainboard.c M src/mainboard/google/hatch/variants/noibat/Makefile.inc D src/mainboard/google/hatch/variants/noibat/mainboard.c M src/mainboard/google/hatch/variants/puff/Makefile.inc 9 files changed, 2 insertions(+), 433 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42241/1 diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index f82325f..ca7f318 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -7,6 +7,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c + romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c romstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/mainboard.c similarity index 100% rename from src/mainboard/google/hatch/variants/puff/mainboard.c rename to src/mainboard/google/hatch/mainboard.c diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/duffy/Makefile.inc +++ b/src/mainboard/google/hatch/variants/duffy/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c deleted file mode 100644 index ecc0937..0000000 --- a/src/mainboard/google/hatch/variants/duffy/mainboard.c +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <delay.h> -#include <device/device.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 90% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (9 * (w) / 10) - -#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); - } else { - /* Input type is barrel jack */ - volts_mv = BJ_VOLTS_MV; - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *confg = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &confg->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c deleted file mode 100644 index ecc0937..0000000 --- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <delay.h> -#include <device/device.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 90% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (9 * (w) / 10) - -#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); - } else { - /* Input type is barrel jack */ - volts_mv = BJ_VOLTS_MV; - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *confg = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &confg->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/noibat/Makefile.inc b/src/mainboard/google/hatch/variants/noibat/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/noibat/Makefile.inc +++ b/src/mainboard/google/hatch/variants/noibat/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/noibat/mainboard.c b/src/mainboard/google/hatch/variants/noibat/mainboard.c deleted file mode 100644 index b5bc699..0000000 --- a/src/mainboard/google/hatch/variants/noibat/mainboard.c +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <delay.h> -#include <device/device.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <intelblocks/power_limit.h> -#include <timer.h> - -#define GPIO_HDMI_HPD GPP_E13 -#define GPIO_DP_HPD GPP_E14 - -/* TODO: This can be moved to common directory */ -static void wait_for_hpd(gpio_t gpio, long timeout) -{ - struct stopwatch sw; - - printk(BIOS_INFO, "Waiting for HPD\n"); - stopwatch_init_msecs_expire(&sw, timeout); - while (!gpio_get(gpio)) { - if (stopwatch_expired(&sw)) { - printk(BIOS_WARNING, - "HPD not ready after %ldms. Abort.\n", timeout); - return; - } - mdelay(200); - } - printk(BIOS_INFO, "HPD ready after %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -/* - * For type-C chargers, set PL2 to 90% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (9 * (w) / 10) - -#define PUFF_PL2 (35) - -#define PUFF_PSYSPL2 (58) - -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) | - * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+---------+-------+ - * | 60 (U42) | 44 | 54 | 54 | 54 | - * | 60 (U22) | 29 | 54 | 54 | x(43) | - * | n (U42) | 44 | .9n | .9n | .9n | - * | n (U22) | 29 | .9n | .9n | x(43) | - * +-------------+-----+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - psyspl2 = watts; - conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2); - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - conf->tdp_pl4 = SET_PSYSPL2(psyspl2); - } else { - /* Input type is barrel jack */ - volts_mv = BJ_VOLTS_MV; - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = PUFF_PL2; - /* set psyspl2 to 90% of max adapter power */ - conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); -} - -void variant_ramstage_init(void) -{ - static const long display_timeout_ms = 3000; - struct soc_power_limits_config *soc_config; - config_t *conf = config_of_soc(); - - /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ - gpio_input(GPIO_HDMI_HPD); - gpio_input(GPIO_DP_HPD); - if (display_init_required() - && !gpio_get(GPIO_HDMI_HPD) - && !gpio_get(GPIO_DP_HPD)) { - /* This has to be done before FSP-S runs. */ - if (google_chromeec_wait_for_displayport(display_timeout_ms)) - wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); - } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &conf->power_limits_config; - mainboard_set_power_limits(soc_config); -} diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc index 2afd494..3b5b7d0 100644 --- a/src/mainboard/google/hatch/variants/puff/Makefile.inc +++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc @@ -1,5 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c -ramstage-y += mainboard.c bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb11cf0e3ef13a1517a91f93a4b4c53a3e01a44 Gerrit-Change-Number: 42241 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/pcengines/apu2/mptable.c: fix invalid MP table and IRQ table
by Piotr Kleinschmidt (Code Review) 09 Jun '23

09 Jun '23

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42097 ) Change subject: mb/pcengines/apu2/mptable.c: fix invalid MP table and IRQ table ...................................................................... mb/pcengines/apu2/mptable.c: fix invalid MP table and IRQ table MP Table and IRQ routing tables were buggy, which results in Linux kernel panic when 'acpi=noirq' flag was added during boot. TEST=boot Linux debian 4.19.0-9 on PC Engines apu4 platform and see if IRQs are correctly assigned to devices analyzing 'cat proc/interrupts' and `lspci -v` outputs. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Change-Id: I9eadba65eb5f8f66d1d28c89c7c29d0745c93119 --- M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/pcengines/apu2/mptable.c M src/northbridge/amd/pi/00730F01/pci_devs.h 3 files changed, 34 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/42097/1 diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 170c912..43a27ea 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -70,7 +70,7 @@ [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* USB Devs 18/19/20/22 INTA-C */ - [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, + [0x30] = 0x1F,0x12,0x1F,0x12,0x1F,0x12,0x1F,0x00, [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* SATA */ [0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, @@ -92,22 +92,22 @@ */ static const struct pirq_struct mainboard_pirq_data[] = { /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* IOMMU: 00.2 */ {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ - {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ - {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* NIC: 02.2 */ {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* NIC: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe slot 1: 02.5 */ {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ - {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ - {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ - {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ - {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ - {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ - {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ - {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ - {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ - {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ - {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ + {SATA_DEVFN, {PIRQ_D, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {EHCI1_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* EHCI0: 12.0 */ + {EHCI2_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 13.0 */ + {SMBUS_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {LPC_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* LPC: 14.3 */ + {SD_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {EHCI3_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 16.0 (same device as xHCI 10.1) */ }; /* PIRQ Setup */ diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index 8cfec5d..cca3cc7 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -54,6 +54,8 @@ * Source Bus IRQ, Dest APIC ID, Dest PIN# */ + ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are @@ -62,40 +64,31 @@ #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + /* IOMMU */ + //ioapic_id = (io_apic_read((u8 *)IO_APIC2_ADDR, 0x00) >> 24); + PCI_INT(0x0, 0x0, 0x2, 0x10); /* SMBUS / ACPI */ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); /* SD card */ - PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]); + PCI_INT(0x0, 0x14, 0x7, intr_data_ptr[PIRQ_SD]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_EHCI3]); /* SATA */ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); /* on board NIC & Slot PCIE */ - PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); - PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); - - - /* GPP0 */ - PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3 - /* GPP1 */ - PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2 - /* GPP2 */ - PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1 - /* GPP3 */ - PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI - /* GPP4 */ - PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI + PCI_INT(0x1, 0x0, 0x0, 0x10); + PCI_INT(0x2, 0x0, 0x0, 0x11); + PCI_INT(0x3, 0x0, 0x0, 0x12); + PCI_INT(0x4, 0x0, 0x0, 0x13); + PCI_INT(0x5, 0x0, 0x0, 0x10); IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); diff --git a/src/northbridge/amd/pi/00730F01/pci_devs.h b/src/northbridge/amd/pi/00730F01/pci_devs.h index 888e54c..91f7274 100644 --- a/src/northbridge/amd/pi/00730F01/pci_devs.h +++ b/src/northbridge/amd/pi/00730F01/pci_devs.h @@ -5,6 +5,12 @@ #define BUS0 0 +/* IOMMU */ +#define IOMMU_DEV 0x00 +#define IOMMU_FUNC 2 +#define IOMMU_DEVID 0x1567 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV,IOMMU_FUNC) + /* Graphics and Display */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/42097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eadba65eb5f8f66d1d28c89c7c29d0745c93119 Gerrit-Change-Number: 42097 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: [WIP][DONOTMERGE]: Use print GPIO DW's for every community
by Shaunak Saha (Code Review) 09 Jun '23

09 Jun '23

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41058 ) Change subject: [WIP][DONOTMERGE]: Use print GPIO DW's for every community ...................................................................... [WIP][DONOTMERGE]: Use print GPIO DW's for every community Use Tigerlake gpio.c the printing of GPIO pins for all community.We need to define DEBUG_GPIO in the Kconfig and then call gpio_print_pads from anywhere we want to rpint all the gpio pins. The print's are in the form: gpio_padcfg GPP_B_1 [0x6e, 01] DW0 [0x40000400] DW1 [0x0003c119] DW2 [0x00000100] DW3 [0x00000000] Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I351a8d981d4cf495d0de254f6f2a24060551749d --- M src/soc/intel/tigerlake/gpio.c 1 file changed, 55 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41058/1 diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index cfdd0ac..7713535 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -37,39 +37,79 @@ }; /* - * This layout matches the Linux kernel pinctrl map for TGL-LP at: + * The GPIO pinctrl driver for Tiger Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + * + * This layout matches the Linux kernel pinctrl map for TGL at: * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c */ static const struct pad_group tgl_community0_groups[] = { - INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */ - INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */ - INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0, "B"), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32, "T"), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 64, "A"), /* GPP_A */ +#else + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 3), /* GPP_T */ + INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_A24, 6), /* GPP_A */ +#endif }; static const struct pad_group tgl_community1_groups[] = { - INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */ - INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */ - INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */ - INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */ - INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96, "S"), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128, "H"), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160, "D"), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192, "U"), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224, "VGPIO"), /* GPP_VGPIO */ +#else + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ + INTEL_GPP_BASE(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK, 192), /* GPP_U */ + INTEL_GPP_BASE(GPP_S0, CNV_BTEN, vI2S2_RXD, 224), /* GPP_VGPIO */ +#endif }; /* This community is not visible to the OS */ static const struct pad_group tgl_community2_groups[] = { +#if CONFIG(DEBUG_GPIO) + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB, "GPD"), /* GPD */ +#else INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +#endif }; static const struct pad_group tgl_community4_groups[] = { - INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */ - INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */ - INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ - INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256, "C"), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288, "F"), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB, "HVCMOS"), /* GPP_HVCMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320, "E"), /* GPP_E */ + INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE, "JTAG"), /* GPP_JTAG */ +#else + INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ + INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ + INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */ + INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */ +#endif }; static const struct pad_group tgl_community5_groups[] = { - INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */ - INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +#if CONFIG(DEBUG_GPIO) + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352, "R"), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK, "SPI"), /* GPP_SPI */ +#else + INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ + INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ +#endif }; static const struct pad_community tgl_communities[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I351a8d981d4cf495d0de254f6f2a24060551749d Gerrit-Change-Number: 41058 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: mainboard/volteer: Enable TcssDma1 and TbtPcie2 & 3
by Shreesh Chhabbi (Code Review) 09 Jun '23

09 Jun '23

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42442 ) Change subject: mainboard/volteer: Enable TcssDma1 and TbtPcie2 & 3 ...................................................................... mainboard/volteer: Enable TcssDma1 and TbtPcie2 & 3 Change-Id: I40fda5506de52cfd7cf03093efa737a2c1bcb068 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42442/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8ff790e..c41fe2e 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -150,12 +150,12 @@ register "TcssAuxOri" = "1" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" - register "IomTypeCPortPadCfg[2]" = "0x0" - register "IomTypeCPortPadCfg[3]" = "0x0" - register "IomTypeCPortPadCfg[4]" = "0x0" - register "IomTypeCPortPadCfg[5]" = "0x0" - register "IomTypeCPortPadCfg[6]" = "0x0" - register "IomTypeCPortPadCfg[7]" = "0x0" + register "IomTypeCPortPadCfg[2]" = "0x09000000" + register "IomTypeCPortPadCfg[3]" = "0x09000000" + register "IomTypeCPortPadCfg[4]" = "0x09000000" + register "IomTypeCPortPadCfg[5]" = "0x09000000" + register "IomTypeCPortPadCfg[6]" = "0x09000000" + register "IomTypeCPortPadCfg[7]" = "0x09000000" # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" @@ -267,15 +267,15 @@ device pci 06.0 off end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 off end # TBT_PCIe2 0x9A27 - device pci 07.3 off end # TBT_PCIe3 0x9A29 + device pci 07.2 on end # TBT_PCIe2 0x9A27 + device pci 07.3 on end # TBT_PCIe3 0x9A29 device pci 08.0 on end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0d.3 on end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) -- To view, visit https://review.coreboot.org/c/coreboot/+/42442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40fda5506de52cfd7cf03093efa737a2c1bcb068 Gerrit-Change-Number: 42442 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: [WIP][DONOTMERGE]: Print GPIO DW's for every community
by Shaunak Saha (Code Review) 09 Jun '23

09 Jun '23

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41057 ) Change subject: [WIP][DONOTMERGE]: Print GPIO DW's for every community ...................................................................... [WIP][DONOTMERGE]: Print GPIO DW's for every community Function to print every gpio DW value. The values would be printed in order of community as defined in soc's gpio.c community array. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I0b7b6963cbe1af8264461b0149681fbcb37bf416 Change-Id: I5f7b9b3d62317dd153a63e684a6193a05d037c61 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 62 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41057/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index e73c776..a5c554c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -298,12 +298,47 @@ gpi_enable_smi(cfg, comm); } +#if CONFIG(DEBUG_GPIO) +void gpio_print_pads(void) +{ + size_t gpio_communities; + const struct pad_community *comm; + uint32_t i, j, k, l; + const struct pad_group *group_curr; + uint32_t comm_size = 0; + uint16_t config_offset; + uint32_t pad_conf; + + comm = soc_gpio_get_community(&gpio_communities); + + for (i = 0; i < gpio_communities; i++) { + group_curr = comm->groups; + for (j = 0; j < comm->num_groups; j++) { + for (k = 0; k < group_curr->size; k++) { + i config_offset = pad_config_offset(comm, (comm_size + k)); + printk(BIOS_DEBUG, "gpio_padcfg GPP_%s_%d [0x%02x, %02zd] ", + group_curr->grp_name, k, comm->port, relative_pad_in_comm(comm, (comm_size+k))); + for (l = 0; l < GPIO_NUM_PAD_CFG_REGS; l++) { + pad_conf = pcr_read32(comm->port, PAD_CFG_OFFSET(config_offset, l)); + printk(BIOS_DEBUG, " DW%d [0x%08x]", l, pad_conf); + } + printk(BIOS_DEBUG, "\n"); + } + comm_size = comm_size + group_curr->size; + group_curr++; + } + comm++; + } +} +#endif + void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) { size_t i; for (i = 0; i < num_pads; i++) gpio_configure_pad(cfg + i); + } /* diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index db0f503..1267cb2 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -39,6 +39,20 @@ #ifndef __ACPI__ #include <types.h> +#if CONFIG(DEBUG_GPIO) +#define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + group_pad_base, name) \ + { \ + .first_pad = (start_of_group) - (first_of_community), \ + .size = (end_of_group) - (start_of_group) + 1, \ + .acpi_pad_base = (group_pad_base), \ + .grp_name = (name), \ + } +/* The common/default group numbering is contiguous */ +#define INTEL_GPP(first_of_community, start_of_group, end_of_group, name)\ + INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + PAD_BASE_NONE, name) +#else /* * GPIO numbers may not be contiguous and instead will have a different * starting pin number for each pad group. @@ -50,18 +64,17 @@ .size = (end_of_group) - (start_of_group) + 1, \ .acpi_pad_base = (group_pad_base), \ } - +/* The common/default group numbering is contiguous */ +#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \ + INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ + PAD_BASE_NONE) +#endif /* * A pad base of -1 indicates that this group uses contiguous numbering * and a pad base should not be used for this group. */ #define PAD_BASE_NONE -1 -/* The common/default group numbering is contiguous */ -#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \ - INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ - PAD_BASE_NONE) - /* * Following should be defined in soc/gpio.h * GPIO_MISCCFG - offset to GPIO MISCCFG Register @@ -107,6 +120,9 @@ * PAD_BASE_NONE and use contiguous numbering for ACPI. */ int acpi_pad_base; +#if CONFIG(DEBUG_GPIO) + const char *grp_name; +#endif }; /* This structure will be used to describe a community or each group within a @@ -174,6 +190,11 @@ */ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +#if CONFIG(DEBUG_GPIO) +/* Print gpio pads configured */ +void gpio_print_pads(void); +#endif + /* * gpio_configure_pads_with_override accepts as input two GPIO tables: * 1. Base config -- To view, visit https://review.coreboot.org/c/coreboot/+/41057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b9b3d62317dd153a63e684a6193a05d037c61 Gerrit-Change-Number: 41057 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

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