coreboot-gerrit November 2022

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[M] Change in coreboot[master]: drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init
by Johnny Lin (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Paul Menzel, Christian Walter, Nill Ge, TangYiwei, Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69310 ) Change subject: drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69310/comment/bd48cb50_26c04619 PS2, Line 7: src/ > Please remove. Done https://review.coreboot.org/c/coreboot/+/69310/comment/569138ad_f43e5276 PS2, Line 8: > Please describe the problem in detail. […] Done https://review.coreboot.org/c/coreboot/+/69310/comment/e180edc4_124827da PS2, Line 11: > Please mention the solution (retrying up to ten times and waiting one second), and how you determine […] The IPMI handshaking w/ BMC still relies on retry for certain IPMI commands, especially this command that would disable IPMI device if it failed. The 10 seconds retry time should be big enough and wait_ms would return early whenever the condition is satisfied, so only the worst case would take up to 10 seconds which is not supposed to happen from a SW perspective. File src/drivers/ipmi/ipmi_kcs_ops.c: https://review.coreboot.org/c/coreboot/+/69310/comment/641e07e6_c9f38b0e PS2, Line 130: } > Please use coreboot’s stopwatch framework. Maybe `wait_ms()` can be used. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Gerrit-Change-Number: 69310 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 03:20:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/scripts: Add script to run abuild on specific SOCs
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68956 ) Change subject: util/scripts: Add script to run abuild on specific SOCs ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135396 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135395 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135394 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135393 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135392 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135391 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135390 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135389 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135388 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135387 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135386 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135385 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135384 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135383 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135382 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135381 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3 Gerrit-Change-Number: 68956 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 03:17:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init
by Johnny Lin (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Nill Ge, TangYiwei. Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Christian Walter, Nill Ge, TangYiwei, Sergii Dmytruk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69310 to look at the new patch set (#3). Change subject: drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init ...................................................................... drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init Add retry up to 10 seconds maximal in ipmi_get_device_id. Without this retry, on OCP Craterlake with BMC version v2022.28.1, there's a chance that ipmi_get_device_id failed then ipmi device won't be enabled. Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 41 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/69310/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Gerrit-Change-Number: 69310 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/brya: Update devicetree setting for gladios
by Kevin Chiu (Code Review) 10 Nov '22

10 Nov '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69423 ) Change subject: mb/google/brya: Update devicetree setting for gladios ...................................................................... mb/google/brya: Update devicetree setting for gladios update devicetree setting per the schematic BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3 --- M src/mainboard/google/brya/variants/gladios/overridetree.cb 1 file changed, 324 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/69423/1 diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 4f2c04a..ae099c3 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -1,6 +1,313 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | NC | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | NC | + #| I2C5 | NC | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A1(DCI) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A3 + + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # USB TYPE C + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "led_feature" = "0xe0" + register "customized_led0" = "0x23f" + register "customized_led2" = "0x028" + register "enable_aspm_l1_2" = "1" + device pci 00.0 on end + end + end # RTL8111 Ethernet NIC + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref pcie_rp12 on + # Enable PCIE eMMC bridge 12 using clk 4 + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + end #PCIE12 EMMC + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3 Gerrit-Change-Number: 69423 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya/var/gaelin: Configure devicetree settings
by Derek Huang (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Raymond Chung, Nick Vaccaro, Eric Lai, Zhuohao Lee. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69137 ) Change subject: mb/google/brya/var/gaelin: Configure devicetree settings ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Gerrit-Change-Number: 69137 Gerrit-PatchSet: 3 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 03:01:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device/xhci: Factor out common PORTSC code
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67933 ) Change subject: device/xhci: Factor out common PORTSC code ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135380 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135379 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135378 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135377 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135376 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135375 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135374 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135373 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135372 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135371 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135370 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135369 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135368 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135367 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135366 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135365 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/67933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Gerrit-Change-Number: 67933 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:34:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: security/tpm: resolve conflicts in TSS implementations
by Julius Werner (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Erik van den Bogaert, Jason Glenesk, Raul Rangel, Michał Żygowski, Frans Hendriks, Matt DeVillier, Christian Walter, Krystian Hebel, Fred Reitberger, Yu-Ping Wu, Sergii Dmytruk, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69160 ) Change subject: security/tpm: resolve conflicts in TSS implementations ...................................................................... Patch Set 4: (5 comments) File src/security/tpm/tss.h: https://review.coreboot.org/c/coreboot/+/69160/comment/4c0031dd_43fe391f PS4, Line 26: * tlcl_lib_init(). I think you should use tlcl1_ and tlcl2_ as prefixes... mixing tlcl12_ and tlcl2_ is just confusing. https://review.coreboot.org/c/coreboot/+/69160/comment/32e28046_2580604d PS4, Line 30: * TPM1.2-specific I think this would be a good opportunity to factor this out into more files, since this one is getting quite long... I would make one for 1.2-only functions, one for 2.0-only functions, and one for the shared wrappers. File src/security/tpm/tss/tss.c: https://review.coreboot.org/c/coreboot/+/69160/comment/89a24733_90c31bf3 PS4, Line 32: #if CONFIG(TPM1) These don't need to be preprocessor #if, you can just write `if (CONFIG(TPM1) && tpm_family == 1)`. Linker garbage collection will ensure that the code for compiled-out versions doesn't get pulled into the final binary. https://review.coreboot.org/c/coreboot/+/69160/comment/4647751c_ce998039 PS4, Line 35: return VB2_SUCCESS; Why don't you just make tis_sendrecv an exported global in this file that can be directly accessed from the other files, rather than passing this pointer back and forth between so many files? https://review.coreboot.org/c/coreboot/+/69160/comment/1f49a065_236180aa PS4, Line 62: die("%s: can't be used with TPM %d\n", __func__, tpm_family); nit: not really sure you need these since it shouldn't be possible to get to this place (tlcl_lib_init() would have already resulted in an error). -- To view, visit https://review.coreboot.org/c/coreboot/+/69160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Gerrit-Change-Number: 69160 Gerrit-PatchSet: 4 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/gaelin: Configure devicetree settings
by Raymond Chung (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Nick Vaccaro, Eric Lai, Zhuohao Lee. Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69137 ) Change subject: mb/google/brya/var/gaelin: Configure devicetree settings ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69137/comment/4ea2eb29_5d3018fc PS2, Line 7: gaelin > missing var/ Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Gerrit-Change-Number: 69137 Gerrit-PatchSet: 3 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:19:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/gaelin: Configure devicetree settings
by Raymond Chung (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Raymond Chung, Nick Vaccaro, Zhuohao Lee. Hello build bot (Jenkins), Tarun Tuli, Derek Huang, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69137 to look at the new patch set (#3). Change subject: mb/google/brya/var/gaelin: Configure devicetree settings ...................................................................... mb/google/brya/var/gaelin: Configure devicetree settings Override devicetree configuration based on the latest gaelin schematic. BUG=b:249000573, b:254375472 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- M src/mainboard/google/brya/variants/gaelin/overridetree.cb 1 file changed, 221 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/69137/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256 Gerrit-Change-Number: 69137 Gerrit-PatchSet: 3 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bruce Chiang <brucechiang(a)msi.corp-partner.google.com> Gerrit-CC: Eason Chang <easonchang(a)msi.corp-partner.google.com> Gerrit-CC: Eddy Lu <eddylu(a)ami.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
by Macpaul Lin (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Chen-Tsung Hsieh, Martin L Roth, Julius Werner, Yidi Lin. Macpaul Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66625 ) Change subject: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Thanks you all! However, I've found there are rebase conflicts, will check these issue later. Hope these files were just moved to common driver. 😊 Quote error log: Could not perform action: The change could not be rebased due to a conflict during merge. merge conflict(s): src/soc/mediatek/mt8195/dptx.c src/soc/mediatek/mt8195/dptx_hal.c src/soc/mediatek/mt8195/include/soc/dp_intf.h src/soc/mediatek/mt8195/include/soc/dptx.h src/soc/mediatek/mt8195/include/soc/dptx_hal.h src/soc/mediatek/mt8195/include/soc/dptx_reg.h -- To view, visit https://review.coreboot.org/c/coreboot/+/66625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Gerrit-Change-Number: 66625 Gerrit-PatchSet: 7 Gerrit-Owner: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 02:17:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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