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Change subject: mb/google/nissa: Remove SI_ME subregions
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya/variants/volmar: Update ELAN touchscreen timing
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69559/comment/dd254fb2_8b25fd32
PS1, Line 11: Correct the delay time to 150ms to follow the spec.
Needn't warp line.
Patchset:
PS1:
Change to 150 will impact the resume time.
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Change subject: mb/google/skyrim/var/winterhold: update thermal config
......................................................................
mb/google/skyrim/var/winterhold: update thermal config
Enable STT and set 6 thermal table profiles for Dynamic Thermal Table Switching Proposal support.
BUG=b:232946420
BRANCH=none
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823
---
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
1 file changed, 107 insertions(+), 0 deletions(-)
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Change subject: mb/google/skyrim/var/winterhold: update thermal config
......................................................................
Patch Set 22:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68472/comment/46e67e89_e403e320
PS21, Line 9: Enable STT and set 6 thermal table profiles for
: Dynamic Thermal Table Switching Proposal support
> Would you please reflow for 72 characters per line?
Done
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Change subject: mb/google/skyrim/var/winterhold: update thermal config
......................................................................
mb/google/skyrim/var/winterhold: update thermal config
Enable STT and set 6 thermal table profiles for Dynamic Thermal Table Switching Proposal support
BUG=b:232946420
BRANCH=none
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823
---
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
1 file changed, 107 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/68472/22
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Change subject: ec/google/chromec: Add DPTC support for host event 1/2/9
......................................................................
ec/google/chromec: Add DPTC support for host event 1/2/9
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event lid-open/lid-close/Thermal Threshold.
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M src/ec/google/chromeec/acpi/ec.asl
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Change subject: commonlib/fsp_relocate: Fix Coverity Issues
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68637/comment/3dbf07d6_0833cba2
PS3, Line 18: on my own to test my changes against coverity tests.
> Check [CB:69408], I am able to do so.
Done
File src/commonlib/fsp_relocate.c:
https://review.coreboot.org/c/coreboot/+/68637/comment/56813738_1484d084
PS4, Line 230: offset_limit = roffset + rsize;
Fixes issue reported as below:
Coverity issue:
*** CID 1498391: (TAINTED_SCALAR)
/src/commonlib/fsp_relocate.c: 229 in pe_relocate()
223 rsize = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].Size);
224 roffset = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress);
225 printk(FSP_DBG_LVL, "relocation table at offset-%x,size=%x\n", roffset, rsize);
226 // TODO - add support for PE32+ also
227
228 offset = roffset;
CID 1498391: (TAINTED_SCALAR)
Using tainted variable "roffset + rsize" as a loop boundary.
229 while (offset < (roffset + rsize)) {
230 uint32_t vaddr;
231 uint32_t rlen, rnum;
232 uint16_t *rdata;
233 uint32_t i;
234 EFI_IMAGE_DATA_DIRECTORY *relocd;
https://review.coreboot.org/c/coreboot/+/68637/comment/1dc1dcdf_2dbcbc5c
PS4, Line 258: ptr = &pe_base[aoff];
Fixes the below reported Coverity issue.
Coverity Issue:
*** CID 1498391: (TAINTED_SCALAR)
250 printk(FSP_DBG_LVL, "\t\treloc type %x offset %x aoff %x, base-0x%x\n",
251 rtype, roff, aoff, img_base_off);
252 switch (rtype) {
253 case EFI_IMAGE_REL_BASED_ABSOLUTE:
254 continue;
255 case EFI_IMAGE_REL_BASED_HIGHLOW:
CID 1498391: (TAINTED_SCALAR)
Using tainted variable "aoff" as an index to pointer "pe_base".
256 val = read_le32(&pe_base[aoff]);
257 printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n",
258 &pe_base[aoff], val, val + delta);
259 write_le32(&pe_base[aoff], val + delta);
260 break;
261 case EFI_IMAGE_REL_BASED_DIR64:
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Change subject: soc/intel/xeon_sp: lockdown LPC configuration
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68876/comment/bc1f82b5_6be79d81
PS1, Line 12: contriol
> nit: control
Done
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