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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by EricKY Cheng (Code Review) 14 Nov '22

14 Nov '22

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by EricKY Cheng (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Eric Peers, Tim Van Patten, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68471 to look at the new patch set (#39). Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... common/acpi/dptc: Implement DTTS Proposal DTTS indicated Dynamic Thermal Table Switching.The proposal would like to develop the schematic for switching 6 thermal table by lid status, machine body mode and temperature. After entering the OS, the thermal table would be table A. If the “Motion” or “Lid-status change” is detected.The thermal table would switch to laptop mode or lid-close mode. Once the higher environment temperatures are detected,the thermal table would switch to the corresponding power throttle table (B, D or F). Based on these table switching mechanisms, no matter how the end-user uses Chromebook,they could enjoy more humanized thermal designs. Release Over Over Release . Temp. Temp. Temp. Temp. . -------------------------------------------------------- . Desktop mode Table A Table B 50C 45C . Lid open (Default) . -------------------------------------------------------- . Desktop mode Table C Table D 55C 50C . Lid close . -------------------------------------------------------- . Laptop mode Table E Table F 45C 40C . -------------------------------------------------------- . On the proposal, the transmission rules are list below: 1. Table A is the default table after booting. 2. A, C, E (Release Temp) can switch to each other. 3. B, D, F (Over Temp) can switch to each other. 4. A and B, C and D, E and F can switch to each other. 5. If Lid open/close or mode switch event trigger, temperature release tables will translation to each other, temperature over tables will translation to each other.After that event trigger, EC will check the new temperature condition and decide if the temperature need to be trigger.For example, if table A will switch to table D, table A will switch to C with Lid close event, if temperature is over 55C, EC will trigger temperature to switch form table C to D. 6. EC will trigger 3 times body-detection events during power on boot without any body-mode and lid status change. For this case if the previous table label is on same group, we will based on the temperature to decide the table. For example, assume table A is current table. When the temperature reaches 50C, than the table is switched from A to B. The current table is B. When the temperature is downgrade below 45C, the table is switched form B to A. The same rule is for C and D, E and F. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 --- A src/soc/amd/common/acpi/DTTS.asl M src/soc/amd/mendocino/acpi/soc.asl 2 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68471/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 39 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by EricKY Cheng (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... Patch Set 38: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68471/comment/f79dc173_80669e9b PS30, Line 39: Table > table Done https://review.coreboot.org/c/coreboot/+/68471/comment/39d8a358_970e7bc6 PS30, Line 40: reach > reaches Done File src/mainboard/google/skyrim/dsdt.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/73bf143d_6d92ccfc PS30, Line 18: variants/winterhold/DTTS.asl > Add the following include line here: […] I move DTTS.asl to src/soc/amd/common/acpi/ now File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/5a9a3a9b_4599ac15 PS12, Line 44: TIN4 > Please don't resolve comments that are still incomplete, since it makes it difficult to see there ar […] I created DTTS.asl and put it under src/soc/amd/common/acpi/. src/soc/amd/mendocino/acpi/soc.asl call it as below #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) #if CONFIG(FEATURE_DYNAMIC_DPTC) #include <soc/amd/common/acpi/DTTS.asl> #else #include <soc/amd/common/acpi/dptc.asl> #endif #endif File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/fe4da512_33de3565 PS21, Line 46: // AMB sensor trigger point > Please add a comment describing what conditions these checks are looking for and what the result sho […] I update the commit description with table translation rule and new code change following these rules. Please help to review that. Follow your suggestions, I will add more comment describing what conditions these checks are looking for and what the result should be. https://review.coreboot.org/c/coreboot/+/68471/comment/ca24f142_cbd1d08b PS21, Line 47: 123 > Please add a comment stating the units of these temperature values. […] There is an offset of temperature value stored in mapped memory. This allows reporting a temperature range of 200K to 454K = -73C to 181C. static void update_mapped_memory(void) #define EC_TEMP_SENSOR_OFFSET 200 So if the temperature is 50C, there will store 123(0x7b) in mapped memory. 50C=323K, 323-200(offset)=123(0x7b), example https://review.coreboot.org/c/coreboot/+/68471/comment/9fd39296_30202999 PS21, Line 57: (\_SB.PCI0.LPCB.EC0.PRTN == 2) || // Previous table is C : (\_SB.PCI0.LPCB.EC0.PRTN == 4)) // Previous table is E > Similarly, why is this state dependent on tables C/E? Follow thermal team's proposal. A, C, E tables are triggered by AMB sensor release point. B, D, F tables are triggered by AMB sensor over point. When mode change/Lid change happened, A, C, E (Release Temp) can switch to each other. B, D, F (Over Temp) can switch to each other. If temperature meets the new tables condition, EC will help to trigger thermal threshold event. Follow thermal threshold event, thermal table may translation to release temp table, over temp table or keep the previous table. So table translation is depended on previous table. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 38 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Nov 2022 08:43:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/vpd, cpu/x86/smm: Add VPD support for SMM
by Johnny Lin (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Arthur Heymans, Marc Jones, Subrata Banik, Ed Sharma, Christian Walter, Shuming Chu (Shuming), Michael Niewöhner, Kyösti Mälkki. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67092 ) Change subject: drivers/vpd, cpu/x86/smm: Add VPD support for SMM ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67092/comment/269d8e18_d1be57c7 PS4, Line 9: The main purpose is to be able to dynamically configure system during : SMM boot time via VPD. > It does way more than fulfill that purpose. […] It's safer to pass each config variable ex. 'var' by mod_params->var, I wonder if there are multiple config variables is there a generic way to pass them, otherwise need to add each one of them to mod_params. VPD driver is a generic way but it does bloat the runtime and not that safe. -- To view, visit https://review.coreboot.org/c/coreboot/+/67092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I418568ef53b6de46db9b02846543e592930effd3 Gerrit-Change-Number: 67092 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 08:37:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/mrc_cache: Prevent printing errors in expected use cases
by Yu-Ping Wu (Code Review) 14 Nov '22

14 Nov '22

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69542 ) Change subject: drivers/mrc_cache: Prevent printing errors in expected use cases ...................................................................... drivers/mrc_cache: Prevent printing errors in expected use cases The following are considered "expected" situations, where we shouldn't print error messages as in other unexpected errors: 1. When the previous boot is in recovery mode, under certain config combination the normal MRC cache would have been invalidated. Therefore the "couldn't read metadata" error is expected to show in the current normal boot. Special-case this situation by printing a different warning message. 2. If the platform doesn't have recovery cache (!HAS_RECOVERY_MRC_CACHE) and vboot starts before romstage (!VBOOT_STARTS_IN_ROMSTAGE), then there should be no region for recovery cache. In this case, "failed to locate region type 0" will be shown. Since it's pretty clear from the code that this is the only case for the error to happen, simply change it to a warning. BUG=b:257401937 TEST=emerge-corsola coreboot TEST=Ran `cbmem -1 | grep ERROR` in recovery boot TEST=Ran `cbmem -1 | grep ERROR` in normal boot following recovery boot BRANCH=corsola Change-Id: Ia942eeecaca3f6b2b90bac725279d2dc6174e0fd Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/drivers/mrc_cache/mrc_cache.c 1 file changed, 45 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/69542/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index fd3853f..1216463 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -25,6 +25,8 @@ /* Signature "MRCD" was used for older header format before CB:67670. */ #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('d'<<24)) +const static uint32_t mrc_invalid_sig = ~MRC_DATA_SIGNATURE; + struct mrc_metadata { uint32_t signature; uint32_t data_size; @@ -154,8 +156,7 @@ cr = lookup_region_type(type); if (cr == NULL) { - printk(BIOS_ERR, "MRC: failed to locate region type %d.\n", - type); + printk(BIOS_WARNING, "MRC: failed to locate region type %d\n", type); return NULL; } @@ -172,6 +173,14 @@ size_t size; if (rdev_readat(rdev, md, 0, sizeof(*md)) < 0) { + /* When the metadata was invalidated intentionally (for example from the + previous recovery boot), print a warning instead of an error. */ + if (rdev_readat(rdev, md, 0, sizeof(mrc_invalid_sig)) >= 0 && + md->signature == mrc_invalid_sig) { + printk(BIOS_WARNING, "MRC: metadata was invalidated\n"); + return -1; + } + printk(BIOS_ERR, "MRC: couldn't read metadata\n"); return -1; } @@ -263,7 +272,7 @@ /* Validate header and resize region to reflect actual usage on the * saved medium (including metadata and data). */ if (mrc_header_valid(rdev, md) < 0) { - printk(BIOS_ERR, "MRC: invalid header in '%s'\n", name); + printk(BIOS_WARNING, "MRC: invalid header in '%s'\n", name); return fail_bad_data ? -1 : 0; } @@ -595,7 +604,6 @@ struct region_file cache_file; struct region_device rdev; const char *name = DEFAULT_MRC_CACHE; - const uint32_t invalid = ~MRC_DATA_SIGNATURE; /* * If !HAS_RECOVERY_MRC_CACHE and VBOOT_STARTS_IN_ROMSTAGE is @@ -631,7 +639,8 @@ /* Push an update that consists of 4 bytes that is smaller than the * MRC metadata as well as an invalid signature. */ - if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + if (region_file_update_data(&cache_file, &mrc_invalid_sig, + sizeof(mrc_invalid_sig)) < 0) printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia942eeecaca3f6b2b90bac725279d2dc6174e0fd Gerrit-Change-Number: 69542 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
by EricKY Cheng (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Isaac Lee, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68942 ) Change subject: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/68942/comment/57199633_42340fdd PS8, Line 146: FEATURE_DYNAMIC_DPTC > Done This is the CL before the others on the relation chain and only define but not enable. We have the FEATURE_DYNAMIC_DPTC enable on the top of the relation chain. Could we merged this first? Or I need to move the position of this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/68942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3db70c151f962184e0475a8d11a51568f4b8ced3 Gerrit-Change-Number: 68942 Gerrit-PatchSet: 8 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Mon, 14 Nov 2022 08:30:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Makefile.inc: Remove workaround ACPI warnings
by Elyes Haouas (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Martin L Roth, Angel Pons, Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69514 ) Change subject: Makefile.inc: Remove workaround ACPI warnings ...................................................................... Patch Set 1: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/69514/comment/33c8165c_ed23b1b8 PS1, Line 275: IASL_MISSING_DEPENDENCY = 3141 it still necessary. https://qa.coreboot.org/job/coreboot-toolchain/1276/#showFailuresLink -- To view, visit https://review.coreboot.org/c/coreboot/+/69514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef Gerrit-Change-Number: 69514 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 14 Nov 2022 08:24:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
by EricKY Cheng (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Isaac Lee, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68942 ) Change subject: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/68942/comment/50c7d284_9f615662 PS8, Line 146: FEATURE_DYNAMIC_DPTC > Merge this with the CL that actually implements this Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3db70c151f962184e0475a8d11a51568f4b8ced3 Gerrit-Change-Number: 68942 Gerrit-PatchSet: 8 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Mon, 14 Nov 2022 08:23:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by EricKY Cheng (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Martin Roth, Tim Van Patten, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Eric Peers, Tim Van Patten, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68471 to look at the new patch set (#38). Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... common/acpi/dptc: Implement DTTS Proposal DTTS indicated Dynamic Thermal Table Switching.The proposal would like to develop the schematic for switching 6 thermal table by lid status, machine body mode and temperature. After entering the OS, the thermal table would be table A. If the “Motion” or “Lid-status change” is detected.The thermal table would switch to laptop mode or lid-close mode. Once the higher environment temperatures are detected,the thermal table would switch to the corresponding power throttle table (B, D or F). Based on these table switching mechanisms, no matter how the end-user uses Chromebook,they could enjoy more humanized thermal designs. Release Over Over Release . Temp. Temp. Temp. Temp. . -------------------------------------------------------- . Desktop mode Table A Table B 50C 45C . Lid open (Default) . -------------------------------------------------------- . Desktop mode Table C Table D 55C 50C . Lid close . -------------------------------------------------------- . Laptop mode Table E Table F 45C 40C . -------------------------------------------------------- . On the proposal, the transmission rules are list below: 1. Table A is the default table after booting. 2. A, C, E (Release Temp) can switch to each other. 3. B, D, F (Over Temp) can switch to each other. 4. A and B, C and D, E and F can switch to each other. 5. Assume table A is current table. When the temperature reaches 50C, than the table is switched from A to B. 6. Based on 4. The current table is B. When the temperature is downgrade below 45C, the table is switched form B to A. 7. Based on 4 an 5, the same rule is for C and D, E and F. 8. If Lid open/close or mode switch event trigger, temperature release tables will translation to each other, temperature over tables will translation to each other.After that event trigger, EC will check the new temperature condition and decide if the temperature need to be trigger.For example, if table A will switch to table D, table A will switch to C with Lid close event, if temperature is over 55C, EC will trigger temperature to switch form table C to D. 9. EC will trigger 3 times body-detection events during power on boot without any body-mode and lid status change. For this case if the previous table label is on same group, we will based on the temperature to decide the table. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 --- A src/soc/amd/common/acpi/DTTS.asl M src/soc/amd/mendocino/acpi/soc.asl 2 files changed, 179 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68471/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 38 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Set DPTC Electrical Parameters
by John Su (Code Review) 14 Nov '22

14 Nov '22

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69565 ) Change subject: mb/google/skyrim/var/frostflow: Set DPTC Electrical Parameters ...................................................................... mb/google/skyrim/var/frostflow: Set DPTC Electrical Parameters Set DPTC Electrical Parameters form AMD DevHub document #57316. "system_configuration" = "4" "slow_ppt_limit_mW" = "15000" "fast_ppt_limit_mW" = "22000" "stapm_time_constant_s" = "200" "thermctl_limit_degreeC" = "100" "vrm_current_limit_mA" = "28000" "vrm_maximum_current_limit_mA" = "50000" "vrm_soc_current_limit_mA" = "10000" BRANCH=none BUG=b:257187831 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a --- M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69565/1 diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index a3858c8..5581d40 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -1,6 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/mendocino + # System config index + register "system_configuration" = "4" + + # Set DPTC Electrical Parameters + register "slow_ppt_limit_mW" = "15000" + register "fast_ppt_limit_mW" = "22000" + register "stapm_time_constant_s" = "200" + register "thermctl_limit_degreeC" = "100" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller -- To view, visit https://review.coreboot.org/c/coreboot/+/69565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a Gerrit-Change-Number: 69565 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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