coreboot-gerrit November 2022

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[S] Change in coreboot[master]: drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed comment
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Jan Samek has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69545 ) Change subject: drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed comment ...................................................................... drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed comment There is a note about the default I2C speed of this being 400 kHz despite the logic in rx6110sa.c sets the fallback (correctly) to 100 kHz. This information originally comes from the fact the dw_i2c bus controller default speed is 400 kHz. This is irrelevant to the default speed of this device as it can be used with any bus controller. BUG=none TEST=coreboot builds correctly (no functional changes). Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/drivers/i2c/rx6110sa/chip.h 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/69545/1 diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index 4df9580..1c0abe8 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -3,7 +3,7 @@ #include "rx6110sa.h" struct drivers_i2c_rx6110sa_config { - unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz)*/ + unsigned int bus_speed; /* Bus clock in Hz */ /* The day (of the week) is indicated by 7 bits, bit 0 to bit 6. */ unsigned char user_weekday; /* User day of the week to set */ unsigned char user_day; /* User day to set */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341 Gerrit-Change-Number: 69545 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/nissa: Remove SI_ME subregions
by Sridhar Siricilla (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Reka Norman. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69540 ) Change subject: mb/google/nissa: Remove SI_ME subregions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c Gerrit-Change-Number: 69540 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Mon, 14 Nov 2022 16:05:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/Kconfig: Don't allow native mode in x86_64
by Paul Fagerburg (Code Review) 14 Nov '22

14 Nov '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69506 ) Change subject: device/Kconfig: Don't allow native mode in x86_64 ...................................................................... device/Kconfig: Don't allow native mode in x86_64 This option is not working so don't advertise it. Change-Id: I910162756a567289b2484a5445360a3197ae848c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69506 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/device/Kconfig 1 file changed, 16 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index a41f261..34600ad 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -197,7 +197,7 @@ config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_X86 && !ARCH_RAMSTAGE_X86_64 help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, -- To view, visit https://review.coreboot.org/c/coreboot/+/69506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910162756a567289b2484a5445360a3197ae848c Gerrit-Change-Number: 69506 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: arch/x86/Kconfig: Move AMD stages arch to common code
by Paul Fagerburg (Code Review) 14 Nov '22

14 Nov '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69505 ) Change subject: arch/x86/Kconfig: Move AMD stages arch to common code ...................................................................... arch/x86/Kconfig: Move AMD stages arch to common code Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE needs to be build as x86 stage. Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/arch/x86/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/mendocino/Kconfig M src/soc/amd/morgana/Kconfig M src/soc/amd/picasso/Kconfig 6 files changed, 19 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b60f600..f7b9250 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -28,9 +28,9 @@ config ARCH_ALL_STAGES_X86_32 bool - default ARCH_ALL_STAGES_X86 && !ARCH_ALL_STAGES_X86_64 + default !ARCH_ALL_STAGES_X86_64 select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_SUPPORTS_CLANG @@ -61,14 +61,10 @@ config ARCH_ALL_STAGES_X86_64 bool select ARCH_BOOTBLOCK_X86_64 - select ARCH_VERSTAGE_X86_64 + select ARCH_VERSTAGE_X86_64 if !VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_ROMSTAGE_X86_64 select ARCH_RAMSTAGE_X86_64 -config ARCH_ALL_STAGES_X86 - bool - default y - config HAVE_EXP_X86_64_SUPPORT bool help diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1630df2..30e3e73 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -10,10 +10,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -88,9 +84,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/cezanne/chipset.cb" diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 6c09ac9..5bf1d5f 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -13,10 +13,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -93,9 +89,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/glinda/chipset.cb" diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 9da6138..05c349f 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -23,10 +23,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -106,9 +102,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index 37d3613..23d296c 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -13,10 +13,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -93,9 +89,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/morgana/chipset.cb" diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e852826..7f56803 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -11,10 +11,6 @@ def_bool y select ACPI_SOC_NVS select ADD_FSP_BINARIES if USE_AMD_BLOBS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK @@ -80,9 +76,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/picasso/chipset.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/69505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Gerrit-Change-Number: 69505 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/rv3028c7/chip.h: https://review.coreboot.org/c/coreboot/+/69543/comment/2cd330fd_0d9e606a PS1, Line 38: unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz) */ > [After a direct discussion with Werner] it's clear that there's no direct relation with dw_i2c and t […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 15:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Hello Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69543 to look at the new patch set (#2). Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... drivers/i2c/rv3028c7: Add ACPI generation callbacks Added ACPI generation callback to the driver after obtaining the ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY"). Also added I2C bus speed field to the device config structure, which is a required ACPI entry. BUG=none TEST=Disassemble the SSDT table and see whether the device entry "MC28" is generated correctly. Also check whether the RV3028 driver in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding an ACPI match table to it containing the HID (a proper kernel patch is pending). Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/drivers/i2c/rv3028c7/chip.h M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rv3028c7/rv3028c7.h 3 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69543/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: drivers/intel/fsp2_0/hand_off_block: add functions to iterate over HOBs
by Martin Roth (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Martin L Roth, Andrey Petrov, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69475 ) Change subject: drivers/intel/fsp2_0/hand_off_block: add functions to iterate over HOBs ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/69475/comment/e3b6361e_421f32b7 PS1, Line 140: while ((*hob_iterator)->type != HOB_TYPE_END_OF_HOB_LIST) { > this is the check that is in all other HOB access functions use in coreboot and i'm not sure what el […] Okay, it sounds like we need a wider fix then. I see two options. We can set a max number of expected HOBs. 200? 10000? whatever, and bail if we loop that many times. Alternatively, we can set a timeout value in ms and error out if we hit that. -- To view, visit https://review.coreboot.org/c/coreboot/+/69475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86dde2a9f41d0ca7941493a92f11b91a77e2ae0 Gerrit-Change-Number: 69475 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Nov 2022 15:50:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/rv3028c7/chip.h: https://review.coreboot.org/c/coreboot/+/69543/comment/5a1415ca_4098896d PS1, Line 38: unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz) */ > The term 'default' here means the default speed the DW-I2C controller uses. In dw_i2c. […] [After a direct discussion with Werner] it's clear that there's no direct relation with dw_i2c and this comment should be removed (also from RX6110 driver) to avoid further confusion. -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 15:47:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion
by Felix Held (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69507 ) Change subject: soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e Gerrit-Change-Number: 69507 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 15:35:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/rv3028c7/rv3028c7.c: https://review.coreboot.org/c/coreboot/+/69543/comment/ef6a7ce8_842c9268 PS1, Line 197: bus_speed = I2C_SPEED_STANDARD; > Yes, fall back to lowest possible mode to ensure bus stability in case of doubt. […] OK, this makes sense. Keeping 100 kHZ as a fallback. -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 15:08:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2022