Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69503 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: cpu/cpu.h: Remove unused functions prototypes
......................................................................
cpu/cpu.h: Remove unused functions prototypes
These were dropped with LEGACY_SMP_INIT.
Change-Id: Iecaf9ba3d31d22311557b885b31e98a0edd74d96
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69503
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/include/cpu/cpu.h
1 file changed, 15 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Elyes Haouas: Looks good to me, approved
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index e668de8..955bd73 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -13,8 +13,6 @@
/* Function to keep track of cpu default apic_id */
void cpu_add_map_entry(unsigned int index);
struct bus;
-void initialize_cpus(struct bus *cpu_bus);
-asmlinkage void secondary_cpu_init(unsigned int cpu_index);
int cpu_phys_address_size(void);
#if ENV_RAMSTAGE
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69503 )
Change subject: cpu/cpu.h: Remove unused functions prototypes
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69503/comment/f970ad2b_066f0677
PS1, Line 7: cpu/cpu.h: Remove unused functions
> do you want to rename this to "cpu/cpu. […]
Done
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Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 )
Change subject: cpu/x86/smm: Enable setting SMM console log level from mainboard
......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS23:
Build failure was due to poor configuration on a new builder. Added it to the queue again.
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David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 )
Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
......................................................................
Patch Set 6:
(1 comment)
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/bccbe394_f697ec67
PS5, Line 105:
> But the original struct had no blank line in between, thus I will remove the line in the next patchs […]
Done
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Hello build bot (Jenkins), Jonathan Zhang, weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Sean Rhodes, Tarun Tuli, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
......................................................................
soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.
This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.
Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.
This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.
Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
---
M src/include/memory_info.h
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/apollolake/meminit_util_apl.c
M src/soc/intel/apollolake/meminit_util_glk.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/common/smbios.c
M src/soc/intel/common/smbios.h
M src/soc/intel/elkhartlake/romstage/romstage.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/meteorlake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
M src/soc/intel/xeon_sp/cpx/romstage.c
14 files changed, 64 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68525/6
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68851 )
Change subject: mb/google/kahlee/mainboard: rewrite IRQ mapping handling
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/google/skyrim: Create crystaldrift variant
......................................................................
Patch Set 1: Code-Review+2
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Change subject: src/soc/intel/xeon_sp/ras/hest.c: fix HEST table length
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/ras/hest.c:
https://review.coreboot.org/c/coreboot/+/69500/comment/b6293907_1e5ee0f6
PS3, Line 62: void *current;
: current = (void *)(hest);
: void *next = current;
: next = hest + 1;
> Thank you for pointing out this problem of arithmetics on pointers to void. I agree with you to avoid this.
>
> By the way, the next won't be in the middle of the header, because `hest + 1' does skip the acpi_hest_t struct. And stoneyridge code also use arithmetics on pointers to void in function acpi_fill_hest.
>
Oh right. I though it would use the pointer size of the lefthand size but it does not...
> To avoid arithmetics on pointers to void completely, is it possible to add CFLAGS -Werror=pointer-arith?
It's not always bad and Linus Torvalds even argued it makes sense in some cases https://lore.kernel.org/lkml/CAHk-=whFKYMrF6euVvziW+drw7-yi1pYdf=uccnzJ8k09… . I personally prefer integers for aritmetics on pointers (that's why I got confused by hest + 1). I think there are too many cases in coreboot to enable that flag.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68852
to look at the new patch set (#4).
Change subject: mb/amd/gardenia,pademelon: rewrite IRQ mapping handling
......................................................................
mb/amd/gardenia,pademelon: rewrite IRQ mapping handling
Gardenia and Pademelon had the same mainboard_picr_data and
mainboard_intr_data data arrays. Compared to Kahlee there were 4
differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data
arrays.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ia460b467990be7c3e6261440505988a9770ea084
---
M src/mainboard/amd/gardenia/mainboard.c
M src/mainboard/amd/pademelon/mainboard.c
2 files changed, 149 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/68852/4
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Hello build bot (Jenkins), Jason Nien, Matt DeVillier, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68851
to look at the new patch set (#4).
Change subject: mb/google/kahlee/mainboard: rewrite IRQ mapping handling
......................................................................
mb/google/kahlee/mainboard: rewrite IRQ mapping handling
Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD
SoCs to allow making the largest part of the corresponding code common
for all AMD SoCs in the coreboot tree.
The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the
data tables which is the PIT IRQ which looks very wrong to me, so it was
changed to PIRQ_NC. Since the ASF and likely also the SDIO controller
are unused, this shouldn't change runtime behavior. The data tables also
had non 0 and non 0x1f entries in the following locations the internal
BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37,
0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the
description in the BKDG says that it controls the IRQ mapping of another
internal PCI device, but that PCI device doesn't exist in the SoC.
TEST=No obvious IRQ-related breakage on google/liara
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9
---
M src/mainboard/google/kahlee/mainboard.c
1 file changed, 91 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68851/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9
Gerrit-Change-Number: 68851
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
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