coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
by Frans Hendriks (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Werner Zeh. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 05:41:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
by Subrata Banik (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: weidong.wd(a)bytedance.com, Angel Pons, Arthur Heymans, TangYiwei, Andrey Petrov, Tarun Tuli, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Kapil Porwal, Tim Wawrzynczak, Lean Sheng Tan, Werner Zeh, David Milosevic, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 ) Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > Oh, sorry for the confusion. We don't have any dependencies on FSP. The problem we have is that on a DDR5 system (mb/prodrive/atlas) with 2 SO-DIMMs, the SMBIOS tables report the same locators for the DIMMs. This is because both SO-DIMMs are on "Channel 0 Slot 0", but one is on Memory Controller 0 and the other one is on Memory Controller 1. > > This change shouldn't make any meaningful difference on its own, because the `node_num` field is not consumed (yet). Thanks, that clarification. -- To view, visit https://review.coreboot.org/c/coreboot/+/68525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Gerrit-Change-Number: 68525 Gerrit-PatchSet: 4 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: weidong.wd(a)bytedance.com Gerrit-Attention: weidong.wd(a)bytedance.com Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 05:38:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
by Lean Sheng Tan (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 05:21:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Update mtcmos settings for display and audio
by Rex-BC Chen (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68489 ) Change subject: soc/mediatek/mt8188: Update mtcmos settings for display and audio ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/common/mtcmos.c: https://review.coreboot.org/c/coreboot/+/68489/comment/5f1520cb_54b857ed PS6, Line 23: ext_buck_iso > MT8183 has no such field, but has `cpu_ext_buck_iso`. […] I am not sure about that, but I think we just keep the original modification? -- To view, visit https://review.coreboot.org/c/coreboot/+/68489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Gerrit-Change-Number: 68489 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 05:08:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
by Werner Zeh (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68669/comment/030c2d9f_3ed16063 PS1, Line 7: mb/siemens/mc_ehl2 > Oh yes, you are right. Will change. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 04:57:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
by Werner Zeh (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Lean Sheng Tan. Hello build bot (Jenkins), Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68669 to look at the new patch set (#2). Change subject: soc/intel/elkhartlake: Fix incorrect divider for MDIO clock ...................................................................... soc/intel/elkhartlake: Fix incorrect divider for MDIO clock After some measurements it turned out that Elkhart Lake uses a higher CSR clock internally from which the MDIO clock is derived. In order to stay compliant with the specification, the MDIO clock needs to be lower than 2.5 MHz. Therefore, the divider needs to be 102 and not 62. This patch changes the define to match the new divider value and uses this new define at the appropriate place. Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz. Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h M src/soc/intel/elkhartlake/tsn_gbe.c 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68669/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock
by Werner Zeh (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68669/comment/f0586590_9d0f402e PS1, Line 7: mb/siemens/mc_ehl2 > should it be soc/intel/ehl instead? Oh yes, you are right. Will change. -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 04:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Add/Remove LTR disqualification for UFS
by Subrata Banik (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Haribalaraman Ramasubramanian, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Meera Ravindranath, Divagar Mohandass. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 ) Change subject: soc/intel/alderlake: Add/Remove LTR disqualification for UFS ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68251/comment/3439b322_fb6b8b5c PS6, Line 7: alderlake {adl, cmn} -- To view, visit https://review.coreboot.org/c/coreboot/+/68251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Gerrit-Change-Number: 68251 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Daniil Lunev <dlunev(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Daniil Lunev <dlunev(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 04:48:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock
by Lean Sheng Tan (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68669 ) Change subject: mb/siemens/mc_ehl2: Fix incorrect divider for MDIO clock ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68669/comment/486df4ff_edf111b7 PS1, Line 7: mb/siemens/mc_ehl2 should it be soc/intel/ehl instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/68669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Gerrit-Change-Number: 68669 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 04:37:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
by Lean Sheng Tan (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Angel Pons, Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68667 ) Change subject: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Gerrit-Change-Number: 68667 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 04:34:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2022