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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68898 )
Change subject: mb/google/brask/variants/moli: keep SAGV disable
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68898/comment/36de9912_32fbcb2d
PS4, Line 9: disable.
Note that this line really needed to be wrapped. I'll have to see why checkpatch didn't comment on it.
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68956 )
Change subject: util/scripts: Add script to run abuild on specific SOCs
......................................................................
util/scripts: Add script to run abuild on specific SOCs
If this looks useful, let me know and I'll clean it up some. This
just finds all the boards using a specified SOC and runs both CrOS
and non-CrOS abuilds on them to make sure they're working.
Nobody wants to run the full what-jenkins-does build on their host
machine. Hopefully this can help get some tests run locally before
pushing to coreboot.org.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
---
A util/scripts/testsoc
1 file changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/68956/1
diff --git a/util/scripts/testsoc b/util/scripts/testsoc
new file mode 100755
index 0000000..af24208
--- /dev/null
+++ b/util/scripts/testsoc
@@ -0,0 +1,38 @@
+#!/usr/bin/bash
+
+SOC="${1:-SOC_AMD_MENDOCINO}"
+ABUILD="./util/abuild/abuild"
+OUTPUT="coreboot-builds"
+
+if [[ ! -f "MAINTAINERS" ]]; then
+ echo "Error: This doesn't look like the coreboot directory."
+ exit 1
+fi
+
+mainboards=$(grep -r "${SOC}" src/mainboard | sed 's|src/mainboard/||;s|/Kconfig.*||')
+
+if [ -n "${mainboards}" ]; then
+ printf "Building the boards:\n%s\n\n" "${mainboards}"
+else
+ echo "Error: No mainboards using $SOC found."
+ exit 1
+fi
+
+for board in ${mainboards}; do
+ rm -rf "./${OUTPUT}"
+
+ # Non-CrOS build
+ if ! "${ABUILD}" -z -e -r -c $(nproc) -t "${board}"; then
+ echo "Error: Non-cros build of ${board} failed.
+ exit 1
+ fi
+
+ # CrOS build
+ if ! "${ABUILD}" -z -e -x -r -c $(nproc) -t "${board}"; then
+ echo "Error: CrOS build of ${board} failed.
+ exit 1
+ fi
+
+done
+
+printf "\nSuccessfully built all boards\n%s\n\n" "${mainboards}"
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68955 )
Change subject: [WIP] soc/amd/common: Add header info for STB prints to console
......................................................................
[WIP] soc/amd/common: Add header info for STB prints to console
The STB data being printed to the console wasn't clearly identified.
- Add which stage the data is being printed in.
- Add a header row to better explain the data.
TEST=Build tested only
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I368d20cb617cfefb1721a207925571064907f4d4
---
M src/soc/amd/common/block/stb/stb.c
1 file changed, 26 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/68955/1
diff --git a/src/soc/amd/common/block/stb/stb.c b/src/soc/amd/common/block/stb/stb.c
index 0cea5c3..6865b77 100644
--- a/src/soc/amd/common/block/stb/stb.c
+++ b/src/soc/amd/common/block/stb/stb.c
@@ -51,8 +51,16 @@
return;
}
- if (i == 0)
- printk(BIOS_DEBUG, "Available Smart Trace Buffer data:\n");
+ if (i == 0) {
+ const char *str = " Timestamp | Value |";
+ printk(BIOS_DEBUG, "Available %s Smart Trace Buffer data:\n",
+ ENV_STRING);
+ printk(BIOS_DEBUG, "Ofst|%s%s%s%s\n", str,
+ STB_ENTRIES_PER_ROW >= 2 ? str : "",
+ STB_ENTRIES_PER_ROW >= 3 ? str : "",
+ STB_ENTRIES_PER_ROW >= 4 ? str : "");
+ }
+
if ((i % STB_ENTRIES_PER_ROW) == 0)
printk(BIOS_DEBUG, "%04d,", i);
printk(BIOS_DEBUG, " 0x%08x,0x%08x, ", stb_val.ts, stb_val.val);
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Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59585 )
Change subject: soc/amd/*: Add PSP verstage minbuild
......................................................................
Abandoned
Never got any traction.
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68906 )
Change subject: mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz
......................................................................
mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz
Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to
382.9 kHz.
BUG=b:255505160
BRANCH=firmware-brya-14505.B
TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage
measure by scope with skolas
Signed-off-by: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com>
Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/skolas/overridetree.cb
1 file changed, 23 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb
index 110ca42..fe60e90 100644
--- a/src/mainboard/google/brya/variants/skolas/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb
@@ -95,7 +95,7 @@
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 650,
+ .rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
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