coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot
by Shelley Chen (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Ravi kumar, Paul Menzel, Sudheer Amrabadi, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 22 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:58:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot
by mturney mturney (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, Sudheer Amrabadi. mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot ...................................................................... Patch Set 22: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58545/comment/632e6f5d_649d3d7f PS21, Line 7: sc7280: Add Modem region to avoid modem cleanup in Secboot reboot. > Please remove the dot/period at the end. Ack https://review.coreboot.org/c/coreboot/+/58545/comment/c47b0288_f28b80b3 PS21, Line 8: > What is “modem cleanup”? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 22 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:53:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7280: Add support for edp and mdp driver
by build bot (Jenkins) (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Ravi kumar, Sudheer Amrabadi, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61342 ) Change subject: qualcomm/sc7280: Add support for edp and mdp driver ...................................................................... Patch Set 3: Verified+1 (2 comments) File src/mainboard/google/herobrine/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139424): https://review.coreboot.org/c/coreboot/+/61342/comment/dcec886a_196eb83d PS3, Line 61: if (display_init_required()) { suspect code indent for conditional statements (8, 24) File src/soc/qualcomm/sc7280/display/edp_ctrl.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139424): https://review.coreboot.org/c/coreboot/+/61342/comment/5ada71fc_d18a354f PS3, Line 863: ret = edp_start_link_train_2(ctrl,dpcd); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/61342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89abb76028766b19450e756889a5d7776106f95 Gerrit-Change-Number: 61342 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:40:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Tim Wawrzynczak (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 ) Change subject: device: Add support for PCIe Resizable BARs ...................................................................... Patch Set 2: (4 comments) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/61215/comment/26f8fad6_905334bd PS2, Line 656: For instance, if a device requests : 30 bits of address space (1 GiB), but this field is set to 29, then : the device will only be allocated 29 bits worth of address space (512 : MiB). > what will be the case when device may request for 28 bits address space (256MB) and default is set t […] Correct, it is the default MAX number of bits of address space to hand out, so if the device requests less than that, that's fine and that's what it gets. File src/device/pci_device.c: https://review.coreboot.org/c/coreboot/+/61215/comment/4e8ca019_68af794f PS2, Line 324: ctrl0 > > can we rename this to rebar_ctrl_reg or ctrl_reg. […] This is the Resizable BAR Control Register for BAR 0; the field NBARs, although it is in the control register for each BAR, it only contains a valid value in BAR 0; i.e., you can't have less than 1 Resizable BAR (BAR 0 has to be supported if any are). https://review.coreboot.org/c/coreboot/+/61215/comment/f3bc7b26_a3a2a130 PS2, Line 324: const uint32_t ctrl0 = pci_read_config32( : dev, offset + PCI_REBAR_CTRL_OFFSET); > nit: I believe it can fit even in single line? Done https://review.coreboot.org/c/coreboot/+/61215/comment/4e3a5083_77bd9bd1 PS2, Line 330: ctrl > regbar_cap_reg ? this is the control register, but I'll give it a better name -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:33:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Add support for PCIe Resizable BARs
by Tim Wawrzynczak (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Hello build bot (Jenkins), Nico Huber, Subrata Banik, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61215 to look at the new patch set (#3). Change subject: device: Add support for PCIe Resizable BARs ...................................................................... device: Add support for PCIe Resizable BARs Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability. When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range. This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig. BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf --- M src/device/Kconfig M src/device/pci_device.c M src/include/device/pci_def.h M src/include/device/resource.h 4 files changed, 180 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/61215/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Gerrit-Change-Number: 61215 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
by Cliff Huang (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61353 ) Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61353/comment/0b45db89_c8a41a2c PS1, Line 9: - > ok Done File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/61353/comment/b85095aa_c7dacc7a PS1, Line 428: _ONS > sure. I will make change. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Gerrit-Change-Number: 61353 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:32:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
by Cliff Huang (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Lance Zhao, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61352 ) Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61352/comment/5a06f5ab_beac8a4c PS1, Line 9: Add L23 enter/exit, modPHY power gate, and source clock control methods. : DL23: method for L2/L3 entry. : L23D: method for L2/L3 exit. : PSD0: method for modPHY power gate. : SRCK: method for enabling/disable source clock. : These optional methods are to be used in the device ACPI to construct : flows with root port's power management functions. : : Test: : Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt. > sure Done File src/soc/intel/common/block/pcie/rtd3/chip.h: https://review.coreboot.org/c/coreboot/+/61352/comment/b21be275_3956a4f1 PS1, Line 53: ext_pm_support > Actually this file would be included in `static. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f Gerrit-Change-Number: 61352 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:31:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by Jason Glenesk (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Al Hirani, Rob Barnes, Fred Reitberger. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 ) Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:07:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control
by Cliff Huang (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61353 to look at the new patch set (#3). Change subject: soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control ...................................................................... soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip control - Optional feature to provide mechanism to skip _OFF and _On execution. - It is used for the device to skip _OFF and _ON during device driver reload. - OFSK is used to skip _OFF Method at the end of device driver removal. - ONSK is used to skip _ON Method at the beginning of driver loading. - General flow use case: 1. Device driver is removed by 'rmmod' command. 2. Device _RST is called. _RST perform reset. 3. Device sets OFSK in _RST to skip the following _OFF invoked by OSPM. 4. OSPM invokes _OFF at the end of driver removal. 5. _OFF sees OFSK and skips current execution and clears OFSK so that _OFF will be executed normally next time. 6. _OFF sets ONSK to skip the following _ON invoked by OSPM. 7. Device driver is reloaded by 'insmod/modprobe' command. 8. OSPM invokes _ON at the beginning of driver loading. 9. _ON sees ONSK and skip current execution and clears ONSK so that _ON will be executed normally next time. - In normal case: When suspend, OSPM invokes _OFF. Since OFSK is not set, the device goes to deeper state as expected. When resume, OSPM invokes _ON. Sinc ONSK is not set, the device goes to active state as expected. - Generated changes: PowerResource (RTD3, 0x00, 0x0000) Name (ONSK, Zero) Name (OFSK, Zero) ... Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { ... } ElseIf ((ONSK == One)) { ONSK = Zero } } Method (_OFF, 0, Serialized) // _OFF: Power Off { If ((OFSK == Zero)) { ... } ElseIf ((OFSK == One)) { OFSK = Zero ONSK = One } } Test: Enable and verify OFSK and ONSK Name objects and the if-condition logic inside _OFF and _ON metheds is added. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/61353/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32d151d65107bfc220258c383a575e40a496b6f Gerrit-Change-Number: 61353 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
by Tim Wawrzynczak (Code Review) 28 Jan '22

28 Jan '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Selma Bensaid, Paul Menzel, Thejaswani Putta. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 ) Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support ...................................................................... Patch Set 2: (17 comments) File src/drivers/wwan/fm/acpi_fm350gl.c: https://review.coreboot.org/c/coreboot/+/61354/comment/e99258ba_47e647c7 PS2, Line 25: initializatioin `initialization` https://review.coreboot.org/c/coreboot/+/61354/comment/1ca7b7ed_0e1d7eea PS2, Line 26: rtd3 `RTD3` https://review.coreboot.org/c/coreboot/+/61354/comment/458809d0_3d21cb36 PS2, Line 57: acpigen_pop_len `acpigen_write_if_end()` https://review.coreboot.org/c/coreboot/+/61354/comment/119dd725_87a848fc PS2, Line 58: acpigen_pop_len We don't really have an `acpigen_write_else_end()` that I see https://review.coreboot.org/c/coreboot/+/61354/comment/e662f7f4_f9eef9a9 PS2, Line 59: acpigen_pop_len `acpigen_write_method_end()` https://review.coreboot.org/c/coreboot/+/61354/comment/4af08c51_588fd937 PS2, Line 82: acpigen_pop_len `acpigen_write_method_end()` https://review.coreboot.org/c/coreboot/+/61354/comment/c7f42249_fd2859dd PS2, Line 98: acpigen_pop_len `acpigen_write_method_end` https://review.coreboot.org/c/coreboot/+/61354/comment/2be17725_b1b16ae0 PS2, Line 114: acpigen_pop_len `acpigen_write_method_end` https://review.coreboot.org/c/coreboot/+/61354/comment/5a42a8f1_d29adae1 PS2, Line 155: the 5G driver is looking for MRST._RST for cold reset called during : * firmware update. suggestion: ``` NOTE: the 5G driver will call MRST._RST to trigger a cold reset during firmware update. ``` https://review.coreboot.org/c/coreboot/+/61354/comment/1f081cc8_16e4c056 PS2, Line 161: acpigen_pop_len We added a few new niceities for this like `acpigen_write_device_end()` https://review.coreboot.org/c/coreboot/+/61354/comment/467b3edc_2b85b975 PS2, Line 162: acpigen_pop_len `acpigen_write_device_end()` https://review.coreboot.org/c/coreboot/+/61354/comment/9c8af938_edbe4bb3 PS2, Line 163: acpigen_pop_len `acpigen_write_scope_end()` File src/drivers/wwan/fm/chip.h: https://review.coreboot.org/c/coreboot/+/61354/comment/c15fd32e_c58b7d5e PS2, Line 10: fcpo nit: `fcpo_gpio` https://review.coreboot.org/c/coreboot/+/61354/comment/f9f42899_e0cf2c10 PS2, Line 12: fcpo_asserted_delay_ms in other drivers that do power sequencing, we usually call these `X_on_delay_ms` and `X_off_delay_ms` etc. mind changing all of these here? https://review.coreboot.org/c/coreboot/+/61354/comment/11a9ea92_2c06f583 PS2, Line 17: reset nit: `reset_gpio` https://review.coreboot.org/c/coreboot/+/61354/comment/07b11c88_815d79b1 PS2, Line 24: perst nit: `perst_gpio` https://review.coreboot.org/c/coreboot/+/61354/comment/6b9662fe_f4f83652 PS2, Line 30: wake nit: `wake_gpio` -- To view, visit https://review.coreboot.org/c/coreboot/+/61354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566 Gerrit-Change-Number: 61354 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Fri, 28 Jan 2022 23:03:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2022