coreboot-gerrit August 2021

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Change in coreboot[master]: soc/amd/common: Update SPI based on Kconfig & EFS instead of devtree
by Martin Roth (Code Review) 14 Aug '21

14 Aug '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Martin Roth has removed Raul Rangel from this change. ( https://review.coreboot.org/c/coreboot/+/56959 ) Change subject: soc/amd/common: Update SPI based on Kconfig & EFS instead of devtree ...................................................................... Removed reviewer Raul Rangel. -- To view, visit https://review.coreboot.org/c/coreboot/+/56959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b Gerrit-Change-Number: 56959 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: tests/Makefile.inc: Add missing include paths to TEST_CFLAGS
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56933 ) Change subject: tests/Makefile.inc: Add missing include paths to TEST_CFLAGS ...................................................................... tests/Makefile.inc: Add missing include paths to TEST_CFLAGS Add missing paths to common tests cflags and remove these paths from individual tests configuration. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I13cb336195bfb06b861d7f403822f06bec8a40aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/56933 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/Makefile.inc M tests/lib/Makefile.inc 2 files changed, 3 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index f3a708a..f45638d 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -35,8 +35,9 @@ # Include generic test mock headers, before original ones TEST_CFLAGS += -I$(testsrc)/include/mocks -I$(testsrc)/include -TEST_CFLAGS += -I$(src)/include -I$(src)/commonlib/include \ - -I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include +TEST_CFLAGS += -I$(src) -I$(src)/include -I$(src)/commonlib/include \ + -I$(src)/commonlib/bsd/include -I$(src)/arch/x86/include \ + -I$(top)/3rdparty/vboot/firmware/include # Note: This is intentionally just a subset of the warnings in the toplevel # Makefile.inc. We don't need to be as strict with test code, and things like diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 028db73..45cef1b 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -73,7 +73,6 @@ fmap-test-srcs += src/lib/boot_device.c fmap-test-srcs += src/commonlib/region.c fmap-test-cflags += -I tests/include/tests/lib/fmap -fmap-test-cflags += -I 3rdparty/vboot/firmware/include imd_cbmem-ramstage-test-stage := ramstage imd_cbmem-ramstage-test-srcs += tests/lib/imd_cbmem-test.c @@ -141,7 +140,6 @@ coreboot_table-test-srcs += src/lib/coreboot_table.c coreboot_table-test-srcs += src/lib/imd_cbmem.c coreboot_table-test-srcs += src/lib/imd.c -coreboot_table-test-cflags += -I src -I 3rdparty/vboot/firmware/include coreboot_table-test-cflags += -I tests/include/tests/lib/fmap coreboot_table-test-mocks += cbmem_top_chipset @@ -175,8 +173,6 @@ cbmem_stage_cache-test-srcs += src/lib/cbmem_stage_cache.c cbmem_stage_cache-test-srcs += src/lib/imd_cbmem.c cbmem_stage_cache-test-srcs += src/lib/imd.c -cbmem_stage_cache-test-cflags += -I 3rdparty/vboot/firmware/include -cbmem_stage_cache-test-cflags += -I $(src)/commonlib/include cbmem_stage_cache-test-config += CONFIG_CBMEM_STAGE_CACHE=1 libgcc-test-srcs += tests/lib/libgcc-test.c -- To view, visit https://review.coreboot.org/c/coreboot/+/56933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13cb336195bfb06b861d7f403822f06bec8a40aa Gerrit-Change-Number: 56933 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests/Makefile.inc: Add copy-test macro
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56932 ) Change subject: tests/Makefile.inc: Add copy-test macro ...................................................................... tests/Makefile.inc: Add copy-test macro copy-test macro copies attributes from one test to another. It can be used to create multiple tests with the same subset of attributes values. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I9c9b6b12830c7060ffe5dcf35c9486655cbd08e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56932 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/Makefile.inc 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 85d30a2..f3a708a 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -94,6 +94,12 @@ Check your $(dir $(1)$(2))Makefile.inc)) endef +# Copy attributes of one test to another. +# $1 - input test name +# $2 - output test name +copy-test = $(foreach attr,$(attributes), \ + $(eval $(strip $(2))-$(attr) := $($(strip $(1))-$(attr)))) + $(call add-special-class, tests) $(call evaluate_subdirs) -- To view, visit https://review.coreboot.org/c/coreboot/+/56932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9b6b12830c7060ffe5dcf35c9486655cbd08e0 Gerrit-Change-Number: 56932 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests/Makefile.inc: Change assignments to immediate and fix style
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56931 ) Change subject: tests/Makefile.inc: Change assignments to immediate and fix style ...................................................................... tests/Makefile.inc: Change assignments to immediate and fix style Change assignments to be immediate instead of lazy. Add spaces between variable name and assignment operators to increase readability. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Idf07b5a836b33cd80c3533e582e2a1916a7bd45d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56931 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/Makefile.inc 1 file changed, 29 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index c3f5f51..85d30a2 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -1,34 +1,34 @@ # SPDX-License-Identifier: GPL-2.0-only -testsrc = $(top)/tests +testsrc := $(top)/tests # Place the build output in one of two places depending on COV, so that code # built with code coverage never mixes with code built without code coverage. ifeq ($(COV),1) -testobj = $(obj)/coverage +testobj := $(obj)/coverage else -testobj = $(obj)/tests +testobj := $(obj)/tests endif -cmockasrc = 3rdparty/cmocka -cmockaobj = $(objutil)/cmocka -coverage_dir = coverage_reports +cmockasrc := 3rdparty/cmocka +cmockaobj := $(objutil)/cmocka +coverage_dir := coverage_reports CMOCKA_LIB := $(cmockaobj)/src/libcmocka.so -CMAKE:= cmake -OBJCOPY?= objcopy -OBJDUMP?= objdump +CMAKE := cmake +OBJCOPY ?= objcopy +OBJDUMP ?= objdump -TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx -TEST_DOTCONFIG = $(testobj)/.config +TEST_DEFAULT_CONFIG := $(top)/configs/config.emulation_qemu_x86_i440fx +TEST_DOTCONFIG := $(testobj)/.config TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd TEST_KCONFIG_SPLITCONFIG := $(testobj)/config/ TEST_KCONFIG_TRISTATE := $(testobj)/tristate.conf -TEST_CFLAGS = -include $(src)/include/kconfig.h \ +TEST_CFLAGS := -include $(src)/include/kconfig.h \ -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h \ -include $(src)/include/rules.h @@ -55,7 +55,7 @@ TEST_CFLAGS += -I$(cmockasrc)/include # Link against Cmocka -TEST_LDFLAGS = -L$(cmockaobj)/src -lcmocka -Wl,-rpath=$(cmockaobj)/src +TEST_LDFLAGS := -L$(cmockaobj)/src -lcmocka -Wl,-rpath=$(cmockaobj)/src TEST_LDFLAGS += -Wl,--gc-sections # Some memlayout symbols don't work with userspace relocation -- disable it. @@ -69,26 +69,26 @@ endif # Extra attributes for unit tests, declared per test -attributes:= srcs cflags config mocks stage +attributes := srcs cflags config mocks stage -stages:= decompressor bootblock romstage smm verstage -stages+= ramstage rmodule postcar libagesa +stages := decompressor bootblock romstage smm verstage +stages += ramstage rmodule postcar libagesa -alltests:= -subdirs:= tests/arch tests/acpi tests/commonlib tests/console tests/cpu -subdirs+= tests/device tests/drivers tests/ec tests/lib tests/mainboard -subdirs+= tests/northbridge tests/security tests/soc tests/southbridge -subdirs+= tests/superio tests/vendorcode +alltests := +subdirs := tests/arch tests/acpi tests/commonlib tests/console tests/cpu +subdirs += tests/device tests/drivers tests/ec tests/lib tests/mainboard +subdirs += tests/northbridge tests/security tests/soc tests/southbridge +subdirs += tests/superio tests/vendorcode define tests-handler alltests += $(1)$(2) $(foreach attribute,$(attributes), $(eval $(1)$(2)-$(attribute) += $($(2)-$(attribute)))) $(foreach attribute,$(attributes), - $(eval $(2)-$(attribute):=)) + $(eval $(2)-$(attribute) := )) # Sanity check for stage attribute value -$(eval $(1)$(2)-stage:=$(if $($(1)$(2)-stage),$($(1)$(2)-stage),ramstage)) +$(eval $(1)$(2)-stage := $(if $($(1)$(2)-stage),$($(1)$(2)-stage),ramstage)) $(if $(findstring $($(1)$(2)-stage), $(stages)),, $(error Wrong $(1)$(2)-stage value $($(1)$(2)-stage). \ Check your $(dir $(1)$(2))Makefile.inc)) @@ -145,19 +145,19 @@ endef $(foreach test, $(alltests), \ - $(eval $(test)-srcobjs:=$(addprefix $(testobj)/$(test)/, \ + $(eval $(test)-srcobjs := $(addprefix $(testobj)/$(test)/, \ $(patsubst %.c,%.o,$(filter src/%,$($(test)-srcs))))) \ - $(eval $(test)-objs:=$(addprefix $(testobj)/$(test)/, \ + $(eval $(test)-objs := $(addprefix $(testobj)/$(test)/, \ $(patsubst %.c,%.o,$($(test)-srcs))))) $(foreach test, $(alltests), \ - $(eval $(test)-bin:=$(testobj)/$(test)/run)) + $(eval $(test)-bin := $(testobj)/$(test)/run)) $(foreach test, $(alltests), \ $(eval $(call TEST_CC_template,$(test)))) $(foreach test, $(alltests), \ - $(eval all-test-objs+=$($(test)-objs))) + $(eval all-test-objs += $($(test)-objs))) $(foreach test, $(alltests), \ - $(eval test-bins+=$($(test)-bin))) + $(eval test-bins += $($(test)-bin))) DEPENDENCIES += $(addsuffix .d,$(basename $(all-test-objs))) -include $(DEPENDENCIES) @@ -176,7 +176,7 @@ # Don't override default Kconfig variables, since this will affect all # Kconfig targets. Change them only when calling sub-make instead. -$(TEST_KCONFIG_AUTOHEADER): TEST_KCONFIG_FLAGS:= DOTCONFIG=$(TEST_DOTCONFIG) \ +$(TEST_KCONFIG_AUTOHEADER): TEST_KCONFIG_FLAGS := DOTCONFIG=$(TEST_DOTCONFIG) \ KCONFIG_AUTOHEADER=$(TEST_KCONFIG_AUTOHEADER) \ KCONFIG_AUTOCONFIG=$(TEST_KCONFIG_AUTOCONFIG) \ KCONFIG_DEPENDENCIES=$(TEST_KCONFIG_DEPENDENCIES) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/56931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf07b5a836b33cd80c3533e582e2a1916a7bd45d Gerrit-Change-Number: 56931 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/brya0: add PL4 values for different SKUs
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56916 ) Change subject: mb/google/brya/variants/brya0: add PL4 values for different SKUs ...................................................................... mb/google/brya/variants/brya0: add PL4 values for different SKUs Add PL4 values for brya0 board for different CPU SKUs. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/ramstage.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/ramstage.c b/src/mainboard/google/brya/variants/brya0/ramstage.c index 0da8eb1..9a4fc28 100644 --- a/src/mainboard/google/brya/variants/brya0/ramstage.c +++ b/src/mainboard/google/brya/variants/brya0/ramstage.c @@ -4,11 +4,11 @@ #include <device/pci_ids.h> const struct cpu_power_limits limits[] = { - /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max */ - /* PL2 values are for baseline config as per bug:191906315 comment #10 */ - { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000 }, - { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000 }, + /* SKU_ID, pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 3000, 15000, 39000, 39000, 100000}, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 4000, 28000, 43000, 43000, 105000}, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 5000, 45000, 80000, 80000, 159000}, }; void variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/56916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Gerrit-Change-Number: 56916 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56925 ) Change subject: mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5 ...................................................................... mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5 Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to higher value for USB port 5 (Type-A). BUG=b:194053549 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925 Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index f9a1201..c707c0f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -118,13 +118,13 @@ .txrestune = 1, }, .Usb2PhyPort[5] = { - .compdstune = 3, + .compdstune = 5, .sqrxtune = 3, .txfslstune = 3, .txpreempamptune = 1, .txpreemppulsetune = 0, .txrisetune = 1, - .txvreftune = 6, + .txvreftune = 9, .txhsxvtune = 3, .txrestune = 1, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/56925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Gerrit-Change-Number: 56925 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/(amd,google): Update SPI Kconfig settings based on devicetree
by Martin Roth (Code Review) 14 Aug '21

14 Aug '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56885 to look at the new patch set (#5). Change subject: mb/(amd,google): Update SPI Kconfig settings based on devicetree ...................................................................... mb/(amd,google): Update SPI Kconfig settings based on devicetree This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed --- M src/mainboard/amd/bilby/Kconfig M src/mainboard/amd/majolica/Kconfig M src/mainboard/amd/mandolin/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/zork/Kconfig 5 files changed, 75 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/56885/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Gerrit-Change-Number: 56885 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56881 ) Change subject: mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU ...................................................................... mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM configuration. TEST=Boot DDR5 MR SKU to OS. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/spd/Makefile.inc A src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex 3 files changed, 34 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 5241f96..34fc04e 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -53,9 +53,9 @@ case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - case ADL_P_DDR5_2: memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); break; + case ADL_P_DDR5_2: case ADL_P_LP4_1: case ADL_P_LP4_2: case ADL_P_LP5_1: diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 5c5c1b4..4cb0f98 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -6,5 +6,5 @@ SPD_SOURCES += adlrvp_lp5 # 0b003 SPD_SOURCES += empty # 0b004 SPD_SOURCES += empty # 0b005 -SPD_SOURCES += empty # 0b006 +SPD_SOURCES += adlrvp_ddr5_mr # 0b006 SPD_SOURCES += adlrvp_lp5 # 0b007 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex new file mode 100644 index 0000000..80ef521 --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex @@ -0,0 +1,32 @@ +30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00 +00 00 00 00 A1 01 E8 03 72 15 00 00 00 00 1E 41 +1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 47 AE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08 00 C2 C4 80 00 80 B3 80 11 00 00 00 00 00 00 +00 00 80 B3 80 11 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 0F 10 00 01 01 22 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 9C AD +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/56881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882 Gerrit-Change-Number: 56881 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/mb/google: add template files for guybrush
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56918 ) Change subject: util/mb/google: add template files for guybrush ...................................................................... util/mb/google: add template files for guybrush Create template for guyrbsuh variant creation. BRANCH=none BUG=b:194031783 TEST=n/a Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8 Signed-off-by: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- A util/mainboard/google/guybrush/template/Makefile.inc A util/mainboard/google/guybrush/template/include/variant/ec.h A util/mainboard/google/guybrush/template/include/variant/gpio.h A util/mainboard/google/guybrush/template/memory/Makefile.inc A util/mainboard/google/guybrush/template/memory/dram_id.generated.txt A util/mainboard/google/guybrush/template/memory/mem_parts_used.txt A util/mainboard/google/guybrush/template/overridetree.cb 7 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved Bhanu Prakash Maiya: Looks good to me, but someone else must approve diff --git a/util/mainboard/google/guybrush/template/Makefile.inc b/util/mainboard/google/guybrush/template/Makefile.inc new file mode 100644 index 0000000..88e75bd --- /dev/null +++ b/util/mainboard/google/guybrush/template/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./memory diff --git a/util/mainboard/google/guybrush/template/include/variant/ec.h b/util/mainboard/google/guybrush/template/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/util/mainboard/google/guybrush/template/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/util/mainboard/google/guybrush/template/include/variant/gpio.h b/util/mainboard/google/guybrush/template/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/util/mainboard/google/guybrush/template/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/util/mainboard/google/guybrush/template/memory/Makefile.inc b/util/mainboard/google/guybrush/template/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/util/mainboard/google/guybrush/template/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/util/mainboard/google/guybrush/template/memory/dram_id.generated.txt b/util/mainboard/google/guybrush/template/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/util/mainboard/google/guybrush/template/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/util/mainboard/google/guybrush/template/memory/mem_parts_used.txt b/util/mainboard/google/guybrush/template/memory/mem_parts_used.txt new file mode 100644 index 0000000..8124e4f --- /dev/null +++ b/util/mainboard/google/guybrush/template/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) diff --git a/util/mainboard/google/guybrush/template/overridetree.cb b/util/mainboard/google/guybrush/template/overridetree.cb new file mode 100644 index 0000000..c182265 --- /dev/null +++ b/util/mainboard/google/guybrush/template/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/cezanne + device domain 0 on + + end # domain +end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/56918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8 Gerrit-Change-Number: 56918 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Rename spd_info struct based on memory topology
by Nick Vaccaro (Code Review) 14 Aug '21

14 Aug '21

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56899 ) Change subject: mb/intel/adlrvp: Rename spd_info struct based on memory topology ...................................................................... mb/intel/adlrvp: Rename spd_info struct based on memory topology Naming spd_info struct based on memory topology helps in reuse of code. lp4_lp5_spd_info -> memory_down_spd_info ddr4_ddr5_spd_info -> dimm_module_spd_info Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index cccd258..5241f96 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -30,12 +30,12 @@ int board_id = get_board_id(); const bool half_populated = false; - const struct mem_spd lp4_lp5_spd_info = { + const struct mem_spd memory_down_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, .cbfs_index = get_spd_index(), }; - const struct mem_spd ddr4_ddr5_spd_info = { + const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { [0] = { @@ -54,7 +54,7 @@ case ADL_P_DDR4_2: case ADL_P_DDR5_1: case ADL_P_DDR5_2: - memcfg_init(m_cfg, mem_config, &ddr4_ddr5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: @@ -62,7 +62,7 @@ case ADL_P_LP5_2: case ADL_M_LP4: case ADL_M_LP5: - memcfg_init(m_cfg, mem_config, &lp4_lp5_spd_info, half_populated); + memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/56899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882 Gerrit-Change-Number: 56899 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit August 2021