Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52541 )
Change subject: soc/mediatek/mt8195: Add timer support
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
What is timer v1 and v2 about? Please write commit messages. Hung-Te and Yu-Ping, please ask for these things in your reviews.
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Change subject: soc/mediatek/mt8195: Add GPIO driver
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52598/comment/fb0b7814_6cc8d125
PS6, Line 8:
The commit message should contain the datasheet name and revision.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57034 )
Change subject: drivers/gfx/nvidia: Add driver for NVIDIA Optimus
......................................................................
Patch Set 2: Code-Review+1
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57034/comment/fd379ae5_1675c5ac
PS2, Line 10: GC6
What does GC6 mean?
Patchset:
PS2:
I like the idea, thank you for making CB:43615 more generic
File src/drivers/gfx/nvidia/Kconfig:
PS2:
Given that this driver is for NVIDIA Optimus, I'd place its code in a subfolder so that the path is `drivers/gfx/nvidia/optimus`. This would provide additional information about what the driver is meant to be used for.
File src/drivers/gfx/nvidia/acpi/gpu.asl:
https://review.coreboot.org/c/coreboot/+/57034/comment/76c791d8_0df5d3b5
PS2, Line 39: CONFIG_MMCONF_BASE_ADDRESS + 0x8000
CONFIG_MMCONF_BASE_ADDRESS + CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15 ?
Another option: use a SSDT. This would be more complicated, but would avoid having to hardcode ASL path names and offsets for PCI config space registers.
File src/drivers/gfx/nvidia/chip.h:
https://review.coreboot.org/c/coreboot/+/57034/comment/9c6b7cd7_4320d438
PS2, Line 7: /* TODO: Set GPIOs in devicetree? */
Yes
File src/drivers/gfx/nvidia/nvidia.c:
https://review.coreboot.org/c/coreboot/+/57034/comment/a2d911c1_32aa1398
PS2, Line 44:
nit: just one blank line?
https://review.coreboot.org/c/coreboot/+/57034/comment/9c3c09d7_0eb70a32
PS2, Line 47: if (!dev->enabled || dev->path.type != DEVICE_PATH_PCI)
Maybe sanity-check the PCI vendor ID?
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Change subject: mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for primus
......................................................................
mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for primus
Enable DRIVERS_GENESYSLOGIC_GL9755 support for primus.
BUG=b:195611000
BRANCH=None
TEST=build pass
Signed-off-by: Malik_Hsu <malik_hsu(a)wistron.corp-partner.google.com>
Change-Id: I0c60979a2d42f836e0f0261c42fcfc36c41e113a
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/57008/2
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Hello Chun-Jie Chen,
I'd like you to do a code review. Please visit
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Change subject: soc/mediatek/mt8195: Update clock square setting
......................................................................
soc/mediatek/mt8195: Update clock square setting
This patch is for reducing suspend power consumption.
1. Disable unused CLKSQ2.
2. Set CLKSQ_EN to sleep control for SPM 26M sleep control.
No bus clock when enter 26m sleep control, and only control
clock square by side band.
Signed-off-by: Chun-Jie Chen <chun-jie.chen(a)mediatek.com>
Change-Id: Ia9a1735d6f508ce35b9af2d67831a3474255198b
---
M src/soc/mediatek/mt8195/pll.c
1 file changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/57043/1
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c
index ebdc37f..74dd150 100644
--- a/src/soc/mediatek/mt8195/pll.c
+++ b/src/soc/mediatek/mt8195/pll.c
@@ -638,12 +638,18 @@
int i;
/* enable clock square */
- setbits32(&mtk_apmixed->ap_pll_con0, 0x4);
+ setbits32(&mtk_apmixed->ap_pll_con0, BIT(2));
udelay(PLL_CKSQ_ON_DELAY);
/* enable clock square1 low-pass filter */
- setbits32(&mtk_apmixed->ap_pll_con0, 0x2);
+ setbits32(&mtk_apmixed->ap_pll_con0, BIT(1));
+
+ /*
+ * BIT(3): 1 for register control; 0 for sleep control
+ * BIT(8): 1 to enable clock square2; 0 to disable it
+ */
+ clrbits32(&mtk_apmixed->ap_pll_con0, BIT(3) | BIT(8));
/* xPLL PWR ON */
for (i = 0; i < APMIXED_PLL_MAX; i++)
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Change subject: mb/google/brya/primus: modify HID to MX98357 to enable audio function
......................................................................
mb/google/brya/primus: modify HID to MX98357 to enable audio function
As discussed in b:194749863, this value will be reverted
to MX98360A until the kernel SoF driver has support.
BUG=b:194749863
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Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
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Change subject: mb/google/brya/primus: modify HID to MX98357 to enable audio function
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57038/comment/0fdc5dc0_4b9a0c9e
PS1, Line 8:
> Can you add a note that this is a W/A until the kernel SoF driver has support?
Ack
Patchset:
PS2:
Got it. Modified commit message.
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Change subject: mb/google/brya/primus: modify HID to MX98357 to enable audio function
......................................................................
mb/google/brya/primus: modify HID to MX98357 to enable audio function
As discussed in b:194749863, this value will be reverted back to MX98360
until the kernel SoF driver has support.
BUG=b:194749863
BRANCH=none
TEST=build coreboot and audio function works
Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com>
Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47
---
M src/mainboard/google/brya/variants/primus/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/57038/2
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Change subject: mb/google/dedede/var/corori: Configure GPIO settings
......................................................................
mb/google/dedede/var/corori: Configure GPIO settings
Updated the GPIO pins based on the latest schematic.
BUG=b:196867404
BRANCH=keeby
TEST=FW_NAME=corori emerge-keeby coreboot
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7
---
A src/mainboard/google/dedede/variants/corori/Makefile.inc
A src/mainboard/google/dedede/variants/corori/gpio.c
2 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/57001/2
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