coreboot-gerrit August 2021

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Change in coreboot[master]: coreboot tables: Add tcss information to coreboot table
by Nick Vaccaro (Code Review) 21 Aug '21

21 Aug '21

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57069 ) Change subject: coreboot tables: Add tcss information to coreboot table ...................................................................... coreboot tables: Add tcss information to coreboot table This change adds tcss information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and HSL orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds correctly (volteer has CONFIG_SOC_INTEL_COMMON_BLOCK_TCSS set), and TEST='emerge-brya coreboot chromeos-bootimage' and verify it builds correctly (brya does NOT have CONFIG_SOC_INTEL_COMMON_BLOCK_TCSS set) Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 5 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 91f8486..9e4deb4 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -82,6 +82,7 @@ CB_TAG_SMMSTOREV2 = 0x0039, CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_ACPI_CNVS = 0x0041, + CB_TAG_TCSS_INFO = 0x0042, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, @@ -142,6 +143,16 @@ u8 strings[0]; }; +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +struct cb_tcss_info { + u32 tag; + u32 size; + /* port_count holds number of type-c ports supported by device */ + u32 port_count; + struct tcss_config_info tcss_info[MAX_TYPE_C_PORTS]; +}; +#endif + struct cb_string { u32 tag; u32 size; diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 26dece7..0892fba 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -148,6 +148,16 @@ #if CONFIG(LP_PCI) struct pci_access pacc; #endif + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) + /* USB Type-C Port Configuration Info */ + struct { + uint8_t sbu_orientation; + uint8_t hsl_orientation; + uint8_t usb2_port_number; + uint8_t usb3_port_number; + } tcss_config_info[MAX_TYPE_C_PORTS]; +#endif }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 269275d..4436f8b 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -246,6 +246,18 @@ info->fmap_cache = get_cbmem_addr(ptr); } +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +static void cb_parse_tcss_info(void *ptr, struct sysinfo_t *info) +{ + int i; + const struct cb_tcss_info *tcss_entry = (struct cb_tcss *)ptr; + const struct tcss_config_info *tcss_info = tcss_entry->tcss_config_info; + + for (i = 0; i < tcss_entry->port_count; i++) + info->tcss_config_info[i] = tcss_info[i]; +} +#endif + #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -420,6 +432,11 @@ case CB_TAG_FMAP: cb_parse_fmap_cache(ptr, info); break; +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) + case CB_TAG_TCSS_INFO: + cb_parse_tcss_info(ptr, info); + break; +#endif default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index fd7461d5..87979ea 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -3,6 +3,7 @@ #ifndef COMMONLIB_COREBOOT_TABLES_H #define COMMONLIB_COREBOOT_TABLES_H +#include <intelblocks/tcss.h> #include <stdint.h> /* The coreboot table information is for conveying information @@ -84,6 +85,7 @@ LB_TAG_TPM_PPI_HANDOFF = 0x003a, LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, + LB_TAG_TCSS_INFO = 0x0042, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -421,6 +423,27 @@ int32_t early_cmd1_status; }; +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +/* + * USB TCSS Configuration Information + * This record contains board-specific TCSS configuration information. + * There will be one record per type-C port. + */ +struct tcss_config_info { + uint8_t usb2_port_number; + uint8_t usb3_port_number; + uint8_t sbu_orientation; + uint8_t hsl_orientation; +}; + +struct lb_tcss_info { + uint32_t tag; + uint32_t size; + uint32_t port_count; + struct tcss_config_info tcss_info[MAX_TYPE_C_PORTS]; +}; +#endif + struct lb_macs { uint32_t tag; uint32_t size; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 27f5315..6cf6160 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cbconfig.h> +#include <assert.h> #include <console/console.h> #include <console/uart.h> #include <ip_checksum.h> @@ -32,6 +33,10 @@ void lb_string_platform_blob_version(struct lb_header *header); #endif +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +int variant_get_tcss_sysinfo(struct tcss_config_info *info); +#endif + static struct lb_header *lb_table_init(unsigned long addr) { struct lb_header *header; @@ -233,6 +238,48 @@ rec->early_cmd1_status = *ms_cbmem; } +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) +int __weak variant_get_tcss_sysinfo(struct tcss_config_info *info) +{ + /* Default weak implementation - return 0 ports supported */ + return 0; +} + +static void lb_add_tcss_info(struct lb_header *header) +{ + int count = 0; + int i; + struct lb_tcss_info *rec; + struct tcss_config_info variant_tcss_info[MAX_TYPE_C_PORTS]; + + count = variant_get_tcss_sysinfo(variant_tcss_info); + if (count == 0) + return; + + ASSERT(count <= MAX_TYPE_C_PORTS); + + rec = (struct lb_tcss_info *)lb_new_record(header); + if (!rec) { + printk(BIOS_ERR, "No more room in coreboot table!\n"); + return; + } + + rec->tag = LB_TAG_TCSS_INFO; + rec->size = sizeof(*rec); + rec->port_count = count; + for (i = 0; i < count; i++) { + rec->tcss_info[i] = variant_tcss_info[i]; + + printk(BIOS_INFO, "Passing conn%d tcss info to payload: " + "usb2:%d usb3:%d sbu:%d hsl:%d\n", i, + rec->tcss_info[i].usb2_port_number, + rec->tcss_info[i].usb3_port_number, + rec->tcss_info[i].sbu_orientation, + rec->tcss_info[i].hsl_orientation); + } +} +#endif /* CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) */ + static void add_cbmem_pointers(struct lb_header *header) { /* @@ -522,6 +569,11 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); +#if CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) + /* Add tcss information */ + lb_add_tcss_info(head); +#endif + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/fsp/fsp_validate: check FSP-M binary size
by Raul Rangel (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57068 ) Change subject: soc/amd/common/fsp/fsp_validate: check FSP-M binary size ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Gerrit-Change-Number: 57068 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 20 Aug 2021 22:40:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Fix MRC cache write
by Angel Pons (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57033 ) Change subject: soc/intel/denverton_ns: Fix MRC cache write ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57033/comment/74829ce5_b0b229bd PS1, Line 10: > Please give a little more details on how it fails. Done https://review.coreboot.org/c/coreboot/+/57033/comment/c0febd4b_5016177f PS1, Line 12: Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff > Please add a tag: Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/57033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff Gerrit-Change-Number: 57033 Gerrit-PatchSet: 2 Gerrit-Owner: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 22:11:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add PCH-H GPIO definitions
by Tim Crawford (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Jeremy Soller, Tim Wawrzynczak, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56946 ) Change subject: soc/intel/tigerlake: Add PCH-H GPIO definitions ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/tigerlake/gpio_pch_h.c: https://review.coreboot.org/c/coreboot/+/56946/comment/08d38ba1_19a6bc9a PS2, Line 37: * linux/drivers/pinctrl/intel/pinctrl-tigerlake.c These were updated recently (2f658f7a395) so may need to test with 5.14-rc6. File src/soc/intel/tigerlake/include/soc/gpio_soc_defs_pch_h.h: https://review.coreboot.org/c/coreboot/+/56946/comment/c992ad9b_01f563e8 PS2, Line 117: /* Group vGPIO_0 */ Wasn't sure if these should be prefixed, since vGPIO isn't either. -- To view, visit https://review.coreboot.org/c/coreboot/+/56946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659 Gerrit-Change-Number: 56946 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 20 Aug 2021 22:11:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Fix MRC cache write
by Angel Pons (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57033 ) Change subject: soc/intel/denverton_ns: Fix MRC cache write ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff Gerrit-Change-Number: 57033 Gerrit-PatchSet: 2 Gerrit-Owner: King Sumo <kingsumos(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: King Sumo <kingsumos(a)gmail.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 22:10:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/fsp_validate: check FSP-M binary size
by Felix Held (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57068 to look at the new patch set (#2). Change subject: soc/amd/common/fsp/fsp_validate: check FSP-M binary size ...................................................................... soc/amd/common/fsp/fsp_validate: check FSP-M binary size When modules are added to the FSP and they won't fit into the FSP binary any more, the size can be increased in the FSP build. Especially in the case of debug builds the increased size might not fit into the memory region it gets put into which starts at FSP_M_ADDR and has a size of FSP_M_SIZE. SoCs can implement the soc_validate_fsp_version function that ends up being called by the FSP driver in romstage to check the FSP version, but since the image size is also present in the header we can also implement and use this function to check if it fits into the reserved region. Since the FSP-M memory region is located after romstage loading it won't clobber the romstage code where we do the check. BUG=b:186149011 TEST=Mandolin still boots fine with the patch applied. When as a test the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000 which is by far not enough for the decompressed FSP-M binary to fit into it prints the newly added error message on the console and then stops. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 --- M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/fsp_validate.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/57068/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Gerrit-Change-Number: 57068 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/fsp/fsp_validate: check FSP-M binary size
by Felix Held (Code Review) 21 Aug '21

21 Aug '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57068 ) Change subject: soc/amd/common/fsp/fsp_validate: check FSP-M binary size ...................................................................... soc/amd/common/fsp/fsp_validate: check FSP-M binary size When modules are added to the FSP and they won't fit into the FSP binary any more, the size can be increased in the FSP build. Especially in the case of debug builds the increased size might not fit into the memory region it gets put into which starts at FSP_M_ADDR and has a size of FSP_M_SIZE. SoCs can implement the soc_validate_fsp_version function that ends up being called by the FSP driver in romstage to check the FSP version, but since the image size is also present in the header we can also implement and use this function to check if it fits into the reserved region. Since the FSP-M memory region is located after romstage loading it won't clobber the romstage code where we do the check. BUG=b:186149011 TEST=Mandolin still boots fine with the patch applied. When as a test the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000 which is by far not enough for the decompressed FSP-M binary to fit into it prints the newly added error message on the console and then stops. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 --- M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/fsp_validate.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/57068/1 diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc index 8a5cef5..f1a78fb 100644 --- a/src/soc/amd/common/fsp/Makefile.inc +++ b/src/soc/amd/common/fsp/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += fsp_reset.c +romstage-y += fsp_validate.c ramstage-y += fsp_reset.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_DMI_TABLES) += dmi.c diff --git a/src/soc/amd/common/fsp/fsp_validate.c b/src/soc/amd/common/fsp/fsp_validate.c new file mode 100644 index 0000000..1a4f9b3 --- /dev/null +++ b/src/soc/amd/common/fsp/fsp_validate.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <fsp/util.h> +#include <types.h> + +/* Validate the FSP-M header in romstage */ +void soc_validate_fsp_version(const struct fsp_header *hdr) +{ + /* TODO: Add FSP version number check to see if the UPD interface is compatible. */ + + if (hdr->image_size > CONFIG_FSP_M_SIZE) + die("The FSP-M binary is larger than the memory region allocated for it! " + "Increase FSP_M_SIZE for it to fit into its memory region.\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/57068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Gerrit-Change-Number: 57068 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]amdfwtool: Use relative address for EFS gen2
by Eric Peers (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Bao Zheng, Martin Roth, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao, Karthikeyan Ramasubramanian, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56438 ) Change subject: [WIP]amdfwtool: Use relative address for EFS gen2 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56438/comment/b408b451_b7963e28 PS2, Line 9: The second generation EFS (offset 0x24[0]=0) uses : "binary relative" offsets and not "x86 physical : MMIO address" like gen1. : : Chips like Cezanne can run in both cases, so no problem : comes up so far. : : TODO: Need to fix the problem in psp_verstage. > Please re-flow for 75 characters per line. if this breaks psp_verstage, why are you putting it up for review? https://review.coreboot.org/c/coreboot/+/56438/comment/d306e6dc_09089faa PS2, Line 19: Test=Majolica (Cezanne) need to test on guybrush as well since Majolica doesn't have the TPM that guybrush does. -- To view, visit https://review.coreboot.org/c/coreboot/+/56438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Gerrit-Change-Number: 56438 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 20 Aug 2021 22:07:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add TGL-H PEG ports
by build bot (Jenkins) (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Jeremy Soller, Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56949 ) Change subject: soc/intel/tigerlake: Add TGL-H PEG ports ...................................................................... Patch Set 2: (4 comments) File src/soc/intel/tigerlake/romstage/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126485): https://review.coreboot.org/c/coreboot/+/56949/comment/f4b25ef9_0662ec70 PS2, Line 195: if (is_devfn_enabled(SA_DEVFN_CPU_PCIE)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126485): https://review.coreboot.org/c/coreboot/+/56949/comment/a19ddc3f_0b2c7f2f PS2, Line 198: if (is_devfn_enabled(SA_DEVFN_PEG1)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126485): https://review.coreboot.org/c/coreboot/+/56949/comment/3e45c14a_d0b7e130 PS2, Line 201: if (is_devfn_enabled(SA_DEVFN_PEG2)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126485): https://review.coreboot.org/c/coreboot/+/56949/comment/493764ef_bb2c20db PS2, Line 204: if (is_devfn_enabled(SA_DEVFN_PEG3)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/56949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e Gerrit-Change-Number: 56949 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 20 Aug 2021 21:54:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add USB ACPI devices for PCH-H
by Tim Crawford (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56953 ) Change subject: soc/intel/tigerlake: Add USB ACPI devices for PCH-H ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1c1c3d172366ddcc8c194cb2e0b0c2fb2acf678 Gerrit-Change-Number: 56953 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 21:45:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2021