coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
by Tim Wawrzynczak (Code Review) 05 May '21

05 May '21

Attention is currently required from: Furquan Shaikh, Kane Chen, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52874 ) Change subject: soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT ...................................................................... Patch Set 6: Code-Review+2 (3 comments) File src/soc/intel/alderlake/pmc.c: https://review.coreboot.org/c/coreboot/+/52874/comment/78dbe3f9_dd996996 PS6, Line 147: /* : * Enable Power button SMI only after BS_DEV_INIT_CHIPS (FSP-S) is done. : */ nit: can be a one-line comment File src/soc/intel/jasperlake/pmc.c: https://review.coreboot.org/c/coreboot/+/52874/comment/8ec4a95c_5ee54a5f PS6, Line 98: /* : * Enable Power button SMI only after BS_DEV_INIT_CHIPS (FSP-S) is done. : */ same File src/soc/intel/tigerlake/pmc.c: https://review.coreboot.org/c/coreboot/+/52874/comment/dc901d7d_64b5b418 PS6, Line 151: /* : * Enable Power button SMI only after BS_DEV_INIT_CHIPS (FSP-S) is done. : */ same -- To view, visit https://review.coreboot.org/c/coreboot/+/52874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Gerrit-Change-Number: 52874 Gerrit-PatchSet: 6 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 05 May 2021 21:01:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards
by Aseda Aboagye (Code Review) 05 May '21

05 May '21

Attention is currently required from: Andrey Pronin, Aaron Durbin. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52920 ) Change subject: mb/google/dedede: Select TPM20_CREATE_FWMP for discrete TPM boards ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/52920/comment/76599c64_33155b5c PS1, Line 167: select TPM20_CREATE_FWMP > Doesn't this selection need to be under another config? Basically move this to line 41 or 42. […] Ah, thanks for the correction. That might explain why it didn't seem like my changes were being built. (still a Kconfig noob) && I believe Andrey would prefer to have this as a config option for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/52920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c49f2018baa17df8c932b7a7d7f1aec28749ff2 Gerrit-Change-Number: 52920 Gerrit-PatchSet: 5 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 05 May 2021 20:53:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Switch eSPI ALERT# to in-band
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Attention is currently required from: Raul Rangel. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52956 ) Change subject: mb/google/mancomb: Switch eSPI ALERT# to in-band ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929 Gerrit-Change-Number: 52956 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Diana Zigterman <dzigterman(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 05 May 2021 20:52:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Switch eSPI ALERT# to in-band
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Attention is currently required from: Raul Rangel. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52955 ) Change subject: mb/google/guybrush: Switch eSPI ALERT# to in-band ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Gerrit-Change-Number: 52955 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 05 May 2021 20:52:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/espi,mb/: Allow configuring open drain ALERT#
by Karthik Ramasubramanian (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52954 ) Change subject: soc/amd/common/espi,mb/: Allow configuring open drain ALERT# ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Overall looks good to me. I dont see any takers of open drain yet. So that code path probably might not get exercised for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/52954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Gerrit-Change-Number: 52954 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 20:50:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52957 ) Change subject: soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing ...................................................................... soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing PCI interrupts are level active low, so they can be shared. BUG=b:184766519 TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic` Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I439337dd66fe56790406c6d603e73512c806a19d --- M src/soc/amd/common/acpi/pci_int.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/52957/1 diff --git a/src/soc/amd/common/acpi/pci_int.asl b/src/soc/amd/common/acpi/pci_int.asl index 06ba0cc..306995d 100644 --- a/src/soc/amd/common/acpi/pci_int.asl +++ b/src/soc/amd/common/acpi/pci_int.asl @@ -2,14 +2,14 @@ /* PIC Possible Resource Values */ Name(IRQP, ResourceTemplate() { - Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , PIC){ + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , PIC){ 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15 } }) /* IO-APIC Possible Resource Values */ Name(IRQI, ResourceTemplate() { - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , APIC) { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , APIC) { 16, 17, 18, 19, 20, 21, 22, 23 } }) @@ -63,7 +63,7 @@ ResourceConsumer, \ Level, \ ActiveLow, \ - Exclusive, , , NUMB) \ + Shared, , , NUMB) \ { 0 } \ } \ CreateDWordField(local0, NUMB._INT, IRQN) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/52957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I439337dd66fe56790406c6d603e73512c806a19d Gerrit-Change-Number: 52957 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52917 to look at the new patch set (#2). Change subject: soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT ...................................................................... soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT This will use the FSP PCI routing HOB to generate the PCI _PRT table. This is loosely based off of picasso/pcie_gpp.c. We can eventually migrate picasso over to this code. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/acpi_prt.c 3 files changed, 202 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52917/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52911 ) Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/fsp/pci/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52911/comment/0dc5d718_eed266aa PS1, Line 3: ramstage-y > ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_PCI) += pci_routing_info. […] I have it in line 1. I did it this way since this whole folder should be guarded by the config. File src/soc/amd/common/fsp/pci/pci_routing_info.c: https://review.coreboot.org/c/coreboot/+/52911/comment/1179ed60_5f7cedd8 PS1, Line 29: routing_table > i'd also strongly recommend that, since the search for the hob is rather expensive in terms of time Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 05 May 2021 20:35:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Raul Rangel (Code Review) 05 May '21

05 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52911 to look at the new patch set (#2). Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 --- A src/soc/amd/common/fsp/pci/Kconfig A src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/pci_routing_info.c A src/soc/amd/common/fsp/pci/pci_routing_info.h 4 files changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/52911/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Populate PIC IRQ data
by Raul Rangel (Code Review) 05 May '21

05 May '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52915 to look at the new patch set (#2). Change subject: mb/google/guybrush: Populate PIC IRQ data ...................................................................... mb/google/guybrush: Populate PIC IRQ data The PIC IRQs are required so we can correctly setup the PCI_INT registers. This only matters when booting in PIC mode. We don't need to set the IO-APIC registers since the linux kernel will auto-assign those to reduce conflicts. BUG=b:184766519 TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and verify xhci and graphics continue to work. $ cat /proc/interrupts 12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci 13: 100000 XT-PIC xhci-hcd:usb1 14: 4032 XT-PIC amdgpu, xhci-hcd:usb3 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f --- M src/mainboard/google/guybrush/mainboard.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/52915/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Gerrit-Change-Number: 52915 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021