coreboot-gerrit April 2021

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Change in coreboot[master]: nb/intel/nehalem: Introduce macros to reduce indentation level
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36083 ) Change subject: nb/intel/nehalem: Introduce macros to reduce indentation level ...................................................................... nb/intel/nehalem: Introduce macros to reduce indentation level While the indentation of the code is adapted to the new macro's the wrapping is not fixed. A followup commit running this code through clang-format will do that. TEST: build with BUILD_TIMELESS=1, hash of resulting binary is identical before and after. Change-Id: I95358d49b57e771d86a562702403f491a02fe017 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 527 insertions(+), 491 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/36083/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b9d407a..dde51f9 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -50,22 +50,57 @@ #define HECIDEV PCI_DEV(0, 0x16, 0) #define HECIBAR 0x10 -#define FOR_ALL_RANKS \ - for (channel = 0; channel < NUM_CHANNELS; channel++) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ - for (rank = 0; rank < NUM_RANKS; rank++) +#define RANK_IS_POPULATED(info, channel, slot, rank) \ + ((info)->populated_ranks[(channel)][(slot)][(rank)] != 0) -#define FOR_POPULATED_RANKS \ - for (channel = 0; channel < NUM_CHANNELS; channel++) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ - for (rank = 0; rank < NUM_RANKS; rank++) \ - if (info->populated_ranks[channel][slot][rank]) +#define IF_RANK_POPULATED(info, channel, slot, rank) \ + if (RANK_IS_POPULATED(info, channel, slot, rank)) -#define FOR_POPULATED_RANKS_BACKWARDS \ - for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ - for (rank = 0; rank < NUM_RANKS; rank++) \ - if (info->populated_ranks[channel][slot][rank]) +#define FOR_EACH_CHANNEL(channel) \ + for (channel = 0; channel < NUM_CHANNELS; channel++) + +#define FOR_EACH_SLOT(slot) \ + for (slot = 0; slot < NUM_SLOTS; slot++) + +#define FOR_ALL_SLOTS(channel, slot) \ + FOR_EACH_CHANNEL(channel) \ + FOR_EACH_SLOT(slot) + +#define FOR_ALL_POPULATED_SLOTS(info, channel, slot) \ + FOR_ALL_SLOTS(channel, slot) \ + IF_RANK_POPULATED(info, channel, slot, 0) + +#define FOR_EACH_RANK(rank) \ + for (rank = 0; rank < NUM_RANKS; rank++) + +#define FOR_ALL_RANKS(channel, slot, rank) \ + FOR_ALL_SLOTS(channel, slot) \ + FOR_EACH_RANK(rank) + +#define FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \ + FOR_EACH_SLOT(slot) \ + FOR_EACH_RANK(rank) + +#define FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) \ + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \ + IF_RANK_POPULATED(info, channel, slot, rank) + +#define FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) \ + FOR_ALL_RANKS(channel, slot, rank) \ + IF_RANK_POPULATED(info, channel, slot, rank) + +#define FOR_EACH_CHANNEL_BACKWARDS(channel) \ + for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) + +#define FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) \ + FOR_EACH_CHANNEL_BACKWARDS(channel) \ + FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) + +#define FOR_EACH_LANE(lane) \ + for (lane = 0; lane < 8; lane++) + +#define FOR_EACH_LANE_WITH_ECC(lane) \ + for (lane = 0; lane < 9; lane++) /* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */ typedef struct { @@ -315,7 +350,7 @@ program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank) { int lane; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { write_500(info, channel, base + info->training. @@ -363,7 +398,7 @@ int i, lane; for (i = 0; i < 2; i++) - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { write_500(info, channel, info->training.lane_timings[i + 1][channel][slot] @@ -372,24 +407,22 @@ slot, rank), 9, 0); + } write_1d0(1, 0x103, 6, 1); - for (lane = 0; lane < 8; lane++) - write_500(info, channel, - info->training. - lane_timings[0][channel][slot][rank][lane], + FOR_EACH_LANE(lane) { + write_500(info, channel, info->training.lane_timings[0][channel][slot] + [rank][lane], get_timing_register_addr(lane, 0, slot, rank), 9, 0); + } for (i = 0; i < 2; i++) { - for (lane = 0; lane < 8; lane++) - write_500(info, channel, - info->training.lane_timings[i + - 1][channel][slot] - [rank][lane], get_timing_register_addr(lane, - i + 1, - slot, - rank), + FOR_EACH_LANE(lane) { + write_500(info, channel, info->training.lane_timings[i + 1][channel] + [slot] [rank][lane], + get_timing_register_addr(lane, i + 1, slot, rank), 9, 0); + } gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); } @@ -397,7 +430,7 @@ MCHBAR8(0x5ff) = 0x0; MCHBAR8(0x5ff) = 0x80; write_1d0(0x2, 0x142, 3, 1); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); info->training.lane_timings[2][channel][slot][rank][lane] = read_500(info, channel, @@ -413,9 +446,10 @@ { int slot, rank; int res = 0; - for (slot = 0; slot < NUM_SLOTS; slot++) + FOR_EACH_SLOT(slot) { for (rank = 0; rank < NUM_SLOTS; rank++) res += info->populated_ranks[channel][slot][rank]; + } return res; } @@ -465,7 +499,7 @@ const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b }; u32 vd8[2][16]; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { for (j = 0; j < 4; j++) { u32 a = (j == 1) ? 0x29292929 : 0x31313131; u32 lmask = (j == 3) ? 0xffff : 0xffffffff; @@ -559,41 +593,25 @@ /* Find common CAS latency */ supported_cas_latencies = 0x3fe; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - if (info->populated_ranks[channel][slot][0]) - supported_cas_latencies &= - 2 * - (info-> - spd[channel][slot][CAS_LATENCIES_LSB] | - (info-> - spd[channel][slot][CAS_LATENCIES_MSB] << - 8)); + FOR_ALL_POPULATED_SLOTS(info, channel, slot) { + supported_cas_latencies &= 2 * (info->spd[channel][slot][CAS_LATENCIES_LSB] + | (info->spd[channel][slot][CAS_LATENCIES_MSB] + << 8)); + } max_clock_index = min(3, info->max_supported_clock_speed_index); cycletime = min_cycletime[max_clock_index]; cas_latency_time = min_cas_latency_time[max_clock_index]; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - if (info->populated_ranks[channel][slot][0]) { - unsigned timebase; - timebase = - 1000 * - info-> - spd[channel][slot][TIMEBASE_DIVIDEND] / - info->spd[channel][slot][TIMEBASE_DIVISOR]; - cycletime = - max(cycletime, - timebase * - info->spd[channel][slot][CYCLETIME]); - cas_latency_time = - max(cas_latency_time, - timebase * - info-> - spd[channel][slot][CAS_LATENCY_TIME]); - } + FOR_ALL_POPULATED_SLOTS(info, channel, slot) { + unsigned timebase; + timebase = 1000 * info->spd[channel][slot][TIMEBASE_DIVIDEND] / + info->spd[channel][slot][TIMEBASE_DIVISOR]; + cycletime = max(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); + cas_latency_time = max(cas_latency_time, timebase * + info->spd[channel][slot][CAS_LATENCY_TIME]); + } if (cycletime > min_cycletime[0]) die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!"); for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { @@ -633,128 +651,125 @@ extended_silicon_revision = info->silicon_revision; if (info->silicon_revision == 0) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) + FOR_ALL_SLOTS(channel, slot) { + if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3) + extended_silicon_revision = 4; + } + + FOR_EACH_CHANNEL(channel) { + FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) { + int card_timing_2; + if (!info->populated_ranks[channel][slot][rank]) + continue; + + FOR_EACH_LANE_WITH_ECC(lane) { + int tm_reg; + int card_timing; + + card_timing = 0; if ((info-> - spd[channel][slot][MODULE_TYPE] & 0xF) == - 3) - extended_silicon_revision = 4; - - for (channel = 0; channel < NUM_CHANNELS; channel++) { - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_SLOTS; rank++) { - int card_timing_2; - if (!info->populated_ranks[channel][slot][rank]) - continue; - - for (lane = 0; lane < 9; lane++) { - int tm_reg; - int card_timing; - - card_timing = 0; - if ((info-> - spd[channel][slot][MODULE_TYPE] & - 0xF) == 3) { - int reference_card; - reference_card = - info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & - 0x1f; - if (reference_card == 3) - card_timing = - u16_ffd1188[0][lane] - [info-> - clock_speed_index]; - if (reference_card == 5) - card_timing = - u16_ffd1188[1][lane] - [info-> - clock_speed_index]; - } - - info->training. - lane_timings[0][channel][slot][rank] - [lane] = - u8_FFFD1218[info-> - clock_speed_index]; - info->training. - lane_timings[1][channel][slot][rank] - [lane] = 256; - - for (tm_reg = 2; tm_reg < 4; tm_reg++) - info->training. - lane_timings[tm_reg] - [channel][slot][rank][lane] - = - u8_FFFD1240[channel] - [extended_silicon_revision] - [lane][2 * slot + - rank][info-> - clock_speed_index] - + info->max4048[channel] - + - u8_FFFD0C78[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][slot] - [rank][info-> - clock_speed_index] - + card_timing; - for (tm_reg = 0; tm_reg < 4; tm_reg++) - write_500(info, channel, - info->training. - lane_timings[tm_reg] - [channel][slot][rank] - [lane], - get_timing_register_addr - (lane, tm_reg, slot, - rank), 9, 0); + spd[channel][slot][MODULE_TYPE] & + 0xF) == 3) { + int reference_card; + reference_card = + info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1f; + if (reference_card == 3) + card_timing = + u16_ffd1188[0][lane] + [info-> + clock_speed_index]; + if (reference_card == 5) + card_timing = + u16_ffd1188[1][lane] + [info-> + clock_speed_index]; } - card_timing_2 = 0; - if (!(extended_silicon_revision != 4 - || (info-> - populated_ranks_mask[channel] & 5) == - 5)) { - if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & 0x1F) - == 3) - card_timing_2 = - u16_FFFE0EB8[0][info-> - clock_speed_index]; - if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & 0x1F) - == 5) - card_timing_2 = - u16_FFFE0EB8[1][info-> - clock_speed_index]; - } + info->training. + lane_timings[0][channel][slot][rank] + [lane] = + u8_FFFD1218[info-> + clock_speed_index]; + info->training. + lane_timings[1][channel][slot][rank] + [lane] = 256; - for (i = 0; i < 3; i++) + for (tm_reg = 2; tm_reg < 4; tm_reg++) + info->training. + lane_timings[tm_reg] + [channel][slot][rank][lane] + = + u8_FFFD1240[channel] + [extended_silicon_revision] + [lane][2 * slot + + rank][info-> + clock_speed_index] + + info->max4048[channel] + + + u8_FFFD0C78[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][slot] + [rank][info-> + clock_speed_index] + + card_timing; + for (tm_reg = 0; tm_reg < 4; tm_reg++) write_500(info, channel, - (card_timing_2 + - info->max4048[channel] - + - u8_FFFD0EF8[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][info-> - clock_speed_index]), - u16_fffd0c50[i][slot][rank], - 8, 1); - write_500(info, channel, - (info->max4048[channel] + - u8_FFFD0C78[channel] - [extended_silicon_revision][info-> - mode4030 - [channel]] - [slot][rank][info-> - clock_speed_index]), - u16_fffd0c70[slot][rank], 7, 1); + info->training. + lane_timings[tm_reg] + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, tm_reg, slot, + rank), 9, 0); } + + card_timing_2 = 0; + if (!(extended_silicon_revision != 4 + || (info-> + populated_ranks_mask[channel] & 5) == + 5)) { + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 3) + card_timing_2 = + u16_FFFE0EB8[0][info-> + clock_speed_index]; + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 5) + card_timing_2 = + u16_FFFE0EB8[1][info-> + clock_speed_index]; + } + + for (i = 0; i < 3; i++) + write_500(info, channel, + (card_timing_2 + + info->max4048[channel] + + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> + clock_speed_index]), + u16_fffd0c50[i][slot][rank], + 8, 1); + write_500(info, channel, + (info->max4048[channel] + + u8_FFFD0C78[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]] + [slot][rank][info-> + clock_speed_index]), + u16_fffd0c70[slot][rank], 7, 1); + } if (!info->populated_ranks_mask[channel]) continue; for (i = 0; i < 3; i++) @@ -828,12 +843,12 @@ some_delay_3_ps_rounded = 0; extended_silicon_revision = info->silicon_revision; if (!info->silicon_revision) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - if ((info-> - spd[channel][slot][MODULE_TYPE] & 0xF) == - 3) - extended_silicon_revision = 4; + FOR_ALL_SLOTS(channel, slot) { + if ((info-> + spd[channel][slot][MODULE_TYPE] & 0xF) == + 3) + extended_silicon_revision = 4; + } if (info->board_lane_delay[7] < 5) info->board_lane_delay[7] = 5; info->revision_flag_1 = 2; @@ -914,7 +929,7 @@ || (count_ranks_in_channel(info, 1) == 2)) ? 2 : 3; } - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { int max_of_unk; int min_of_unk_2; @@ -945,67 +960,66 @@ [i]; else unk1 = 0; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) { - int a = 0; - int b = 0; + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + int a = 0; + int b = 0; - if (!info-> - populated_ranks[channel][slot] - [rank]) - continue; - if (extended_silicon_revision == 4 - && (info-> - populated_ranks_mask[channel] & - 5) != 5) { + if (!info-> + populated_ranks[channel][slot] + [rank]) + continue; + if (extended_silicon_revision == 4 + && (info-> + populated_ranks_mask[channel] & + 5) != 5) { + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1F) == 3) { + a = u16_ffd1178[0] + [info-> + clock_speed_index]; + b = u16_fe0eb8[0][info-> + clock_speed_index]; + } else if ((info-> spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & - 0x1F) == 3) { - a = u16_ffd1178[0] - [info-> - clock_speed_index]; - b = u16_fe0eb8[0][info-> - clock_speed_index]; - } else - if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] - & 0x1F) == 5) { + [REFERENCE_RAW_CARD_USED] + & 0x1F) == 5) { a = u16_ffd1178[1] - [info-> - clock_speed_index]; + [info-> + clock_speed_index]; b = u16_fe0eb8[1][info-> clock_speed_index]; } - } - min_of_unk_2 = min(min_of_unk_2, a); - min_of_unk_2 = min(min_of_unk_2, b); - if (rank == 0) { - sum += a; - count++; - } - { - int t; - t = b + - u8_FFFD0EF8[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][info-> - clock_speed_index]; - if (unk1 >= t) - max_of_unk = - max(max_of_unk, - unk1 - t); - } } + min_of_unk_2 = min(min_of_unk_2, a); + min_of_unk_2 = min(min_of_unk_2, b); + if (rank == 0) { + sum += a; + count++; + } + { + int t; + t = b + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> + clock_speed_index]; + if (unk1 >= t) + max_of_unk = + max(max_of_unk, + unk1 - t); + } + } { int t = - u8_FFFD17E0[channel] - [extended_silicon_revision][info-> - mode4030 - [channel]] - [info->clock_speed_index] + min_of_unk_2; + u8_FFFD17E0[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]] + [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) max_of_unk = max(max_of_unk, unk1 - t); } @@ -1080,7 +1094,7 @@ } else { write_recovery = 6; } - FOR_POPULATED_RANKS { + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { auto_self_refresh &= (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1; self_refresh_temperature &= @@ -1097,7 +1111,7 @@ total_rank = 0; - for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) { + FOR_EACH_CHANNEL_BACKWARDS(channel) { int rtt, rtt_wr = MR2_RTT_WR_DISABLED; int rzq_reg58e; @@ -1126,31 +1140,31 @@ MCHBAR16(0x58e + (channel << 10)) = rzq_reg58e | 0x82; MCHBAR16(0x590 + (channel << 10)) = 0x1282; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info->populated_ranks[channel][slot][rank]) { - jedec_read(info, channel, slot, rank, - total_rank, 0x28, - rtt_wr | (info-> - clock_speed_index - << 3) - | (auto_self_refresh << 6) | - (self_refresh_temperature << - 7)); - jedec_read(info, channel, slot, rank, - total_rank, 0x38, 0); - jedec_read(info, channel, slot, rank, - total_rank, 0x18, - rtt | MR1_ODS34OHM); - jedec_read(info, channel, slot, rank, - total_rank, 6, - (dll_on << 12) | - (write_recovery << 9) - | ((info->cas_latency - 4) << - 4) | MR0_BT_INTERLEAVED | - MR0_DLL_RESET_ON); - total_rank++; - } + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info->populated_ranks[channel][slot][rank]) { + jedec_read(info, channel, slot, rank, + total_rank, 0x28, + rtt_wr | (info-> + clock_speed_index + << 3) + | (auto_self_refresh << 6) | + (self_refresh_temperature << + 7)); + jedec_read(info, channel, slot, rank, + total_rank, 0x38, 0); + jedec_read(info, channel, slot, rank, + total_rank, 0x18, + rtt | MR1_ODS34OHM); + jedec_read(info, channel, slot, rank, + total_rank, 6, + (dll_on << 12) | + (write_recovery << 9) + | ((info->cas_latency - 4) << + 4) | MR0_BT_INTERLEAVED | + MR0_DLL_RESET_ON); + total_rank++; + } + } } } @@ -1160,7 +1174,7 @@ unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ unsigned int channel_0_non_interleaved; - FOR_ALL_RANKS { + FOR_ALL_RANKS(channel, slot, rank) { if (info->populated_ranks[channel][slot][rank]) { total_mb[channel] += pre_jedec ? 256 : (256 << info-> @@ -1257,7 +1271,7 @@ } if (MCHBAR8(0x2ca9) & 1) some_delay_3_half_cycles = 3; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32_OR(0x220 + (channel << 10), 0x18001117); MCHBAR32(0x224 + (channel << 10)) = (info->max_slots_used_in_channel - 1) | @@ -1314,7 +1328,7 @@ cas_latency_derived = info->cas_latency - info->clock_speed_index + 2; if (info->clock_speed_index > 1) cas_latency_derived++; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x240 + (channel << 10)) = ((info->clock_speed_index == 0) * 0x11000) | 0x1002100 | ((2 + info->clock_speed_index) << 4) | @@ -1518,13 +1532,14 @@ if (capid0[2] & 2) { info->silicon_revision = 0; info->max_supported_clock_speed_index = 2; - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { if (info->populated_ranks[channel][0][0] && (info->spd[channel][0][MODULE_TYPE] & 0xf) == 3) { info->silicon_revision = 2; info->max_supported_clock_speed_index = 1; } + } } else { switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1)) { case 1: @@ -1556,19 +1571,19 @@ return; for (tm = 0; tm < 4; tm++) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) - write_500(info, channel, - info-> - cached_training-> - lane_timings[tm] - [channel][slot][rank] - [lane], - get_timing_register_addr - (lane, tm, slot, - rank), 9, 0); + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + write_500(info, channel, + info-> + cached_training-> + lane_timings[tm] + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, tm, slot, + rank), 9, 0); + } + } write_1d0(info->cached_training->reg_178, 0x178, 7, 1); write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); } @@ -1577,10 +1592,10 @@ { int channel, slot, rank, lane, i; printk(RAM_DEBUG, "Timings:\n"); - FOR_POPULATED_RANKS { + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank); - for (lane = 0; lane < 9; lane++) { + FOR_EACH_LANE_WITH_ECC(lane) { printk(RAM_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { printk(RAM_DEBUG, "%x (%x) ", @@ -1610,16 +1625,19 @@ int channel, slot, rank, lane, i; train = info->training; - FOR_POPULATED_RANKS for (lane = 0; lane < 9; lane++) - for (i = 0; i < 4; i++) - train.lane_timings[i][channel][slot][rank][lane] = - read_500(info, channel, - get_timing_register_addr(lane, i, slot, - rank), 9); + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + for (i = 0; i < 4; i++) + train.lane_timings[i][channel][slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr(lane, i, slot, + rank), 9); + } + } train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { u32 reg32; reg32 = MCHBAR32((channel << 10) + 0x274); train.reg274265[channel][0] = reg32 >> 16; @@ -1912,27 +1930,28 @@ { int i, channel, slot, rank, lane; for (i = 0; i < 2; i++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) - info->training. - lane_timings[0][i][slot][rank][lane] - = 32; + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + info->training. + lane_timings[0][i][slot][rank][lane] + = 32; + } + } - for (i = 1; i < 4; i++) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) { - info->training. - lane_timings[i][channel] - [slot][rank][lane] = - read_500(info, channel, - get_timing_register_addr - (lane, i, slot, - rank), 9) - + (i == 1) * 11; // !!!! - } + for (i = 1; i < 4; i++) { + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + info->training. + lane_timings[i][channel] + [slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr + (lane, i, slot, + rank), 9) + + (i == 1) * 11; // !!!! + } + } + } } @@ -2186,7 +2205,7 @@ { int lane; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { int is_fail = (fail_mask >> lane) & 1; switch (state[lane]) { case BEFORE_USABLE: @@ -2250,7 +2269,7 @@ if (!first_run) { int is_all_ok = 1; - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (timings[reg_178][channel][slot][rank][lane]. smallest == timings[reg_178][channel][slot][rank][lane]. @@ -2261,6 +2280,7 @@ largest = 0; is_all_ok = 0; } + } if (is_all_ok) { for (i = 0; i < 8; i++) state[i] = COMPLETE; @@ -2280,7 +2300,7 @@ if (reg1b3) { write_1d0(0, 0x1b3, 6, 1); write_1d0(0, 0x1a3, 6, 1); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { if (state[lane] == COMPLETE) { timings[reg_178][channel][slot][rank][lane]. smallest = @@ -2299,7 +2319,7 @@ } if (!first_run) { - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (state[lane] == COMPLETE) { write_500(info, channel, timings[reg_178][channel][slot][rank] @@ -2324,7 +2344,7 @@ num_successfully_checked[lane] = 0; } else num_successfully_checked[lane] = -1; - + } do { u8 failmask = 0; for (i = 0; i < niter; i++) { @@ -2338,7 +2358,7 @@ 1); } MCHBAR32_OR(0xfb0, 0x00030000); - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { if (timings[reg_178][channel] @@ -2395,11 +2415,12 @@ num_successfully_checked[lane] ++; } + } } while (!check_bounded(num_successfully_checked, 2)) ; - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (state[lane] == COMPLETE) { write_500(info, channel, timings[reg_178][channel][slot][rank] @@ -2424,6 +2445,7 @@ num_successfully_checked[lane] = 0; } else num_successfully_checked[lane] = -1; + } do { int failmask = 0; @@ -2439,7 +2461,7 @@ } MCHBAR32_OR(0xfb0, 0x00030000); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { if (timings[reg_178][channel] @@ -2502,7 +2524,7 @@ while (!check_bounded(num_successfully_checked, 3)) ; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { write_500(info, channel, info->training. lane_timings[0][channel][slot][rank][lane], @@ -2537,28 +2559,30 @@ write_1d0(val, 0x10b, 6, 1); - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 9; lane++) { - u16 reg_500; - reg_500 = read_500(info, channel, - get_timing_register_addr(lane, 0, slot, - rank), 9); - if (val == 1) { - if (lut16[info->clock_speed_index] <= reg_500) - reg_500 -= lut16[info->clock_speed_index]; - else - reg_500 = 0; - } else { - reg_500 += lut16[info->clock_speed_index]; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + u16 reg_500; + reg_500 = read_500(info, channel, + get_timing_register_addr(lane, 0, slot, + rank), 9); + if (val == 1) { + if (lut16[info->clock_speed_index] <= reg_500) + reg_500 -= lut16[info->clock_speed_index]; + else + reg_500 = 0; + } else { + reg_500 += lut16[info->clock_speed_index]; + } + write_500(info, channel, reg_500, + get_timing_register_addr(lane, 0, slot, rank), 9, 1); } - write_500(info, channel, reg_500, - get_timing_register_addr(lane, 0, slot, rank), 9, 1); } } static void set_ecc(int onoff) { int channel; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { u8 t; t = MCHBAR8((channel << 10) + 0x5f8); if (onoff) @@ -2585,12 +2609,13 @@ { int lane; - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { write_500(info, channel, info->training. lane_timings[type][channel][slot][rank][lane], get_timing_register_addr(lane, type, slot, rank), 9, 0); + } } static void @@ -2610,11 +2635,12 @@ memset(count, 0, sizeof(count)); - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { write_500(info, channel, info->training. lane_timings[2][channel][slot][rank][lane] + 32, get_timing_register_addr(lane, 3, slot, rank), 9, 1); + } for (timing_offset = 0; !validate_state(state) && timing_offset < 64; timing_offset++) { @@ -2634,7 +2660,7 @@ if (!validate_state(state)) die("Couldn't discover DRAM timings (1)\n"); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { u8 bias = 0; if (info->silicon_revision) { @@ -2758,13 +2784,15 @@ reg178 < reg178_max[info->clock_speed_index]; reg178 += reg178_step[info->clock_speed_index]) { margin[reg178] = -1; - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { - int curmargin = - timings[reg178][channel][slot][rank][lane].largest - - timings[reg178][channel][slot][rank][lane]. - smallest + 1; - if (curmargin < margin[reg178]) - margin[reg178] = curmargin; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE(lane) { + int curmargin = + timings[reg178][channel][slot][rank][lane].largest - + timings[reg178][channel][slot][rank][lane]. + smallest + 1; + if (curmargin < margin[reg178]) + margin[reg178] = curmargin; + } } if (margin[reg178] >= STANDARD_MIN_MARGIN) { u16 weight; @@ -2816,29 +2844,28 @@ if (!info->cached_training) return 0; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 8 + info->use_ecc; lane++) { - u16 cached_value, estimation_value; - cached_value = - info->cached_training-> - lane_timings[1][channel][slot][rank] - [lane]; - if (cached_value >= 0x18 - && cached_value <= 0x1E7) { - estimation_value = - info->training. - lane_timings[1][channel] - [slot][rank][lane]; - if (estimation_value < - cached_value - 24) - return 0; - if (estimation_value > - cached_value + 24) - return 0; - } - } + FOR_ALL_RANKS(channel, slot, rank) { + for (lane = 0; lane < 8 + info->use_ecc; lane++) { + u16 cached_value, estimation_value; + cached_value = + info->cached_training-> + lane_timings[1][channel][slot][rank] + [lane]; + if (cached_value >= 0x18 + && cached_value <= 0x1E7) { + estimation_value = + info->training. + lane_timings[1][channel] + [slot][rank][lane]; + if (estimation_value < + cached_value - 24) + return 0; + if (estimation_value > + cached_value + 24) + return 0; + } + } + } return 1; } @@ -2885,9 +2912,9 @@ it still works whereas with j == 1 we check that just outside of bound we fail. */ - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { for (i = 0; i < 2; i++) { - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { write_500(info, channel, info->cached_training-> timing2_bounds[channel][slot] @@ -2982,7 +3009,7 @@ return 1; fail: - FOR_POPULATED_RANKS { + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { write_500_timings_type(info, channel, slot, rank, 1); write_500_timings_type(info, channel, slot, rank, 2); write_500_timings_type(info, channel, slot, rank, 3); @@ -3026,7 +3053,7 @@ } set_ecc(0); - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { int i; write_500_timings_type(info, channel, slot, rank, 0); @@ -3051,9 +3078,8 @@ reg_178 += reg178_step[info->clock_speed_index]) { totalrank = 0; set_178(reg_178); - for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) { + FOR_EACH_CHANNEL_BACKWARDS(channel) { + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { memset(&timings[reg_178][channel][slot] [rank][0].smallest, 0, 16); if (info-> @@ -3067,34 +3093,37 @@ timings); totalrank++; } - } + } + } } reg178_center = choose_reg178(info, timings); - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { - info->training.timing_bounds[0][channel][slot][rank][lane]. - smallest = - timings[info->training. - reg178_smallest][channel][slot][rank][lane]. - smallest; - info->training.timing_bounds[0][channel][slot][rank][lane]. - largest = - timings[info->training. - reg178_smallest][channel][slot][rank][lane].largest; - info->training.timing_bounds[1][channel][slot][rank][lane]. - smallest = - timings[info->training. - reg178_largest][channel][slot][rank][lane].smallest; - info->training.timing_bounds[1][channel][slot][rank][lane]. - largest = - timings[info->training. - reg178_largest][channel][slot][rank][lane].largest; - info->training.timing_offset[channel][slot][rank][lane] = - info->training.lane_timings[1][channel][slot][rank][lane] - - - info->training.lane_timings[0][channel][slot][rank][lane] + - 64; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE(lane) { + info->training.timing_bounds[0][channel][slot][rank][lane]. + smallest = + timings[info->training. + reg178_smallest][channel][slot][rank][lane]. + smallest; + info->training.timing_bounds[0][channel][slot][rank][lane]. + largest = + timings[info->training. + reg178_smallest][channel][slot][rank][lane].largest; + info->training.timing_bounds[1][channel][slot][rank][lane]. + smallest = + timings[info->training. + reg178_largest][channel][slot][rank][lane].smallest; + info->training.timing_bounds[1][channel][slot][rank][lane]. + largest = + timings[info->training. + reg178_largest][channel][slot][rank][lane].largest; + info->training.timing_offset[channel][slot][rank][lane] = + info->training.lane_timings[1][channel][slot][rank][lane] + - + info->training.lane_timings[0][channel][slot][rank][lane] + + 64; + } } if (info->silicon_revision == 1 @@ -3108,19 +3137,18 @@ reg_178 <= reg178_center + 18; reg_178 += 18) { totalrank = 0; set_178(reg_178); - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) { - if (info-> - populated_ranks[1][slot][rank]) { - train_ram_at_178(info, 1, slot, - rank, - totalrank, - reg_178, 0, - niter, - timings); - totalrank++; - } + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info-> + populated_ranks[1][slot][rank]) { + train_ram_at_178(info, 1, slot, + rank, + totalrank, + reg_178, 0, + niter, + timings); + totalrank++; } + } } ranks_after_channel1 = totalrank; @@ -3128,18 +3156,18 @@ reg_178 <= reg178_center + 12; reg_178 += 12) { totalrank = ranks_after_channel1; set_178(reg_178); - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info-> - populated_ranks[0][slot][rank]) { - train_ram_at_178(info, 0, slot, - rank, - totalrank, - reg_178, 0, - niter, - timings); - totalrank++; - } + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info-> + populated_ranks[0][slot][rank]) { + train_ram_at_178(info, 0, slot, + rank, + totalrank, + reg_178, 0, + niter, + timings); + totalrank++; + } + } } } else { @@ -3147,7 +3175,7 @@ reg_178 <= reg178_center + 12; reg_178 += 12) { totalrank = 0; set_178(reg_178); - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { train_ram_at_178(info, channel, slot, rank, totalrank, reg_178, 0, niter, timings); @@ -3157,25 +3185,27 @@ } set_178(reg178_center); - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { - u16 tm0; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE(lane) { + u16 tm0; - tm0 = - choose_training(info, channel, slot, rank, lane, timings, - reg178_center); - write_500(info, channel, tm0, - get_timing_register_addr(lane, 0, slot, rank), 9, 1); - write_500(info, channel, - tm0 + - info->training. - lane_timings[1][channel][slot][rank][lane] - - info->training. - lane_timings[0][channel][slot][rank][lane], - get_timing_register_addr(lane, 1, slot, rank), 9, 1); + tm0 = + choose_training(info, channel, slot, rank, lane, timings, + reg178_center); + write_500(info, channel, tm0, + get_timing_register_addr(lane, 0, slot, rank), 9, 1); + write_500(info, channel, + tm0 + + info->training. + lane_timings[1][channel][slot][rank][lane] - + info->training. + lane_timings[0][channel][slot][rank][lane], + get_timing_register_addr(lane, 1, slot, rank), 9, 1); + } } totalrank = 0; - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { try_timing_offsets(info, channel, slot, rank, totalrank); totalrank++; } @@ -3525,14 +3555,14 @@ if (info->revision < 8) return 256; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info->populated_ranks[channel][slot][rank]) - for (lane = 0; lane < 8 + info->use_ecc; lane++) - ret = max(ret, read_500(info, channel, - get_timing_register_addr - (lane, 0, slot, - rank), 9)); + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info->populated_ranks[channel][slot][rank]) + for (lane = 0; lane < 8 + info->use_ecc; lane++) + ret = max(ret, read_500(info, channel, + get_timing_register_addr + (lane, 0, slot, + rank), 9)); + } return ret; } @@ -3546,7 +3576,7 @@ delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); info->training.reg2ca9_bit0 = 0; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); delay_d_ps = @@ -3634,7 +3664,7 @@ { int channel; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32((channel << 10) + 0x274) = (info->cached_training->reg274265[channel][0] << 16) | info->cached_training->reg274265[channel][1]; @@ -3768,8 +3798,8 @@ memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); info.use_ecc = 1; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) { + FOR_EACH_CHANNEL(channel) { + FOR_EACH_SLOT(slot) { int v; int try; int addr; @@ -3846,16 +3876,17 @@ 0x18)) info.use_ecc = 0; } + } gav(0x55); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { int v = 0; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - v |= info. - populated_ranks[channel][slot][rank] - << (2 * slot + rank); + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + v |= info. + populated_ranks[channel][slot][rank] + << (2 * slot + rank); + } info.populated_ranks_mask[channel] = v; } @@ -4265,10 +4296,11 @@ MCHBAR32(0x160) = 0x5ffffff; MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!! MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!! - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x260 + (channel << 10)) = 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + } + FOR_EACH_CHANNEL(channel) { MCHBAR16(0x31c + (channel << 10)) = 0x101; MCHBAR16(0x360 + (channel << 10)) = 0x909; MCHBAR16(0x3a4 + (channel << 10)) = 0x101; @@ -4296,7 +4328,7 @@ populated_ranks[0] [0][0]) << 0), 0x1d1, 3, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR16(0x38e + (channel << 10)) = 0x5f5f; MCHBAR16(0x3d2 + (channel << 10)) = 0x5f5f; } @@ -4312,13 +4344,14 @@ write_1d0(0x0, 0xeb, 3, 1); write_1d0(0x0, 0xf3, 6, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (lane = 0; lane < 9; lane++) { + FOR_EACH_CHANNEL(channel) { + FOR_EACH_LANE_WITH_ECC(lane) { u16 addr = 0x125 + get_lane_offset(0, 0, lane); u8 a; a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!! write_500(&info, channel, a, addr, 6, 1); } + } udelay(1000); @@ -4333,11 +4366,9 @@ } int tm; info.training = *info.cached_training; - for (tm = 0; tm < 4; tm++) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) + for (tm = 0; tm < 4; tm++) { + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { write_500(&info, channel, info.training. @@ -4349,6 +4380,9 @@ (lane, tm, slot, rank), 9, 0); + } + } + } write_1d0(info.cached_training->reg_178, 0x178, 7, 1); write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); } @@ -4374,9 +4408,10 @@ read_1d0(0x328, 6); // = 0xfa018080 // !!!! write_1d0(7, 0x328, 6, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 8 : 0); + } read_1d0(0x116, 4); // = 0x4040432 // !!!! write_1d0(2, 0x116, 4, 1); @@ -4410,9 +4445,10 @@ 1); } - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 1); + } rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!! MCHBAR32(0x144); // !!!! @@ -4424,9 +4460,10 @@ read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!! write_1d0(4, 0x328, 6, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 0); + } MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30) | (info.populated_ranks[0][0][0] << 29); @@ -4439,15 +4476,16 @@ read_1d0(0x14b, 7); // = 0x810231b0 // !!!! write_1d0(0x35, 0x14b, 7, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 0xb : 0x2); + } set_334(1); MCHBAR8(0x1e8) = 0x4; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { write_500(&info, channel, 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2, 1); @@ -4468,27 +4506,26 @@ MCHBAR8(0x271) = 0x2; MCHBAR8(0x671) = 0x2; MCHBAR8(0x1e8) = 0x4; - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; + } MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000); MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 | ((info.populated_ranks_mask[channel] & 3) << 20)); + } if (!s3resume) jedec_init(&info); int totalrank = 0; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info.populated_ranks[channel][slot][rank]) { - jedec_read(&info, channel, slot, rank, - totalrank, 0xa, 0x400); - totalrank++; - } + FOR_ALL_POPULATED_RANKS(&info, channel, slot, rank) { + jedec_read(&info, channel, slot, rank, + totalrank, 0xa, 0x400); + totalrank++; + } MCHBAR8(0x12c) = 0x9f; @@ -4496,7 +4533,7 @@ MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! if (!s3resume) { - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; MCHBAR16(0x298 + (channel << 10)) = @@ -4523,15 +4560,14 @@ MCHBAR32(0x584) = 0xfffff; MCHBAR32(0x984) = 0xfffff; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info. - populated_ranks[channel][slot] - [rank]) - config_rank(&info, s3resume, - channel, slot, - rank); + FOR_ALL_RANKS(channel, slot, rank) { + if (info. + populated_ranks[channel][slot] + [rank]) + config_rank(&info, s3resume, + channel, slot, + rank); + } MCHBAR8(0x243) = 0x1; MCHBAR8(0x643) = 0x1; @@ -4545,7 +4581,7 @@ /* end */ if (s3resume) { - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; MCHBAR16(0x298 + (channel << 10)) = @@ -4627,7 +4663,7 @@ MCHBAR32(0x20) = 0x33001; } - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32_AND(0x220 + (channel << 10), ~0x7770); if (info.max_slots_used_in_channel == 1) MCHBAR16_OR(0x237 + (channel << 10), 0x0201); @@ -4654,7 +4690,7 @@ MCHBAR32(0x210) = (al << 16) | 0x20; } - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x288 + (channel << 10)) = 0x70605040; MCHBAR32(0x28c + (channel << 10)) = 0xfffec080; MCHBAR32(0x290 + (channel << 10)) = 0x282091c | -- To view, visit https://review.coreboot.org/c/coreboot/+/36083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95358d49b57e771d86a562702403f491a02fe017 Gerrit-Change-Number: 36083 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35821 ) Change subject: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table ...................................................................... [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table There is no explicit dependency on an option table since the reboot counter and the normal/fallback byte is at a fixed offset. I don't feel strongly about imposing this... Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35821/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 502e774..9d26692 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -255,6 +255,7 @@ bool "Always load fallback" config BOOTBLOCK_NORMAL + depends on USE_OPTION_TABLE select CONFIGURABLE_CBFS_PREFIX bool "Switch to normal if CMOS says so" -- To view, visit https://review.coreboot.org/c/coreboot/+/35821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Gerrit-Change-Number: 35821 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35823 ) Change subject: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes ...................................................................... [RFC]arch/x86: Only allow normal and fallback cbfs prefixes Using other cbfsprefixes is errorprone: It requires a properly formatted cbfs file to be present (an error in the cbfsfile will render the system unbootable) and to correctly enter the cbfs prefix in menuconfig. Therefore remove this functionality that merely allows to use different names. Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/bootblock_normal.c 2 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35823/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..5b2a615 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -48,13 +48,10 @@ config CBFS_PREFIX_NORMAL bool "normal" -config CBFS_PREFIX_DIY - bool "Define your own cbfs prefix" - endchoice config CBFS_PREFIX - string "CBFS prefix to use" if CBFS_PREFIX_DIY + string default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK default "normal" if CBFS_PREFIX_NORMAL help diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 905ecb2..c55eda2 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -16,18 +16,9 @@ #include <pc80/mc146818rtc.h> #include <halt.h> -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - static void main(unsigned long bist) { u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; if (boot_cpu()) { bootblock_mainboard_init(); @@ -44,20 +35,15 @@ boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - unsigned long entry; if (boot_mode) { - entry = findstage(normal_candidate); + entry = findstage("normal/romstage"); if (entry) call(entry, bist); } - entry = findstage(get_fallback(normal_candidate)); + entry = findstage("fallback/romstage"); if (entry) call(entry, bist); -- To view, visit https://review.coreboot.org/c/coreboot/+/35823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Gerrit-Change-Number: 35823 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]Makefile.inc: Add Macro to generate cbfs int files
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33353 Change subject: [WIP]Makefile.inc: Add Macro to generate cbfs int files ...................................................................... [WIP]Makefile.inc: Add Macro to generate cbfs int files Add the makefile function 'add-cbfs-int' to generate cbfs files containing a little endian integer. Adding cbfs files containing a 64 bit is usually done with cbfstool add-int, but this requires the coreboot.rom image to be already build which clutters the Makefile. Instead add a method to cleanly generate the cbfsfile containing a 64bit little endian int which integrates better with the rest of the makefile. Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33353/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..d0f47e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -788,6 +788,20 @@ $(call cbfs-add-cmd-for-region,$(1),$(2)) endef +# add-cbfs-int (little endian) +# $(call add-cbfs-int, +# integer +# cbfs-file-name) +define add-cbfs-int + $(eval tmp_int:=$(shell mktemp -u int_file.XXXX)) + $(eval $(obj)/$(tmp_int): + echo -n -e $$$$(printf "%016x" $$$$(($(1))) \ + | sed -re "s/(..)(..)(..)(..)(..)(..)(..)(..)/\\\x\8\\\x\7\\\x\6\\\x\5\\\x\4\\\x\3\\\x\2\\\x\1/") > $$@) + cbfs-files-y += $(2) + $(2)-file := $(obj)/$(tmp_int) + $(2)-type := raw +endef + # list of files to add (using their file system names, not CBFS names), # for dependencies etc. prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) @@ -1064,18 +1078,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efa..24eeba6 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -110,6 +110,18 @@ bootorder-type := raw endif +# Add SeaBIOS PS2 timeout file +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_PS2_TIMEOUT),etc/ps2-keyboard-spinup)) +endif +endif + +# Add SeaBIOS Sercon port file +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_SERCON_PORT_ADDR),etc/sercon-port)) +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/33353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Gerrit-Change-Number: 33353 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: lenovo/g505s: enable device 14.5 FCH USB OHCI Controller
by Mike Banon (Code Review) 20 Apr '22

20 Apr '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47916 ) Change subject: lenovo/g505s: enable device 14.5 FCH USB OHCI Controller ...................................................................... lenovo/g505s: enable device 14.5 FCH USB OHCI Controller I enabled this device hoping to get a webcam working. It still doesn't but there aren't any downsides. For a coreboot master to be a slightly better foundation for getting it working eventually, please merge. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I37547eb951a0afc5da5a12618769975d7071e283 --- M src/mainboard/lenovo/g505s/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47916/1 diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 4b4df36..fba2300 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -41,7 +41,7 @@ end end device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 + device pci 14.5 on end # FCH USB OHCI Controller device pci 14.6 off end # Gec device pci 14.7 off end # SD device pci 15.0 off end # PCIe 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/47916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37547eb951a0afc5da5a12618769975d7071e283 Gerrit-Change-Number: 47916 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Revert "util: Remove 'getpir' and 'mptable' tools"
by Mike Banon (Code Review) 20 Apr '22

20 Apr '22

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Alexandru Gagniuc, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48322 to review the following change. Change subject: Revert "util: Remove 'getpir' and 'mptable' tools" ...................................................................... Revert "util: Remove 'getpir' and 'mptable' tools" This reverts commit 6c90f3334e65ff4b0ff4900df77bc33d53beb677. Reason for revert: Although the output of these tools is indeed far from being perfect, still it could be used as a nice starting point. Change-Id: Ieff7673387ae9275b8271f4a483926b774697a8d --- A util/getpir/Makefile A util/getpir/README A util/getpir/checkpir.c A util/getpir/checksum.c A util/getpir/checksum.h A util/getpir/code_gen.c A util/getpir/code_gen.h A util/getpir/getpir.c A util/getpir/pirq_routing.h A util/mptable/Makefile A util/mptable/mptable.c 11 files changed, 1,708 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48322/1 diff --git a/util/getpir/Makefile b/util/getpir/Makefile new file mode 100644 index 0000000..94270f5 --- /dev/null +++ b/util/getpir/Makefile @@ -0,0 +1,24 @@ +# +# +# + +CC=gcc +CFLAGS=-O2 -D_GNU_SOURCE -DGETPIR -Wall + +all: getpir + +getpir: getpir.o checksum.o code_gen.o + $(CC) $(CFLAGS) -o getpir $^ + +checkpir: checkpir.c checksum.o irq_tables.o + $(CC) $(CFLAGS) -o checkpir $^ + +irq_tables.c: getpir + ./getpir + +clean: + rm -f getpir checkpir *.o *~ + +distclean: clean + rm -f irq_tables.o irq_tables.c + diff --git a/util/getpir/README b/util/getpir/README new file mode 100644 index 0000000..6514585 --- /dev/null +++ b/util/getpir/README @@ -0,0 +1,30 @@ +ABOUT: + +This utility will help to create irq_table.c file, that is very hard to create +manually, specialy when you are testing new motherboards, changing your +hardware often, placing new cards, etc.. + +USAGE: + +Steps +1. make distclean; +2. make getpir +3. ./getpir + + Will dump irq table to the file called irq_tables.c, ready to use with + coreboot. Just move the file to corresponding place in the coreboot tree. + + +4. CHECKING CUSTOM irq_tables.c: + + make checkpir + ./checkpir + + checkpir.c Will verify the irq_tables.c, currently it only checks the + checksum. In case of wrong checksum, a good value is proposed, so you can + edit irq_tables.c manualy and replace checksum. + + +Do not run make checkpir and ./checkpir directly because it needs to be linked +to irq_table.o first. + diff --git a/util/getpir/checkpir.c b/util/getpir/checkpir.c new file mode 100644 index 0000000..c9703c6 --- /dev/null +++ b/util/getpir/checkpir.c @@ -0,0 +1,31 @@ +/* checkpir.c : This software is released under GPL + * For coreboot use only + * Aug 26 2001 , Nikolai Vladychevski, <niko(a)isl.net.mx> + */ + +#include <stdio.h> +#include "pirq_routing.h" +#include "checksum.h" + +struct irq_routing_table *rt; + +int main(void) +{ + uint8_t sum, newsum; + + rt = (struct irq_routing_table *) &intel_irq_routing_table; + sum = calc_checksum(rt); + + printf("Validating checksum, file: irq_tables.c that was in ./ at compile time...\n"); + printf("(no other tests are done)\n"); + + if (!sum) { + printf("Checksum for IRQ Routing table is ok. You can use irq_tables.c in coreboot now.\n"); + } else { + newsum = rt->checksum - sum; + printf("BAD CHECKSUM for IRQ Routing table !!!!\n"); + printf("If you want to make it valid, change the checksum to: %#x\n", + newsum); + } + return 0; +} diff --git a/util/getpir/checksum.c b/util/getpir/checksum.c new file mode 100644 index 0000000..bcf3425 --- /dev/null +++ b/util/getpir/checksum.c @@ -0,0 +1,13 @@ +#include "pirq_routing.h" +#include "checksum.h" + +int calc_checksum(struct irq_routing_table *rt) +{ + long i; + uint8_t *addr, sum = 0; + + addr = (uint8_t *) rt; + for (i = 0; i < rt->size; i++) + sum += addr[i]; + return (sum); +} diff --git a/util/getpir/checksum.h b/util/getpir/checksum.h new file mode 100644 index 0000000..2acc433 --- /dev/null +++ b/util/getpir/checksum.h @@ -0,0 +1,6 @@ +#ifndef __CHECKSUM_H__ +#define __CHECKSUM_H__ + +int calc_checksum(struct irq_routing_table *rt); + +#endif /* __CHECKSUM_H__ */ diff --git a/util/getpir/code_gen.c b/util/getpir/code_gen.c new file mode 100644 index 0000000..d15715c --- /dev/null +++ b/util/getpir/code_gen.c @@ -0,0 +1,88 @@ +#include <stdio.h> +#include <stdlib.h> +#include "pirq_routing.h" + +static char *preamble[] = { + + "/*\n", + " * This file is part of the coreboot project.\n", + " *\n", + " * Copyright (C) 200x TODO <TODO@TODO>\n", + " *\n", + " * This program is free software; you can redistribute it and/or modify\n", + " * it under the terms of the GNU General Public License as published by\n", + " * the Free Software Foundation; either version 2 of the License, or\n", + " * (at your option) any later version.\n", + " *\n", + " * This program is distributed in the hope that it will be useful,\n", + " * but WITHOUT ANY WARRANTY; without even the implied warranty of\n", + " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n", + " * GNU General Public License for more details.\n", + " *\n", + " * You should have received a copy of the GNU General Public License\n", + " * along with this program; if not, write to the Free Software\n", + " * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\n", + " */\n\n", + "#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */\n", + "#include \"pirq_routing.h\" /* TODO: Drop this when copying to coreboot. */\n", + "#else /* TODO: Drop this when copying to coreboot. */\n" + "#include <arch/pirq_routing.h>\n", + "#endif /* TODO: Drop this when copying to coreboot. */\n\n" + "const struct irq_routing_table intel_irq_routing_table = {\n", + "\tPIRQ_SIGNATURE, /* u32 signature */\n", + "\tPIRQ_VERSION, /* u16 version */\n", + 0 +}; + +void code_gen(char *filename, struct irq_routing_table *rt) +{ + char **code = preamble; + struct irq_info *se_arr = (struct irq_info *) ((char *) rt + 32); + int i, ts = (rt->size - 32) / 16; + FILE *fpir; + + if ((fpir = fopen(filename, "w")) == NULL) { + printf("Failed creating file!\n"); + exit(2); + } + + while (*code) + fprintf(fpir, "%s", *code++); + + fprintf(fpir, "\t32 + 16 * %d, /* Max. number of devices on the bus */\n", + ts); + fprintf(fpir, "\t0x%02x, /* Interrupt router bus */\n", + rt->rtr_bus); + fprintf(fpir, "\t(0x%02x << 3) | 0x%01x, /* Interrupt router dev */\n", + rt->rtr_devfn >> 3, rt->rtr_devfn & 7); + fprintf(fpir, "\t%#x, /* IRQs devoted exclusively to PCI usage */\n", + rt->exclusive_irqs); + fprintf(fpir, "\t%#x, /* Vendor */\n", rt->rtr_vendor); + fprintf(fpir, "\t%#x, /* Device */\n", rt->rtr_device); + fprintf(fpir, "\t%#x, /* Miniport */\n", + rt->miniport_data); + fprintf(fpir, "\t{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */\n"); + fprintf(fpir, "\t%#x, /* Checksum (has to be set to some value that\n * would give 0 after the sum of all bytes\n * for this structure (including checksum).\n */\n", + rt->checksum); + fprintf(fpir, "\t{\n"); + fprintf(fpir, "\t\t/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */\n"); + for (i = 0; i < ts; i++) { + fprintf(fpir, "\t\t{0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", + (se_arr+i)->bus, (se_arr+i)->devfn >> 3, + (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, + (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link, + (se_arr+i)->irq[1].bitmap, (se_arr+i)->irq[2].link, + (se_arr+i)->irq[2].bitmap, (se_arr+i)->irq[3].link, + (se_arr+i)->irq[3].bitmap, (se_arr+i)->slot, + (se_arr+i)->rfu); + } + fprintf(fpir, "\t}\n"); + fprintf(fpir, "};\n"); + + fprintf(fpir, "\nunsigned long write_pirq_routing_table(unsigned long addr)\n"); + fprintf(fpir, "{\n"); + fprintf(fpir, "\treturn copy_pirq_routing_table(addr);\n"); + fprintf(fpir, "}\n"); + + fclose(fpir); +} diff --git a/util/getpir/code_gen.h b/util/getpir/code_gen.h new file mode 100644 index 0000000..93bdaec --- /dev/null +++ b/util/getpir/code_gen.h @@ -0,0 +1,6 @@ +#ifndef __CODE_GEN_H__ +#define __CODE_GEN_H__ + +void code_gen(char *filename, struct irq_routing_table *rt); + +#endif /* __CODE_GEN_H__ */ diff --git a/util/getpir/getpir.c b/util/getpir/getpir.c new file mode 100644 index 0000000..9853d7c --- /dev/null +++ b/util/getpir/getpir.c @@ -0,0 +1,189 @@ +/* getpir.c : This software is released under GPL + * For coreboot use only + * Aug 26 2001 , Nikolai Vladychevski, <niko(a)isl.net.mx> + * 2007.04.09 Jeremy Jackson <jerj(a)coplanar.net> + * updated for amd64 and general 64 bit portability + * 2010.04.24 Marc Bertens <mbertens(a)xs4all.nl> + * Added functionality to read a image file for checking the checksum of the PIR + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> + +#include "pirq_routing.h" +#include "checksum.h" +#include "code_gen.h" + +#if defined (__sun) && (defined(__i386) || defined(__amd64)) +# define MEM_DEV "/dev/xsvc" +#else +# define MEM_DEV "/dev/mem" +#endif + +/** + * The probe_table() is now called with the pointer to the memory, + * this is to handle both the assessing memory and a file. + * + * This function now dumps the table found to the stdout, with + * descriptions, it is special handy when building a PIRQ table + * for a board to check the checksum. + */ +static struct irq_routing_table *probe_table(char* ptr) +{ + /** + * Signature to search for $PIR<2-byte-version> + * + * this is to be sure that we find the correct table. + */ + char signature[] = "$PIR\x00\x01"; + /** cast the pointer */ + struct irq_routing_table *rt = (struct irq_routing_table *)ptr; + int size = 16; + int checksum_result; + do { + /** find the PIRQ table */ + rt = (struct irq_routing_table *) memmem(ptr + size, 16, signature, 6); + if (rt != NULL) { + /** found the table */ + int i, ts = (rt->size - 32) / 16; + struct irq_info *se_arr; + se_arr = (struct irq_info *) ((char *) rt + 32); + /** Dump the table information to the stdout */ + printf("Found PCI IRQ routing table signature at %p.\n", (void *) ((char *) rt - ptr + 0xf0000)); + printf("SIGNATURE = %s\n", (char*)&rt->signature); + printf("VERSION = %04x\n", rt->version); + printf("SIZE = %i\n", rt->size); + printf("MAX_DEVICES_ON_BUS = 32 + 16 * %d\n", ts); + printf("INT_ROUTER_BUS = 0x%02x\n", rt->rtr_bus); + printf("INT_ROUTER DEVICE = (0x%02x << 3) | 0x%01x\n", rt->rtr_devfn >> 3, rt->rtr_devfn & 7); + printf("IRQ_DEVOTED_TO_PCI = %#x\n", rt->exclusive_irqs); + printf("VENDOR = %#x\n", rt->rtr_vendor); + printf("DEVICE = %#x\n", rt->rtr_device); + printf("MINIPORT = %#x\n", rt->miniport_data); + printf("CHECKSUM = %#x\n", rt->checksum); + printf("\tbus , dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu\n"); + for (i = 0; i < ts; i++) { + printf("\t0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", + (se_arr+i)->bus, (se_arr+i)->devfn >> 3, + (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, + (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link, + (se_arr+i)->irq[1].bitmap, (se_arr+i)->irq[2].link, + (se_arr+i)->irq[2].bitmap, (se_arr+i)->irq[3].link, + (se_arr+i)->irq[3].bitmap, (se_arr+i)->slot, + (se_arr+i)->rfu); + } + /** A table should not be over 0x400 bytes */ + if (rt->size > 0x400) { + return NULL; + } + printf("Validating...\n"); + /** Calculate the checksum value */ + checksum_result = calc_checksum(rt); + /** Show the calculatedchecksum value */ + printf("CHECKSUM = %#x\n", 0x100-((checksum_result - rt->checksum) & 0xFF)); + /** and the result of the calculation */ + if (!checksum_result) { + printf("checksum is ok.\n"); + break; + } else { + printf("checksum is wrong.\n"); + } + } + size += 16; + } while (size < 0xFFFF); + if (size >= 0xFFFF) { + /** When the functions comes here there is no PIRQ table found. */ + printf("No PCI IRQ routing table signature found.\n"); + return NULL; + } + + return rt; +} + +int main(int argc, char* argv[]) +{ + char* ptr; + int fd_mem = -1; + struct irq_routing_table* rt = NULL; + void* bios_image = NULL; + if ( argc > 1 ) + { + /** there a paramater passed to the program, assume that it is a menory file */ + printf("Opening memory image file '%s'\n", argv[1]); + /** Open the file */ + fd_mem = open(argv[1], O_RDONLY); + if (fd_mem > 0) { + /** get tyhe size of the file */ + int file_size = lseek(fd_mem, 0, SEEK_END); + printf("Memory image '%i'\n", file_size); + /** get a memory block for it. */ + bios_image = malloc(file_size); + if (bios_image) { + /** Fill the created buffer */ + lseek(fd_mem, 0, SEEK_SET); + read(fd_mem, bios_image, file_size); + /** set the pointer for the probe function */ + ptr = (char*)bios_image; + } else { + /* no memory available ? */ + perror("Failed to open imagefile\n"); + return (-3); + } + } else { + /** An error occourd, just exit with a message */ + perror("Failed to open imagefile"); + return (-2); + } + } else { + /** No paramaters means that the program will access the system memory */ + printf("Accessing memory\n"); + if (getuid()) { + /** i'm not root message !!!! */ + fprintf(stderr, "Run me as root, I need access to " MEM_DEV ".\n"); + } + /** open the system memory */ + fd_mem = open(MEM_DEV, O_RDONLY); + if (fd_mem < 0) { + /** could not open the system memory, exit with a message */ + perror("Could not open " MEM_DEV ":"); + exit(1); + } + printf("Probing PIRQ table in memory.\n"); + ptr = mmap(0, 0x10000, PROT_READ, MAP_SHARED, fd_mem, (off_t)0xf0000); + if (ptr == MAP_FAILED) { + /** could not map the system memory, exit with a message */ + perror("Mapping system memory failed: "); + close(fd_mem); + return (1); + } + } + if (ptr) { + /** now do the actual probe function */ + rt = probe_table(ptr); + if (rt != NULL && bios_image == NULL) { + /** when probing system memory we write the 'irq_tables.c' code file */ + printf("Creating irq_tables.c ...\n"); + code_gen("irq_tables.c", rt); + printf("Done, you can move the file to the coreboot tree now.\n"); + } + } else { + printf("invalid memory pointer\n"); + } + if (bios_image) { + /** when we are reading from a file the memory must be released */ + free(bios_image); + } else { + /** when reading from the system memory, it must be unmapped */ + munmap(ptr, 0x10000); + } + /** Close the file handle */ + close(fd_mem); + /** return 0 as OK ) */ + return 0; +} diff --git a/util/getpir/pirq_routing.h b/util/getpir/pirq_routing.h new file mode 100644 index 0000000..88adc21 --- /dev/null +++ b/util/getpir/pirq_routing.h @@ -0,0 +1,55 @@ +#ifndef ARCH_PIRQ_ROUTING_H +#define ARCH_PIRQ_ROUTING_H + +#include <stdint.h> + +#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) +#define PIRQ_VERSION 0x0100 + +struct irq_info { + uint8_t bus, devfn; /* Bus, device and function */ + struct { + uint8_t link; /* IRQ line ID, chipset dependent, 0=not routed */ + uint16_t bitmap; /* Available IRQs */ + } __attribute__((packed)) irq[4]; + uint8_t slot; /* Slot number, 0=onboard */ + uint8_t rfu; +} __attribute__((packed)); + +#if defined(CONFIG_IRQ_SLOT_COUNT) +#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT +#elif (__GNUC__ < 3) +#define IRQ_SLOTS_COUNT 1 +#else +#define IRQ_SLOTS_COUNT +#endif + +struct irq_routing_table { + uint32_t signature; /* PIRQ_SIGNATURE should be here */ + uint16_t version; /* PIRQ_VERSION */ + uint16_t size; /* Table size in bytes */ + uint8_t rtr_bus, rtr_devfn; /* Where the interrupt router lies */ + uint16_t exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ + uint16_t rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */ + uint32_t miniport_data; /* Miniport data */ + uint8_t rfu[11]; + uint8_t checksum; /* Modulo 256 checksum must give zero */ + struct irq_info slots[IRQ_SLOTS_COUNT]; +} __attribute__((packed)); + +extern const struct irq_routing_table intel_irq_routing_table; + +#ifdef GETPIR +#define copy_pirq_routing_table(start) (start) +unsigned long write_pirq_routing_table(unsigned long start); +#else +#if CONFIG_HAVE_PIRQ_TABLE==1 +unsigned long copy_pirq_routing_table(unsigned long start); +unsigned long write_pirq_routing_table(unsigned long start); +#else +#define copy_pirq_routing_table(start) (start) +#define write_pirq_routing_table(start) (start) +#endif +#endif + +#endif /* ARCH_PIRQ_ROUTING_H */ diff --git a/util/mptable/Makefile b/util/mptable/Makefile new file mode 100644 index 0000000..f88367e --- /dev/null +++ b/util/mptable/Makefile @@ -0,0 +1,8 @@ +CC=gcc +CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare + +mptable: mptable.c + $(CC) $(CFLAGS) -o $@ $< + +clean: + rm -f mptable diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c new file mode 100644 index 0000000..5b8a59d --- /dev/null +++ b/util/mptable/mptable.c @@ -0,0 +1,1258 @@ +/* + * Copyright (c) 1996, by Steve Passe + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * mptable.c + */ + +#define VMAJOR 2 +#define VMINOR 0 +#define VDELTA 15 + +/* + * this will cause the raw mp table to be dumped to /tmp/mpdump + * +#define RAW_DUMP + */ + +#define MP_SIG 0x5f504d5f /* _MP_ */ +#define EXTENDED_PROCESSING_READY +#define OEM_PROCESSING_READY_NOT + +#include <sys/types.h> +#include <err.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <stdint.h> + +#define ARRAY_SIZE(_x) (sizeof(_x) / sizeof(_x[0])) +#define SEP_LINE \ +"\n-------------------------------------------------------------------------------\n" + +#define SEP_LINE2 \ +"\n===============================================================================\n" + +/* EBDA is @ 40:0e in real-mode terms */ +#define EBDA_POINTER 0x040e /* location of EBDA pointer */ + +/* CMOS 'top of mem' is @ 40:13 in real-mode terms */ +#define TOPOFMEM_POINTER 0x0413 /* BIOS: base memory size */ + +#define DEFAULT_TOPOFMEM 0xa0000 + +#define BIOS_BASE 0xf0000 +#define BIOS_BASE2 0xe0000 +#define BIOS_SIZE 0x10000 +#define ONE_KBYTE 1024 + +#define GROPE_AREA1 0x80000 +#define GROPE_AREA2 0x90000 +#define GROPE_SIZE 0x10000 + +#define PROCENTRY_FLAG_EN 0x01 +#define PROCENTRY_FLAG_BP 0x02 +#define IOAPICENTRY_FLAG_EN 0x01 + +#define MAXPNSTR 132 + +#define COREBOOT_MP_TABLE 0 + +enum busTypes { + CBUS = 1, + CBUSII = 2, + EISA = 3, + ISA = 6, + PCI = 13, + XPRESS = 18, + MAX_BUSTYPE = 18, + UNKNOWN_BUSTYPE = 0xff +}; + +typedef struct BUSTYPENAME { + uint8_t type; + char name[7]; +} busTypeName; + +static busTypeName busTypeTable[] = { + {CBUS, "CBUS"}, + {CBUSII, "CBUSII"}, + {EISA, "EISA"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {ISA, "ISA"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {PCI, "PCI"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"} +}; + +char *whereStrings[] = { + "Extended BIOS Data Area", + "BIOS top of memory", + "Default top of memory", + "BIOS", + "Extended BIOS", + "GROPE AREA #1", + "GROPE AREA #2" +}; + +typedef struct TABLE_ENTRY { + uint8_t type; + uint8_t length; + char name[32]; +} tableEntry; + +tableEntry basetableEntryTypes[] = { + {0, 20, "Processor"}, + {1, 8, "Bus"}, + {2, 8, "I/O APIC"}, + {3, 8, "I/O INT"}, + {4, 8, "Local INT"} +}; + +tableEntry extendedtableEntryTypes[] = { + {128, 20, "System Address Space"}, + {129, 8, "Bus Heirarchy"}, + {130, 8, "Compatibility Bus Address"} +}; + +/* MP Floating Pointer Structure */ +typedef struct MPFPS { + uint8_t signature[4]; + uint32_t pap; + uint8_t length; + uint8_t spec_rev; + uint8_t checksum; + uint8_t mpfb1; + uint8_t mpfb2; + uint8_t mpfb3; + uint8_t mpfb4; + uint8_t mpfb5; +} mpfps_t; + +/* MP Configuration Table Header */ +typedef struct MPCTH { + uint8_t signature[4]; + uint16_t base_table_length; + uint8_t spec_rev; + uint8_t checksum; + uint8_t oem_id[8]; + uint8_t product_id[12]; + uint32_t oem_table_pointer; + uint16_t oem_table_size; + uint16_t entry_count; + uint32_t apic_address; + uint16_t extended_table_length; + uint8_t extended_table_checksum; + uint8_t reserved; +} mpcth_t; + +typedef struct PROCENTRY { + uint8_t type; + uint8_t apicID; + uint8_t apicVersion; + uint8_t cpuFlags; + uint32_t cpuSignature; + uint32_t featureFlags; + uint32_t reserved1; + uint32_t reserved2; +} ProcEntry; + +typedef struct BUSENTRY { + uint8_t type; + uint8_t busID; + uint8_t busType[6]; +} BusEntry; + +typedef struct IOAPICENTRY { + uint8_t type; + uint8_t apicID; + uint8_t apicVersion; + uint8_t apicFlags; + uint32_t apicAddress; +} IOApicEntry; + +typedef struct INTENTRY { + uint8_t type; + uint8_t intType; + uint16_t intFlags; + uint8_t srcBusID; + uint8_t srcBusIRQ; + uint8_t dstApicID; + uint8_t dstApicINT; +} IntEntry; + +/* + * extended entry type structures + */ + +typedef struct SASENTRY { + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t addressType; + uint64_t addressBase; + uint64_t addressLength; +} SasEntry; + +typedef struct BHDENTRY { + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t busInfo; + uint8_t busParent; + uint8_t reserved[3]; +} BhdEntry; + +typedef struct CBASMENTRY { + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t addressMod; + uint32_t predefinedRange; +} CbasmEntry; + +typedef uint32_t vm_offset_t; + +static void apic_probe(vm_offset_t * paddr, int *where); + +static void MPConfigDefault(int featureByte); + +static void MPFloatingPointer(vm_offset_t paddr, int where, mpfps_t * mpfps); +static void MPConfigTableHeader(uint32_t pap); + +static int readType(void); +static void seekEntry(vm_offset_t addr); +static void readEntry(void *entry, int size); + +static void processorEntry(void); +static void busEntry(void); +static void ioApicEntry(void); +static void intEntry(void); +static void lintEntry(void); + +static void sasEntry(void); +static void bhdEntry(void); +static void cbasmEntry(void); + +static void doOptionList(void); +static void doDmesg(void); +static void pnstr(uint8_t * s, int c); + +/* global data */ +int pfd; /* physical /dev/mem fd */ + +int busses[32]; +int apics[16]; + +int ncpu; +int nbus; +int napic; +int nintr; + +int dmesg = 0; +int grope = 0; +int verbose = 0; +int noisy = 0; +/* preamble to the mptable. This is fixed for all coreboots */ + +char *preamble[] = { + "#include <console/console.h>", + "#include <arch/smp/mpspec.h>", + "#include <arch/ioapic.h>", + "#include <device/pci.h>", + "#include <string.h>", + "#include <stdint.h>", + "", + "#define INTA 0x00", + "#define INTB 0x01", + "#define INTC 0x02", + "#define INTD 0x03", + "", + "static void *smp_write_config_table(void *v)", + "{", + " struct mp_config_table *mc;", + "", + " mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);", + "", + " mptable_init(mc, \"TODO \", LOCAL_APIC_ADDR);", + "", + " smp_write_processors(mc);", + "", + 0 +}; + +char *postamble[] = { + " /* Compute the checksums. */", + " mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);", + " mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);", + " printk(BIOS_DEBUG, \"Wrote the mp table end at: %p - %p\\n\",", + " mc, smp_next_mpe_entry(mc));", + " return smp_next_mpe_entry(mc);", + "}", + "", + "unsigned long write_smp_table(unsigned long addr)", + "{", + " void *v;", + " v = smp_write_floating_table(addr);", + " return (unsigned long)smp_write_config_table(v);", + "}", + 0 +}; + +static void usage(void) +{ + fprintf(stderr, + "usage: mptable [-dmesg] [-verbose] [-grope] [-help]\n"); + exit(0); +} + +void write_code(char **code) +{ + while (*code) + printf("%s\n", *code++); +} + +/* + * + */ +int main(int argc, char *argv[]) +{ + vm_offset_t paddr; + int where; + mpfps_t mpfps; + int defaultConfig; + + /* announce ourselves */ + + if (verbose) + puts(SEP_LINE2); + + printf("/* generated by MPTable, version %d.%d.%d*/\n", VMAJOR, VMINOR, + VDELTA); + printf("/* as modified by RGM for coreboot */\n"); + write_code(preamble); + + /* Ron hates getopt() */ + + for (argc--, argv++; argc; argc--, argv++) { + if (strcmp(argv[0], "-dmesg") == 0) { + dmesg = 1; + } else if (strcmp(argv[0], "-help") == 0) { + usage(); + } else if (strcmp(argv[0], "-grope") == 0) { + grope = 1; + } else if (strcmp(argv[0], "-verbose") == 0) + verbose = 1; + else if (strcmp(argv[0], "-noisy") == 0) + noisy = 1; + else + usage(); + } + + /* open physical memory for access to MP structures */ + if ((pfd = open("/dev/mem", O_RDONLY)) < 0) + err(1, "mem open"); + + /* probe for MP structures */ + apic_probe(&paddr, &where); + if (where <= 0) { + fprintf(stderr, "\n MP FPS NOT found,\n"); + fprintf(stderr, " suggest trying -grope option!!!\n\n"); + return 1; + } + + if (verbose) + printf("\n MP FPS found in %s @ physical addr: 0x%08x\n", + whereStrings[where - 1], paddr); + + if (verbose) + puts(SEP_LINE); + + /* analyze the MP Floating Pointer Structure */ + MPFloatingPointer(paddr, where, &mpfps); + + if (verbose) + puts(SEP_LINE); + + /* check whether an MP config table exists */ + if ((defaultConfig = mpfps.mpfb1)) + MPConfigDefault(defaultConfig); + else + MPConfigTableHeader(mpfps.pap); + + /* build "options" entries for the kernel config file */ + if (noisy) + doOptionList(); + + write_code(postamble); + /* do a dmesg output */ + if (dmesg) + doDmesg(); + + if (verbose) + puts(SEP_LINE2); + + return 0; +} + +/* + * set PHYSICAL address of MP floating pointer structure + */ +#define NEXT(X) ((X) += 4) +static void apic_probe(vm_offset_t * paddr, int *where) +{ + /* + * c rewrite of apic_probe() by Jack F. Vogel + */ + + int x; + u_short segment; + vm_offset_t target; + u_int buffer[BIOS_SIZE / sizeof(int)]; + + if (verbose) + printf("\n"); + + /* search Extended Bios Data Area, if present */ + if (verbose) + printf(" looking for EBDA pointer @ 0x%04x, ", EBDA_POINTER); + seekEntry((vm_offset_t) EBDA_POINTER); + readEntry(&segment, 2); + if (segment) { /* search EBDA */ + target = (vm_offset_t) segment << 4; + if (verbose) + printf("found, searching EBDA @ 0x%08x\n", target); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 1; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + } else { + if (verbose) + printf("NOT found\n"); + } + + target = 0; + segment = 0; + if (verbose) + printf(" searching for coreboot MP table @ 0x%08x (%dK)\n", + target, segment); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 2; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + + /* read CMOS for real top of mem */ + seekEntry((vm_offset_t) TOPOFMEM_POINTER); + readEntry(&segment, 2); + --segment; /* less ONE_KBYTE */ + target = segment * 1024; + if (verbose) + printf(" searching CMOS 'top of mem' @ 0x%08x (%dK)\n", + target, segment); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 2; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + + /* we don't necessarily believe CMOS, check base of the last 1K of 640K */ + if (target != (DEFAULT_TOPOFMEM - 1024)) { + target = (DEFAULT_TOPOFMEM - 1024); + if (verbose) + printf + (" searching default 'top of mem' @ 0x%08x (%dK)\n", + target, (target / 1024)); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 3; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + } + + /* search the BIOS */ + if (verbose) + printf(" searching BIOS @ 0x%08x\n", BIOS_BASE); + seekEntry(BIOS_BASE); + readEntry(buffer, BIOS_SIZE); + + for (x = 0; x < BIOS_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 4; + *paddr = (x * sizeof(unsigned int)) + BIOS_BASE; + return; + } + } + + /* search the extended BIOS */ + if (verbose) + printf(" searching extended BIOS @ 0x%08x\n", BIOS_BASE2); + seekEntry(BIOS_BASE2); + readEntry(buffer, BIOS_SIZE); + + for (x = 0; x < BIOS_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 5; + *paddr = (x * sizeof(unsigned int)) + BIOS_BASE2; + return; + } + } + + if (grope) { + /* search additional memory */ + target = GROPE_AREA1; + if (verbose) + printf(" groping memory @ 0x%08x\n", target); + seekEntry(target); + readEntry(buffer, GROPE_SIZE); + + for (x = 0; x < GROPE_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 6; + *paddr = + (x * sizeof(unsigned int)) + GROPE_AREA1; + return; + } + } + + target = GROPE_AREA2; + if (verbose) + printf(" groping memory @ 0x%08x\n", target); + seekEntry(target); + readEntry(buffer, GROPE_SIZE); + + for (x = 0; x < GROPE_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 7; + *paddr = + (x * sizeof(unsigned int)) + GROPE_AREA2; + return; + } + } + } + + *where = 0; + *paddr = (vm_offset_t) 0; +} + +/* + * + */ +static void MPFloatingPointer(vm_offset_t paddr, int where, mpfps_t * mpfps) +{ + + /* read in mpfps structure */ + seekEntry(paddr); + readEntry(mpfps, sizeof(mpfps_t)); + + /* show its contents */ + if (verbose) { + printf("MP Floating Pointer Structure:\n\n"); + + printf(" location:\t\t\t"); + switch (where) { + case 1: + printf("EBDA\n"); + break; + case 2: + printf("BIOS base memory\n"); + break; + case 3: + printf("DEFAULT base memory (639K)\n"); + break; + case 4: + printf("BIOS\n"); + break; + case 5: + printf("Extended BIOS\n"); + break; + + case 0: + printf("NOT found!\n"); + exit(1); + default: + printf("BOGUS!\n"); + exit(1); + } + printf(" physical address:\t\t0x%08x\n", paddr); + + printf(" signature:\t\t\t'"); + pnstr(mpfps->signature, 4); + printf("'\n"); + + printf(" length:\t\t\t%d bytes\n", mpfps->length * 16); + printf(" version:\t\t\t1.%1d\n", mpfps->spec_rev); + printf(" checksum:\t\t\t0x%02x\n", mpfps->checksum); + + /* bits 0:6 are RESERVED */ + if (mpfps->mpfb2 & 0x7f) { + printf(" warning, MP feature byte 2: 0x%02x\n", + mpfps->mpfb2); + } + + /* bit 7 is IMCRP */ + printf(" mode:\t\t\t\t%s\n", (mpfps->mpfb2 & 0x80) ? + "PIC" : "Virtual Wire"); + + /* MP feature bytes 3-5 are expected to be ZERO */ + if (mpfps->mpfb3) + printf(" warning, MP feature byte 3 NONZERO!\n"); + if (mpfps->mpfb4) + printf(" warning, MP feature byte 4 NONZERO!\n"); + if (mpfps->mpfb5) + printf(" warning, MP feature byte 5 NONZERO!\n"); + } +} + +/* + * + */ +static void MPConfigDefault(int featureByte) +{ + printf(" MP default config type: %d\n\n", featureByte); + switch (featureByte) { + case 1: + printf(" bus: ISA, APIC: 82489DX\n"); + break; + case 2: + printf(" bus: EISA, APIC: 82489DX\n"); + break; + case 3: + printf(" bus: EISA, APIC: 82489DX\n"); + break; + case 4: + printf(" bus: MCA, APIC: 82489DX\n"); + break; + case 5: + printf(" bus: ISA+PCI, APIC: Integrated\n"); + break; + case 6: + printf(" bus: EISA+PCI, APIC: Integrated\n"); + break; + case 7: + printf(" bus: MCA+PCI, APIC: Integrated\n"); + break; + default: + printf(" future type\n"); + break; + } + + switch (featureByte) { + case 1: + case 2: + case 3: + case 4: + nbus = 1; + break; + case 5: + case 6: + case 7: + nbus = 2; + break; + default: + printf(" future type\n"); + break; + } + + ncpu = 2; + napic = 1; + nintr = 16; +} + +/* + * + */ +static void MPConfigTableHeader(uint32_t pap) +{ + vm_offset_t paddr; + mpcth_t cth; + int x; + int totalSize; + int count, c; + int type; + + if (pap == 0) { + printf("MP Configuration Table Header MISSING!\n"); + exit(1); + } + + /* convert physical address to virtual address */ + paddr = (vm_offset_t) pap; + + /* read in cth structure */ + seekEntry(paddr); + readEntry(&cth, sizeof(cth)); + + if (verbose) { + printf("MP Config Table Header:\n\n"); + + printf(" physical address:\t\t0x%08x\n", pap); + + printf(" signature:\t\t\t'"); + pnstr(cth.signature, 4); + printf("'\n"); + + printf(" base table length:\t\t%d\n", cth.base_table_length); + + printf(" version:\t\t\t1.%1d\n", cth.spec_rev); + printf(" checksum:\t\t\t0x%02x\n", cth.checksum); + + printf(" OEM ID:\t\t\t'"); + pnstr(cth.oem_id, 8); + printf("'\n"); + + printf(" Product ID:\t\t\t'"); + pnstr(cth.product_id, 12); + printf("'\n"); + + printf(" OEM table pointer:\t\t0x%08x\n", + cth.oem_table_pointer); + printf(" OEM table size:\t\t%d\n", cth.oem_table_size); + + printf(" entry count:\t\t\t%d\n", cth.entry_count); + + printf(" local APIC address:\t\t0x%08x\n", cth.apic_address); + + printf(" extended table length:\t%d\n", + cth.extended_table_length); + printf(" extended table checksum:\t%d\n", + cth.extended_table_checksum); + } + + totalSize = cth.base_table_length - sizeof(struct MPCTH); + count = cth.entry_count; + + if (verbose) { + if (verbose) + puts(SEP_LINE); + + printf("MP Config Base Table Entries:\n\n"); + } + + /* initialze tables */ + for(x = 0; x < ARRAY_SIZE(busses); x++) + busses[x] = UNKNOWN_BUSTYPE; + for(x = 0; x < ARRAY_SIZE(apics); x++) + apics[x] = 0xff; + + ncpu = 0; + nbus = 0; + napic = 0; + nintr = 0; + + /* process all the CPUs */ + if (verbose) { + printf("--\nProcessors:\tAPIC ID\tVersion\tState" + "\t\tFamily\tModel\tStep\tFlags\n"); + } + for (c = count; c; c--) { + if (readType() == 0) + processorEntry(); + totalSize -= basetableEntryTypes[0].length; + } + + /* process all the busses */ + printf("\t/* Bus: Bus ID Type */\n"); + for (c = count; c; c--) { + if (readType() == 1) + busEntry(); + totalSize -= basetableEntryTypes[1].length; + } + + /* process all the apics */ + printf("\t/* I/O APICs: APIC ID Version State Address */\n"); + for (c = count; c; c--) { + if (readType() == 2) + ioApicEntry(); + totalSize -= basetableEntryTypes[2].length; + } + + /* process all the I/O Ints */ + printf("\t/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ \n"); + for (c = count; c; c--) { + if (readType() == 3) + intEntry(); + totalSize -= basetableEntryTypes[3].length; + } + + /* process all the Local Ints */ + printf + ("\t/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */\n"); + for (c = count; c; c--) { + if (readType() == 4) + lintEntry(); + totalSize -= basetableEntryTypes[4].length; + } + +#if defined( EXTENDED_PROCESSING_READY ) + /* process any extended data */ + if ((totalSize = cth.extended_table_length)) { + if (verbose) + puts(SEP_LINE); + + printf("MP Config Extended Table Entries:\n\n"); + + while (totalSize > 0) { + switch (type = readType()) { + case 128: + sasEntry(); + break; + case 129: + bhdEntry(); + break; + case 130: + cbasmEntry(); + break; + default: + printf("Extended Table HOSED!\n"); + exit(1); + } + + totalSize -= extendedtableEntryTypes[type - 128].length; + } + } +#endif /* EXTENDED_PROCESSING_READY */ + + /* process any OEM data */ + if (cth.oem_table_pointer && (cth.oem_table_size > 0)) { +#if defined( OEM_PROCESSING_READY ) +#error your on your own here! + /* convert OEM table pointer to virtual address */ + poemtp = (vm_offset_t) cth.oem_table_pointer; + + /* read in oem table structure */ + if ((oemdata = (void *)malloc(cth.oem_table_size)) == NULL) + err(1, "oem malloc"); + + seekEntry(poemtp); + readEntry(oemdata, cth.oem_table_size); + + /** process it */ + + free(oemdata); +#else + printf + ("\nyou need to modify the source to handle OEM data!\n\n"); +#endif /* OEM_PROCESSING_READY */ + } + + fflush(stdout); + +#if defined( RAW_DUMP ) + { + int ofd; + u_char dumpbuf[4096]; + + ofd = open("/tmp/mpdump", O_CREAT | O_RDWR); + seekEntry(paddr); + readEntry(dumpbuf, 1024); + write(ofd, dumpbuf, 1024); + close(ofd); + } +#endif /* RAW_DUMP */ +} + +/* + * + */ +static int readType(void) +{ + u_char type; + + if (read(pfd, &type, sizeof(u_char)) != sizeof(u_char)) + err(1, "type read; pfd: %d", pfd); + + if (lseek(pfd, -1, SEEK_CUR) < 0) + err(1, "type seek"); + + return (int)type; +} + +/* + * + */ +static void seekEntry(vm_offset_t addr) +{ + if (lseek(pfd, (off_t) addr, SEEK_SET) < 0) + err(1, "/dev/mem seek"); +} + +/* + * + */ +static void readEntry(void *entry, int size) +{ + if (read(pfd, entry, size) != size) + err(1, "readEntry"); +} + +static void processorEntry(void) +{ + ProcEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + ++ncpu; + if (noisy) { + printf("\t\t%2d", entry.apicID); + printf("\t 0x%2x", entry.apicVersion); + + printf("\t %s, %s", + (entry.cpuFlags & PROCENTRY_FLAG_BP) ? "BSP" : "AP", + (entry. + cpuFlags & PROCENTRY_FLAG_EN) ? "usable" : "unusable"); + + printf("\t %d\t %d\t %d", + (entry.cpuSignature >> 8) & 0x0f, + (entry.cpuSignature >> 4) & 0x0f, + entry.cpuSignature & 0x0f); + + printf("\t 0x%04x\n", entry.featureFlags); + } +} + +/* + * + */ +static int lookupBusType(char *name) +{ + int x; + + for (x = 0; x < MAX_BUSTYPE; ++x) + if (strcmp(busTypeTable[x].name, name) == 0) + return busTypeTable[x].type; + + return UNKNOWN_BUSTYPE; +} + +static void busEntry(void) +{ + char name[8]; + BusEntry entry; + int i; + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + ++nbus; + + if (verbose) { + printf("\t\t%2d", entry.busID); + printf("\t "); + pnstr(entry.busType, 6); + printf("\n"); + } + + memset(name, '\0', sizeof(name)); + for(i = 0; i < 6; i++) { + switch(entry.busType[i]) { + case ' ': + case '\0': + break; + default: + name[i] = entry.busType[i]; + break; + } + } + + if (entry.busID > ARRAY_SIZE(busses)) { + fprintf(stderr, "busses array to small!\n"); + exit(1); + } + + busses[entry.busID] = lookupBusType(name); + printf("\tsmp_write_bus(mc, %d, \"", entry.busID); + pnstr(entry.busType, 6); + printf("\");\n"); +} + +static void ioApicEntry(void) +{ + IOApicEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + ++napic; + + if (noisy) { + printf("\t\t%2d", entry.apicID); + printf("\t 0x%02x", entry.apicVersion); + printf("\t %s", + (entry. + apicFlags & IOAPICENTRY_FLAG_EN) ? "usable" : + "unusable"); + printf("\t\t 0x%x\n", entry.apicAddress); + } + + apics[entry.apicID] = entry.apicID; + + if (entry.apicFlags & IOAPICENTRY_FLAG_EN) + printf("\tsmp_write_ioapic(mc, 0x%x, 0x%x, 0x%x);\n", + entry.apicID, entry.apicVersion, entry.apicAddress); +} + +char *intTypes[] = { + "mp_INT", "mp_NMI", "mp_SMI", "mp_ExtINT" +}; + +char *polarityMode[] = { + "MP_IRQ_POLARITY_DEFAULT", "MP_IRQ_POLARITY_HIGH", "reserved", + "MP_IRQ_POLARITY_LOW" +}; + +char *triggerMode[] = { + "MP_IRQ_TRIGGER_DEFAULT", "MP_IRQ_TRIGGER_EDGE", "reserved", + "MP_IRQ_TRIGGER_LEVEL" +}; + +static void intEntry(void) +{ + IntEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + if ((int)entry.type == 3) + ++nintr; + + if (noisy) { + printf("\n\t\t%s", intTypes[(int)entry.intType]); + + printf("\t%9s", polarityMode[(int)entry.intFlags & 0x03]); + printf("%12s", triggerMode[((int)entry.intFlags >> 2) & 0x03]); + + printf("\t %5d", (int)entry.srcBusID); + if (busses[(int)entry.srcBusID] == PCI) + printf("\t%2d:%c", + ((int)entry.srcBusIRQ >> 2) & 0x1f, + ((int)entry.srcBusIRQ & 0x03) + 'A'); + else + printf("\t 0x%x:0x%x(0x%x)", + (int)entry.srcBusIRQ >> 2, + (int)entry.srcBusIRQ & 3, (int)entry.srcBusIRQ); + printf("\t %6d", (int)entry.dstApicID); + printf("\t %3d\n", (int)entry.dstApicINT); + } + + if (busses[(int)entry.srcBusID] == PCI) { + printf("\tsmp_write_intsrc(mc, %s, %s|%s, 0x%x, (0x%02x << 2) | INT%c, 0x%x, 0x%x);\n", + intTypes[(int)entry.intType], + triggerMode[((int)entry.intFlags >> 2) & 0x03], + polarityMode[(int)entry.intFlags & 0x03], + (int)entry.srcBusID, + (int)entry.srcBusIRQ >> 2, + ((int)entry.srcBusIRQ & 3) + 'A', + (int)entry.dstApicID, (int)entry.dstApicINT); + } else { + printf("\tsmp_write_intsrc(mc, %s, %s|%s, 0x%x, 0x%x, 0x%x, 0x%x);\n", + intTypes[(int)entry.intType], + triggerMode[((int)entry.intFlags >> 2) & 0x03], + polarityMode[(int)entry.intFlags & 0x03], + (int)entry.srcBusID, + (int)entry.srcBusIRQ, + (int)entry.dstApicID, (int)entry.dstApicINT); + } +} + +static void lintEntry(void) +{ + IntEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + if ((int)entry.type == 3) + ++nintr; + + if (noisy) { + printf("\t\t%s", intTypes[(int)entry.intType]); + + printf("\t%9s", polarityMode[(int)entry.intFlags & 0x03]); + printf("%12s", triggerMode[((int)entry.intFlags >> 2) & 0x03]); + + printf("\t %5d", (int)entry.srcBusID); + if (busses[(int)entry.srcBusID] == PCI) + printf("\t%2d:%c", + ((int)entry.srcBusIRQ >> 2) & 0x1f, + ((int)entry.srcBusIRQ & 0x03) + 'A'); + else + printf("\t %3d", (int)entry.srcBusIRQ); + printf("\t %6d", (int)entry.dstApicID); + printf("\t %3d\n", (int)entry.dstApicINT); + } + printf + ("\tsmp_write_lintsrc(mc, %s, %s|%s, 0x%x, 0x%x, MP_APIC_ALL, 0x%x);\n", + intTypes[(int)entry.intType], + triggerMode[((int)entry.intFlags >> 2) & 0x03], + polarityMode[(int)entry.intFlags & 0x03], (int)entry.srcBusID, + (int)entry.srcBusIRQ, (int)entry.dstApicINT); + +} + +static void sasEntry(void) +{ + SasEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + printf("--\n%s\n", extendedtableEntryTypes[entry.type - 128].name); + printf(" bus ID: %d", entry.busID); + printf(" address type: "); + switch (entry.addressType) { + case 0: + printf("I/O address\n"); + break; + case 1: + printf("memory address\n"); + break; + case 2: + printf("prefetch address\n"); + break; + default: + printf("UNKNOWN type\n"); + break; + } + + printf(" address base: 0x%lx\n", entry.addressBase); + printf(" address range: 0x%lx\n", entry.addressLength); +} + +static void bhdEntry(void) +{ + BhdEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + printf("--\n%s\n", extendedtableEntryTypes[entry.type - 128].name); + printf(" bus ID: %d", entry.busID); + printf(" bus info: 0x%02x", entry.busInfo); + printf(" parent bus ID: %d", entry.busParent); +} + +static void cbasmEntry(void) +{ + CbasmEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + printf("--\n%s\n", extendedtableEntryTypes[entry.type - 128].name); + printf(" bus ID: %d", entry.busID); + printf(" address modifier: %s\n", (entry.addressMod & 0x01) ? + "subtract" : "add"); + printf(" predefined range: 0x%08x", entry.predefinedRange); +} + +/* + * do a dmesg output + */ +static void doDmesg(void) +{ + if (verbose) + puts(SEP_LINE); + + printf("dmesg output:\n\n"); + fflush(stdout); + system("dmesg"); +} + +/* + * build "options" entries for the kernel config file + */ +static void doOptionList(void) +{ + if (verbose) + puts(SEP_LINE); + + printf("# SMP kernel config file options:\n\n"); + printf("\n# Required:\n"); + printf("options SMP\t\t\t# Symmetric MultiProcessor Kernel\n"); + printf("options APIC_IO\t\t\t# Symmetric (APIC) I/O\n"); + + printf("\n# Optional (built-in defaults will work in most cases):\n"); + printf("#options NCPU=%d\t\t\t# number of CPUs\n", ncpu); + printf("#options NBUS=%d\t\t\t# number of busses\n", + nbus); + printf("#options NAPIC=%d\t\t\t# number of IO APICs\n", + napic); + printf("#options NINTR=%d\t\t# number of INTs\n", + (nintr < 24) ? 24 : nintr); +} + +/* + * + */ +static void pnstr(uint8_t * s, int c) +{ + uint8_t string[MAXPNSTR + 1]; + + if (c > MAXPNSTR) + c = MAXPNSTR; + strncpy((char *)string, (char *)s, c); + string[c] = '\0'; + printf("%s", string); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieff7673387ae9275b8271f4a483926b774697a8d Gerrit-Change-Number: 48322 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 ) Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage ...................................................................... [TESTONLY]nb/intel/x4x: Cache cbmem in romstage Probably not a good idea to avoid eviction in romstage. TESTED: works fine on P5QL-EM. Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/raminit.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e24..6665eb0 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -27,6 +27,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8013af9..e8729fb 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -33,6 +33,7 @@ #include <mrc_cache.h> #include <timestamp.h> #include <types.h> +#include <cpu/x86/mtrr.h> #include "iomap.h" #include "x4x.h" @@ -718,6 +719,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); if (!fast_boot) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, -- To view, visit https://review.coreboot.org/c/coreboot/+/37213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Gerrit-Change-Number: 37213 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

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coreboot-gerrit April 2021