coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel/cnl: PEG devices
by Felix Singer (Code Review) 07 Aug '23

07 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44741 ) Change subject: soc/intel/cnl: PEG devices ...................................................................... soc/intel/cnl: PEG devices Change-Id: Ie2dd90edf10f1cefed26fe577508a9c8af3eb532 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44741/1 diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index b0430e4..35f0e59 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -22,6 +22,16 @@ #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif +#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) +#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) +#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#define SA_DEVFN_PEG3 PCI_DEVFN(SA_DEV_SLOT_PEG, 3) +#define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0) +#define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1) +#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2) +#define SA_DEV_PEG3 PCI_DEV(0, SA_DEV_SLOT_PEG, 3) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ac42e00..4b2ad50 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -131,6 +131,20 @@ if (config->DisableHeciRetry) tconfig->DisableHeciRetry = config->DisableHeciRetry; #endif + +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + dev = pcidev_path_on_root(SA_DEVFN_PEG0); + m_cfg->Peg0Enable = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_PEG1); + m_cfg->Peg1Enable = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_PEG2); + m_cfg->Peg2Enable = is_dev_enabled(dev); + + dev = pcidev_path_on_root(SA_DEVFN_PEG3); + m_cfg->Peg3Enable = is_dev_enabled(dev); +#endif } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/44741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2dd90edf10f1cefed26fe577508a9c8af3eb532 Gerrit-Change-Number: 44741 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Adds compressed RW blob to RW_A and RW_B
by Sridhar Siricilla (Code Review) 07 Aug '23

07 Aug '23

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44822 ) Change subject: soc/intel/common: Adds compressed RW blob to RW_A and RW_B ...................................................................... soc/intel/common: Adds compressed RW blob to RW_A and RW_B Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic4a8797946284359656d3b092fc55812a3de2d37 --- M src/soc/intel/common/block/cse/Makefile.inc 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44822/1 diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..7ea6fdc 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -11,4 +11,13 @@ $(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw +$(CSE_LITE_ME_RW)-compression := lzma + + +CSE_LITE_ME_RW_VER = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VER_CBFS_NAME)) +regions-for-file-$(CSE_LITE_ME_RW_VER) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_ME_RW_VER) +$(CSE_LITE_ME_RW_VER)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VER_FILE)) +$(CSE_LITE_ME_RW_VER)-name := $(CSE_LITE_ME_RW_VER) +$(CSE_LITE_ME_RW_VER)-type := raw endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a8797946284359656d3b092fc55812a3de2d37 Gerrit-Change-Number: 44822 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] mb/bostentech/gbyt4: Add libgfxinit support
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44938 ) Change subject: [TESTME] mb/bostentech/gbyt4: Add libgfxinit support ...................................................................... [TESTME] mb/bostentech/gbyt4: Add libgfxinit support Change-Id: Id729f730f93f5c26b603a5b7a94f671f7fd9bfb7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/bostentech/gbyt4/Kconfig M src/mainboard/bostentech/gbyt4/Makefile.inc A src/mainboard/bostentech/gbyt4/gma-mainboard.ads 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44938/1 diff --git a/src/mainboard/bostentech/gbyt4/Kconfig b/src/mainboard/bostentech/gbyt4/Kconfig index a267840..d5e8bda 100644 --- a/src/mainboard/bostentech/gbyt4/Kconfig +++ b/src/mainboard/bostentech/gbyt4/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select MAINBOARD_HAS_LIBGFXINIT select SUPERIO_ITE_IT8728F config MAINBOARD_DIR diff --git a/src/mainboard/bostentech/gbyt4/Makefile.inc b/src/mainboard/bostentech/gbyt4/Makefile.inc index 11a2a4a..a4fecae 100644 --- a/src/mainboard/bostentech/gbyt4/Makefile.inc +++ b/src/mainboard/bostentech/gbyt4/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += irqroute.c gpio.c bootblock-y += early_init.c romstage-y += early_init.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/bostentech/gbyt4/gma-mainboard.ads b/src/mainboard/bostentech/gbyt4/gma-mainboard.ads new file mode 100644 index 0000000..c6422a5 --- /dev/null +++ b/src/mainboard/bostentech/gbyt4/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/44938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id729f730f93f5c26b603a5b7a94f671f7fd9bfb7 Gerrit-Change-Number: 44938 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DO NOT COMMIT]: TGLRVP Disabling TBT DMA1 for UP4
by Jason V Le (Code Review) 07 Aug '23

07 Aug '23

Hello Bernardo Perez Priego, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45015 to review the following change. Change subject: [DO NOT COMMIT]: TGLRVP Disabling TBT DMA1 for UP4 ...................................................................... [DO NOT COMMIT]: TGLRVP Disabling TBT DMA1 for UP4 Change-Id: Icc61ae8a63bb84ccae74af79b10d1f11644219c3 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45015/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ccc4df8..928ae36 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -160,7 +160,7 @@ device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D + device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) -- To view, visit https://review.coreboot.org/c/coreboot/+/45015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc61ae8a63bb84ccae74af79b10d1f11644219c3 Gerrit-Change-Number: 45015 Gerrit-PatchSet: 1 Gerrit-Owner: Jason V Le <jason.v.le(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: src/arch/x86: Fix register accesses for x86_64 debugging
by Martin Schmidt (Code Review) 07 Aug '23

07 Aug '23

Martin Schmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45032 ) Change subject: src/arch/x86: Fix register accesses for x86_64 debugging ...................................................................... src/arch/x86: Fix register accesses for x86_64 debugging Code that interacts with GDB was accessing the eip and eflags filed in the eregs struct. Because those registers are rip and rflags in x86_64, compilation would fail with x86_64 + debugging enabled. Fix compilation by accessing the fields with a macro which expends to the corresponding x86_64 or x86 registers. Signed-off-by: Martin Schmidt <martin.schmidt(a)epita.fr> Change-Id: I07183fe84d083e79ccfda19df82e87c374aed84a --- M src/arch/x86/exception.c M src/arch/x86/include/arch/registers.h 2 files changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45032/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f10c7bf..07e2314 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -380,9 +380,9 @@ #if CONFIG(GDB_STUB) int signo; memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); - gdb_stub_registers[PC] = info->eip; + gdb_stub_registers[PC] = info->X86_ARCH_IP_REGISTER; gdb_stub_registers[CS] = info->cs; - gdb_stub_registers[PS] = info->eflags; + gdb_stub_registers[PS] = info->X86_ARCH_FLAGS_REGISTER; signo = GDB_UNKNOWN; if (info->vector < ARRAY_SIZE(exception_to_signal)) signo = exception_to_signal[info->vector]; @@ -416,9 +416,9 @@ copy_from_hex(&gdb_stub_registers, in_buffer + 1, sizeof(gdb_stub_registers)); memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t)); - info->eip = gdb_stub_registers[PC]; + info->X86_ARCH_IP_REGISTER = gdb_stub_registers[PC]; info->cs = gdb_stub_registers[CS]; - info->eflags = gdb_stub_registers[PS]; + info->X86_ARCH_FLAGS_REGISTER = gdb_stub_registers[PS]; memcpy(out_buffer, "OK", 3); break; case 'm': @@ -452,13 +452,13 @@ */ ptr = &in_buffer[1]; if (parse_ulong(&ptr, &addr)) - info->eip = addr; + info->X86_ARCH_IP_REGISTER = addr; /* Clear the trace bit */ - info->eflags &= ~(1 << 8); + info->X86_ARCH_FLAGS_REGISTER &= ~(1 << 8); /* Set the trace bit if we are single stepping */ if (in_buffer[0] == 's') - info->eflags |= (1 << 8); + info->X86_ARCH_FLAGS_REGISTER |= (1 << 8); return; case 'D': memcpy(out_buffer, "OK", 3); diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 5f8f9be..ec3b71a 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -67,6 +67,8 @@ QUAD_DOWNTO16(sp); uint64_t ss; }; +#define X86_ARCH_IP_REGISTER rip +#define X86_ARCH_FLAGS_REGISTER rflags #else struct eregs { LONG_DOWNTO8(a); @@ -83,7 +85,10 @@ uint32_t cs; uint32_t eflags; }; +#define X86_ARCH_IP_REGISTER eip +#define X86_ARCH_FLAGS_REGISTER eflags #endif + #endif // !ASSEMBLER #if CONFIG(COMPILER_LLVM_CLANG) -- To view, visit https://review.coreboot.org/c/coreboot/+/45032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07183fe84d083e79ccfda19df82e87c374aed84a Gerrit-Change-Number: 45032 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Schmidt Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST only]: mb/google/dedede/var/drawcia: Use TABLEMODE bit to load ...
by Chen Wisley (Code Review) 07 Aug '23

07 Aug '23

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45190 ) Change subject: [TEST only]: mb/google/dedede/var/drawcia: Use TABLEMODE bit to load LV or TFC module ...................................................................... [TEST only]: mb/google/dedede/var/drawcia: Use TABLEMODE bit to load LV or TFC module BUG=none TEST=emerge-dedede coreboot, change tabletmode bit in CBI and dump ssdt table, Change-Id: I35dcc7bb82ceb014fd40b794ccf190b226061281 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 3 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45190/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 2bb255f..c9c2803 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -11,6 +11,8 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 363307b..01fcad0 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -1,3 +1,10 @@ +fw_config + field TABLETMODE 10 + option TABLETMODE_DISABLED 0 + option TABLETMODE_ENABLED 1 + end +end + chip soc/intel/jasperlake device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 0506cd4..2c78b21 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -242,7 +242,13 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 36 on end + device i2c 36 on + probe TABLETMODE TABLETMODE_DISABLED + end + device i2c 10 on + probe TABLETMODE TABLETMODE_ENABLED + end + end chip drivers/intel/mipi_camera register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" -- To view, visit https://review.coreboot.org/c/coreboot/+/45190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dcc7bb82ceb014fd40b794ccf190b226061281 Gerrit-Change-Number: 45190 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/variants/drawcia: Reduce TCC offset from 20 to 5
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45267 ) Change subject: mb/google/dedede/variants/drawcia: Reduce TCC offset from 20 to 5 ...................................................................... mb/google/dedede/variants/drawcia: Reduce TCC offset from 20 to 5 Reduce TCC offset value from 20 to 5 for Thermal Control Circuit(TCC) activation. Change-Id: I9222a922a55d27bc175f219c5bbb59b246abec9f Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45267/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 395dee3..adde5bc 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -62,7 +62,7 @@ .tdp_pl2_override = 15, }" - register "tcc_offset" = "20" # TCC of 85C + register "tcc_offset" = "5" # TCC of 100C device domain 0 on device pci 04.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/45267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9222a922a55d27bc175f219c5bbb59b246abec9f Gerrit-Change-Number: 45267 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Relocate read to TPM base address
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45390 ) Change subject: nb/intel/x4x: Relocate read to TPM base address ...................................................................... nb/intel/x4x: Relocate read to TPM base address Other northbridges do it at the start of raminit. Also, since the TPM access register is 8 bits wide, use 8-bit ops instead of 32-bit ops. This register works the same for all TXT-enabled northbridges: If the TPM access register is valid, and the establishment bit (bit 0) is set, then a DRTM has not been established on the platform (or the TPM is not present), and the memory will be unlocked. If bit 0 is clear, then the memory may remain locked depending on whether it could contain secrets. Change-Id: Ic36a2810a861758ce733fe80c4e555439e2ffb7b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/raminit.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/45390/1 diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index baa4ae3..e83a2b8 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/bootblock.h> -#include <arch/mmio.h> #include <device/pci_ops.h> #include "x4x.h" @@ -9,9 +8,6 @@ void bootblock_early_northbridge_init(void) { - /* Disable LaGrande Technology (LT) */ - read32((void *)TPM_BASE_ADDRESS); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index a62771d..6536fbf 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <arch/mmio.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <cbmem.h> @@ -616,6 +617,9 @@ timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); + /* Disable LaGrande Technology (LT) */ + read8((void *)TPM_BASE_ADDRESS); + pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); memset(&s, 0, sizeof(struct sysinfo)); -- To view, visit https://review.coreboot.org/c/coreboot/+/45390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic36a2810a861758ce733fe80c4e555439e2ffb7b Gerrit-Change-Number: 45390 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86: Move SMI GSMI calls entry to a common place
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45474 ) Change subject: cpu/x86: Move SMI GSMI calls entry to a common place ...................................................................... cpu/x86: Move SMI GSMI calls entry to a common place Now that SMM save states are handled in a common place so can the GSMI calls entry. Change-Id: I93639d8d0fde2e874eb9b963c449be1b754ca63d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/elog/gsmi.c M src/include/elog.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 10 files changed, 37 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45474/1 diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index ebdde19..128f4a7 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <elog.h> +#include <cpu/x86/save_state.h> #define GSMI_RET_SUCCESS 0x00 #define GSMI_RET_INVALID_PARAMETER 0x82 @@ -43,7 +44,7 @@ } /* Param is usually EBX, ret in EAX */ -u32 gsmi_exec(u8 command, u32 *param) +static u32 gsmi_exec(u8 command, u32 *param) { struct gsmi_set_eventlog_param *sel; struct gsmi_set_eventlog_type1 *type1; @@ -121,3 +122,28 @@ return ret; } + +void apmc_smi_gsmi(void) +{ + u8 sub_command; + u16 ax; + u32 ret, param; + const int apmc_node = get_apmc_node(APM_CNT_ELOG_GSMI); + + if (apmc_node < 0) + return; + + /* Command and return value in EAX */ + if (get_save_state_reg(RAX, apmc_node, &ax, sizeof(ax))) + return; + + sub_command = (ax >> 8); + + /* Parameter buffer in EBX */ + if (get_save_state_reg(RBX, apmc_node, &param, sizeof(param))) + return; + + ret = gsmi_exec(sub_command, &param); + set_save_state_reg(RAX, apmc_node, &ret, sizeof(ret)); +} + diff --git a/src/include/elog.h b/src/include/elog.h index 6c2c531..89195c5 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -248,7 +248,8 @@ static inline int elog_gsmi_add_event_word(u8 event_type, u16 data) { return 0; } #endif -extern u32 gsmi_exec(u8 command, u32 *param); +void apmc_smi_gsmi(void); +//extern u32 gsmi_exec(u8 command, u32 *param); #if CONFIG(ELOG_BOOT_COUNT) u32 boot_count_read(void); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 7e762a9..89df86f 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -57,25 +57,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); -} - static void southbridge_smi_store(void) { u8 sub_command; @@ -108,7 +89,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index be55458..d55c545 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -55,25 +55,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); -} - static void southbridge_smi_store(void) { u8 sub_command; @@ -106,7 +87,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 6f3f07e..bfe933f 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -186,26 +186,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - /* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are @@ -327,7 +307,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_LEGACY: soc_legacy(); diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a2c26c11..f6ac703 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -220,26 +220,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - uint8_t sub_command; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -307,7 +287,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 86be400..ea5bf8a 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -267,27 +267,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32 *)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32 *)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -347,7 +326,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 7bd17c3..77eaad9 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -266,49 +266,6 @@ } } -static void southbridge_smi_gsmi( - const struct smm_save_state_ops *save_state_ops) -{ - u8 sub_command, ret; - void *io_smi = NULL; - uint32_t reg_ebx; - - io_smi = find_save_state(save_state_ops, APM_CNT_ELOG_GSMI); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) - & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); - - /* drivers/elog/gsmi.c */ - ret = gsmi_exec(sub_command, &reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); -} - -static void southbridge_smi_store( - const struct smm_save_state_ops *save_state_ops) -{ - u8 sub_command, ret; - void *io_smi; - uint32_t reg_ebx; - - io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (save_state_ops->get_reg(io_smi, RAX) >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = save_state_ops->get_reg(io_smi, RBX); - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - save_state_ops->set_reg(io_smi, RAX, ret); -} - static void finalize(void) { static int finalize_done; @@ -379,7 +336,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(save_state_ops); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 49e306f..3ce4ba8 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -230,27 +230,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -322,7 +301,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index e4ebffd..9464904 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -218,27 +218,6 @@ return NULL; } -static void southbridge_smi_gsmi(void) -{ - u32 *ret, *param; - u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); - - if (!io_smi) - return; - - /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); - - /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; - - /* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); -} - static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -323,7 +302,7 @@ break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) - southbridge_smi_gsmi(); + apmc_smi_gsmi(); break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/45474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93639d8d0fde2e874eb9b963c449be1b754ca63d Gerrit-Change-Number: 45474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: cpu/x86/smm: Move smmstore entry to a common place
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45475 ) Change subject: cpu/x86/smm: Move smmstore entry to a common place ...................................................................... cpu/x86/smm: Move smmstore entry to a common place Now that SMM save states are handled in a common place so can the SMMSTORE calls entry. Change-Id: Ieb8d01a2d33e9214c3df7f909dcfab49a05fffff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/smi.c M src/include/smmstore.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 10 files changed, 35 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45475/1 diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index b21423e..ba1d9e8 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -6,6 +6,7 @@ #include <smmstore.h> #include <stddef.h> #include <stdint.h> +#include <cpu/x86/save_state.h> /* * Check that the given range is legal. @@ -24,7 +25,7 @@ } /* Param is usually EBX, ret in EAX */ -uint32_t smmstore_exec(uint8_t command, void *param) +static uint32_t smmstore_exec(uint8_t command, void *param) { uint32_t ret = SMMSTORE_RET_FAILURE; @@ -76,3 +77,27 @@ return ret; } + +void apmc_smmtore_handler(void) +{ + u8 sub_command; + u16 ax; + u32 ret, param; + const int apmc_node = get_apmc_node(APM_CNT_SMMSTORE); + + if (apmc_node < 0) + return; + + /* Command and return value in EAX */ + if (get_save_state_reg(RAX, apmc_node, &ax, sizeof(ax))) + return; + + sub_command = (ax >> 8); + + /* Parameter buffer in EBX */ + if (get_save_state_reg(RBX, apmc_node, &param, sizeof(param))) + return; + + ret = smmstore_exec(sub_command, &param); + set_save_state_reg(RAX, apmc_node, &ret, sizeof(ret)); +} diff --git a/src/include/smmstore.h b/src/include/smmstore.h index ff0b720..3c50690 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -27,7 +27,7 @@ }; /* SMM responder */ -uint32_t smmstore_exec(uint8_t command, void *param); +void apmc_smmtore_handler(void); /* implementation */ int smmstore_read_region(void *buf, ssize_t *bufsize); diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 89df86f..e6be072 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -57,25 +57,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_SMMSTORE); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); -} - static void sb_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -93,7 +74,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; case APM_CNT_SMMINFO: psp_notify_smm(); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index d55c545..2163c80 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -55,25 +55,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; - - io_smi = find_save_state(APM_CNT_SMMSTORE); - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); -} - static void sb_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -91,7 +72,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index bfe933f..9348ae0 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -240,25 +240,6 @@ LPSS_ACPI_MODE_DISABLE(SPI); } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -314,7 +295,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index f6ac703..6f8cd62 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -220,25 +220,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -291,7 +272,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index ea5bf8a..a223bf5 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -267,26 +267,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { u8 reg8; @@ -330,7 +310,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 77eaad9..b629ef2 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -340,7 +340,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(save_state_ops); + apmc_smmtore_handler(); break; case APM_CNT_FINALIZE: finalize(); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 3ce4ba8..ff61c6f 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -230,26 +230,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uintptr_t reg_rbx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_rbx = (uintptr_t)io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_rbx); - io_smi->rax = ret; -} - static int mainboard_finalized = 0; static void southbridge_smi_apmc(void) @@ -305,7 +285,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9464904..a033d68 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -218,26 +218,6 @@ return NULL; } -static void southbridge_smi_store(void) -{ - u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; - - if (!io_smi) - return; - /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; - - /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; - - /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); - io_smi->rax = ret; -} - static void southbridge_smi_apmc(void) { u8 reg8; @@ -306,7 +286,7 @@ break; case APM_CNT_SMMSTORE: if (CONFIG(SMMSTORE)) - southbridge_smi_store(); + apmc_smmtore_handler(); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb8d01a2d33e9214c3df7f909dcfab49a05fffff Gerrit-Change-Number: 45475 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021