coreboot-gerrit December 2021

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Change in coreboot[master]: [WIP] drivers/intel/fsp2_0: Add FSP 2.3 support
by Werner Zeh (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Anil Kumar K, Subrata Banik, Paul Menzel, Andrey Petrov, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59324 ) Change subject: [WIP] drivers/intel/fsp2_0: Add FSP 2.3 support ...................................................................... Patch Set 20: Code-Review+1 (3 comments) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/59324/comment/56ce7fdf_9715c6ca PS14, Line 38: Features added into FSP 2.3 specification that impact coreboot are: : 1. FSP_INFO_HEADER changes : Updated SpecVersion from 0x22 to 0x23 : Updated HeaderRevision from 5 to 6 : Added ExtendedImageRevision : FSP_INFO_HEADER length changed to 0x50 : 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 > I cut short the Kconfig description and added the details in commit message Ack File src/drivers/intel/fsp2_0/header_display.c: https://review.coreboot.org/c/coreboot/+/59324/comment/06dc230b_f8339338 PS3, Line 10: ext_revision.val = 0; > Ack If we do not have some special quirks around local non-static variables are per standard not initialized and can have any value (including 0) since they are created on the stack (see http://www.open-std.org/JTC1/SC22/WG14/www/docs/n1570.pdf Section 6.7.9 clause 10). So if you have to rely on the variable having a certain value you have to initialize it. File src/drivers/intel/fsp2_0/header_display.c: https://review.coreboot.org/c/coreboot/+/59324/comment/c776661d_2b9bc72b PS14, Line 22: ((ext_revision.rev.revision << 8) | revision.rev.revision), : ((ext_revision.rev.bld_num << 8) | revision.rev.bld_num)); > Never mind. […] The value of local variables is undefined per standard. Fine with me now. -- To view, visit https://review.coreboot.org/c/coreboot/+/59324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1bd004286c785aa8a431f39d8efc69982874c1 Gerrit-Change-Number: 59324 Gerrit-PatchSet: 20 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 10 Dec 2021 05:57:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel: Add edk2-stable202111 support
by Subrata Banik (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59986 ) Change subject: vendorcode/intel: Add edk2-stable202111 support ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Can we get this in ? Thanks Jonathan -- To view, visit https://review.coreboot.org/c/coreboot/+/59986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786cc05f9a638ac6226ebc8c0eaf1dc8189a4ca4 Gerrit-Change-Number: 59986 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 10 Dec 2021 04:49:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel: Rework UDK binding Kconfig
by Subrata Banik (Code Review) 10 Dec '21

10 Dec '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59985 ) Change subject: vendorcode/intel: Rework UDK binding Kconfig ...................................................................... vendorcode/intel: Rework UDK binding Kconfig coreboot code currently supports different UDK binding as per underlying FSP requirement, example: ICL and TGL uses UDK_2017_BINDING while ADL uses UDK_202005_BINDING Kconfig. These UDK binding Kconfigs are being used to choose the correct UDK_VERSION. This patch introduces `UDK_BASE` Kconfig option so UDK_VERSION if clause don't need to add specific UDK binding Kconfig everytime with introduction of newer UDK bindings in future. Tested with BUILD_TIMELESS=1, Hatch remains identical. Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68 Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59985 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/vendorcode/intel/Kconfig 1 file changed, 9 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 6b7e495..5e75143 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -1,18 +1,25 @@ ## SPDX-License-Identifier: GPL-2.0-only +config UDK_BASE + def_bool n + config UEFI_2_4_BINDING def_bool n + select UDK_BASE config UDK_2015_BINDING def_bool n + select UDK_BASE config UDK_2017_BINDING def_bool n + select UDK_BASE config UDK_202005_BINDING def_bool n + select UDK_BASE -if (UEFI_2_4_BINDING || UDK_2015_BINDING || UDK_2017_BINDING || UDK_202005_BINDING) +if UDK_BASE config UDK_2013_VERSION int default 2013 @@ -37,4 +44,4 @@ default UDK_2013_VERSION help UEFI Development Kit version for Platform -endif # {UEFI,UDK}_BINDING +endif # UDK_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/59985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c51aa06a14f0ce541537363870ac3925b79a68 Gerrit-Change-Number: 59985 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer
by Subrata Banik (Code Review) 10 Dec '21

10 Dec '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59976 ) Change subject: mb/intel/adlrvp: Add support for external clock buffer ...................................................................... mb/intel/adlrvp: Add support for external clock buffer ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/romstage_fsp_params.c 2 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 6575685..498fbc2 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -23,12 +23,14 @@ select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION select SOC_INTEL_ALDERLAKE_PCH_P + select GEN3_EXTERNAL_CLOCK_BUFFER config BOARD_INTEL_ADLRVP_P_EXT_EC select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_INTEL_PMC select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_ALDERLAKE_PCH_P + select GEN3_EXTERNAL_CLOCK_BUFFER config BOARD_INTEL_ADLRVP_P_MCHP select BOARD_INTEL_ADLRVP_COMMON @@ -140,4 +142,20 @@ config TPM_TIS_ACPI_INTERRUPT int default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3) + +config GEN3_EXTERNAL_CLOCK_BUFFER + bool + depends on SOC_INTEL_ALDERLAKE_PCH_P + default n + help + Support external Gen-3 clock chip for ADL-P. + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer + for further distribution to platform. SRCCLKREQB[7:9] maps to internal + SRCCLKREQB[6]. If any of them asserted, SRC buffer + `CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled. + +config CLKSRC_FOR_EXTERNAL_BUFFER + depends on GEN3_EXTERNAL_CLOCK_BUFFER + int + default 6 # CLKSRC 6 endif diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 34fc04e..05d2a17 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -24,6 +24,24 @@ return spd_index; } +/* + * ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's + * 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are + * connected on the platform, an external differential buffer chip needs to be placed at + * the platform level. + * + * GEN3_EXTERNAL_CLOCK_BUFFER Kconfig is selected for ADL-P RVP (not applicable for + * ADL-M/N RVP) + * + * CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete + * buffer for further distribution to platform. + */ +static void configure_external_clksrc(FSP_M_CONFIG *m_cfg) +{ + for (unsigned int i = CONFIG_MAX_PCIE_CLOCK_SRC; i < CONFIG_MAX_PCIE_CLOCK_REQ; i++) + m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER; +} + void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg) { const struct mb_cfg *mem_config = variant_memory_params(); @@ -68,4 +86,7 @@ die("Unknown board id = 0x%x\n", board_id); break; } + + if (CONFIG(GEN3_EXTERNAL_CLOCK_BUFFER)) + configure_external_clksrc(m_cfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Gerrit-Change-Number: 59976 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add crashlog trigger on all reset toggle soc/int...
by Curtis Chen (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Curtis Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59951 ) Change subject: soc/intel/alderlake: Add crashlog trigger on all reset toggle soc/intel/common: Do not enable crashlog on all resets by default ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: > Do you mind splitting this into two commits, one for the Kconfig, and the other to enable it for ADL? I did it originally. But I abandoned it due to the request from Paul. (https://review.coreboot.org/c/coreboot/+/59952) May you align with him at first? File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/59951/comment/527ac48c_d6246e01 PS2, Line 332: def_bool n : help : Enable PMC reset crashlog record. > indent with tabs (this is the cause of the jenkins failure) […] It's followed by the above config SOC_INTEL_CRASHLOG in the same file. That's why I choose to put it here. Only ADL & TGL has the config SOC_INTEL_CRASHLOG -- To view, visit https://review.coreboot.org/c/coreboot/+/59951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ec4ff3c8a3799156de030f4556fe6ce61305139 Gerrit-Change-Number: 59951 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 10 Dec 2021 02:35:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: set up open-drain ChromeOS pins
by Rex-BC Chen (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60002 ) Change subject: mb/google/corsola: set up open-drain ChromeOS pins ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60002/comment/4b3d357c_7b6d0677 PS2, Line 7: setup > Set up Done https://review.coreboot.org/c/coreboot/+/60002/comment/8db0bb91_c97028c3 PS2, Line 10: GPIO_SAR_INT_ODL/GPIO_BT_WAKE_AP_ODL/GPIO_WIFI_INT_ODL : GPIO_DPBRDG_INT_ODL/GPIO_EDPBRDG_INT_ODL/GPIO_EC_AP_HPD_OD : GPIO_TCHPAD_INT_ODL/GPIO_TCHSCR_INT_1V8_ODL/GPIO_EC_AP_INT_ODL : GPIO_EC_IN_RW_ODL/GPIO_GSC_AP_INT_ODL/GPIO_AP_WP_ODL : GPIO_HP_INT_ODL/GPIO_PEN_EJECT_OD/GPIO_UCAM_DET_ODL > I think you don't need to list all the GPIOs (already in the code); instead you can describe what's […] Done https://review.coreboot.org/c/coreboot/+/60002/comment/d363e7a1_d6a8ae83 PS2, Line 15: > Please add the source for these settings. Done File src/mainboard/google/corsola/gpio.h: https://review.coreboot.org/c/coreboot/+/60002/comment/f231e50a_e8812d44 PS3, Line 25: #define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) > please, no space before tabs Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 10 Dec 2021 02:20:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: set up open-drain ChromeOS pins
by Rex-BC Chen (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60002 to look at the new patch set (#4). Change subject: mb/google/corsola: set up open-drain ChromeOS pins ...................................................................... mb/google/corsola: set up open-drain ChromeOS pins Set open-drain GPIOs for ChromeOS as input and high-z mode. After apply this patch, we can measure these pins from 1.0V to correct voltage (1.8V) to prevent wrong judgement of low/high. Reference document: MT8186_SoC_Pinmux_V1_1 BUG=b:209342636 TEST=measure pins voltage 1.8V on kingler board Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 --- M src/mainboard/google/corsola/bootblock.c M src/mainboard/google/corsola/chromeos.c M src/mainboard/google/corsola/gpio.h 3 files changed, 46 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60002/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: add tracker dump
by Rex-BC Chen (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59990 ) Change subject: soc/mediatek/mt8186: add tracker dump ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59990/comment/c382767d_6563ce29 PS2, Line 14: TEST=build pass > Please give an example, how to use it. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Gerrit-Change-Number: 59990 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 10 Dec 2021 02:16:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: add support for tracker version one
by Rex-BC Chen (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59989 ) Change subject: soc/mediatek: add support for tracker version one ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/common/tracker.c: https://review.coreboot.org/c/coreboot/+/59989/comment/86cfca36_10e808da PS1, Line 9: __weak void tracker_setup(void) > No weak function is needed, as it has to be implemented? It's for version one, and drivers of version one will not implement this function. I have move this weak function to patch to prevent build fail: https://review.coreboot.org/c/coreboot/+/59990 -- To view, visit https://review.coreboot.org/c/coreboot/+/59989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Gerrit-Change-Number: 59989 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 10 Dec 2021 02:16:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: set up open-drain ChromeOS pins
by build bot (Jenkins) (Code Review) 10 Dec '21

10 Dec '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60002 ) Change subject: mb/google/corsola: set up open-drain ChromeOS pins ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/corsola/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-135293): https://review.coreboot.org/c/coreboot/+/60002/comment/a92ed9be_6b38a6d2 PS3, Line 25: #define GPIO_XHCI_DONE GPIO(PERIPHERAL_EN1) please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/60002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Gerrit-Change-Number: 60002 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 10 Dec 2021 02:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2021