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Change subject: mb/google/brya/{kano,taeko}: Change reset type of CPU PCIe vGPIOs
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Can we sync taeko's change with taeko4es as well?
Thanks.
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Change subject: soc/intel/cannonlake: Hook up DPTF device to devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/system76/bonw14/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/59887/comment/e9662848_b9b24b2c
PS4, Line 72: device pci 04.0 off end # SA Thermal device
Looks like it was my mistake when upstreaming the board, forgetting the FSP config.
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Change subject: mainboard: Drop `SataMode` setting from Tiger Lake devicetrees
......................................................................
mainboard: Drop `SataMode` setting from Tiger Lake devicetrees
All Tiger Lake mainboards use the default value for the setting
`SataMode`. Thus, drop it from their devicetree.
Change-Id: I291048250bc82552fde7c71a1dcda4894a61d465
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
2 files changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59890/5
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Change subject: mainboard: Drop `SataMode` setting from Cannon Lake devicetrees
......................................................................
mainboard: Drop `SataMode` setting from Cannon Lake devicetrees
All Coffee Lake mainboards use the default value for the setting
`SataMode`. Thus, drop it from their devicetree.
Change-Id: Ibb329eb8b752c2220bb25f14fb6ae92dd8a308d6
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/google/hatch/variants/akemi/variant.c
M src/mainboard/google/hatch/variants/kindred/variant.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
4 files changed, 0 insertions(+), 4 deletions(-)
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Change subject: mainboard: Drop `SataMode` setting from Skylake devicetrees
......................................................................
mainboard: Drop `SataMode` setting from Skylake devicetrees
All Skylake mainboards use the default value for the setting `SataMode`.
Thus, drop it from their devicetree.
Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/hp/280_g2/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
16 files changed, 0 insertions(+), 16 deletions(-)
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Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60025 )
Change subject: payloads/Makefile.inc: Add warning for image built with no payload
......................................................................
payloads/Makefile.inc: Add warning for image built with no payload
Writing a coreboot image without a payload to a board's flash chip will
result in a non-bootable system, so warn the user if this is the case.
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
Change-Id: I15ae9548a45e9f566c84db41e8e171c6bc179057
---
M payloads/Makefile.inc
1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60025/1
diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
index d89b5ba..9ee893c 100644
--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -48,5 +48,16 @@
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ifeq ($(CONFIG_PAYLOAD_NONE),y)
+files_added:: warn_no_payload
+endif
+
+warn_no_payload:
+ printf "\n\t** WARNING **\n"
+ printf "coreboot has been built without a payload.\n"
+ printf "Writing a coreboot image without a payload to your board's\n"
+ printf "flash chip will result in a non-booting system.\n"
+ printf "You can use cbfstool to add a payload to the image.\n\n"
+
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
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Change subject: mainboard: Drop `SataMode` setting from Skylake devicetrees
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Should we remove the devicetree setting completely? This looks like something that should be user-co […]
This should be an user-configurable setting, right, but not sure if it should be done with CMOS or Kconfig. In my opinion CMOS.
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Change subject: mb/google/guybrush: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/psp_verstage/Kconfig:
https://review.coreboot.org/c/coreboot/+/60024/comment/b855fa17_8b844d3d
PS1, Line 10: bool "S0i3 resume versttage"
> nit: extra t
Done
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Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/guybrush: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
......................................................................
mb/google/guybrush: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will
be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this
in PSP.
BUG=b:200578885, b:202397678
BRANCH=None
TEST=Verstage runs during s0i3 resume on Nipperkin
Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/common/psp_verstage/Kconfig
2 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/60024/2
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Change subject: mb/google/guybrush: Add PSP_S0I3_RESUME_VERSTAGE Kconfig option
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/amd/common/psp_verstage/Kconfig:
https://review.coreboot.org/c/coreboot/+/60024/comment/3f8a0389_3758ae9d
PS1, Line 10: bool "S0i3 resume versttage"
nit: extra t
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