Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60472 )
Change subject: soc/intel/alderlake: Add option to make MRC log silent
......................................................................
soc/intel/alderlake: Add option to make MRC log silent
Typically, FSP-M aka MRC debug log level is default set to `3`
meaning prints all `Load, Error, Warnings & Info` Messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implemented `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless `HAVE_DEBUG_RAM_SETUP` config is enabled.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While the user selects `HAVE_DEBUG_RAM_SETUP`
config `SerialDebugMrcLevel` UPD value is overridden to '5'
aka verbose.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I21ea7324153e93ed32a7ce0f861c36c19a0d463c
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/60472/1
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 8959bf7..0eeaabd 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -312,6 +312,9 @@
static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
+ /* Set MRC debug level */
+ m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level();
+
/* Set debug probe type */
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I21ea7324153e93ed32a7ce0f861c36c19a0d463c
Gerrit-Change-Number: 60472
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60233 )
Change subject: util/cbfstool: Replace swab.h with commonlib/bsd/sysincludes.h
......................................................................
Patch Set 7: Code-Review+2
(2 comments)
File util/cbfstool/cbfs_image.c:
https://review.coreboot.org/c/coreboot/+/60233/comment/bd99fcbf_715ac377
PS6, Line 528: uint32_t type = htobe32(cur->type);
:
: /* Current entry is empty. Kepp track of it. */
: if ((type == htobe32(CBFS_TYPE_NULL)) ||
: (type == htobe32(CBFS_TYPE_DELETED))) {
> Yeah...
Feel free to fix it if you want to... a lot of this code is very old and never really gets any attention.
https://review.coreboot.org/c/coreboot/+/60233/comment/e6defdb5_03a9f5c5
PS6, Line 1031: be32toh(stage->loadaddr)
> Seems like a mistake? be64toh(stage->loadaddr) is used everywhere else in this file.
My mistake (from CB:46484), thanks for catching! Please fix it while we're here.
--
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