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Change subject: crossgcc/Makefile: Remove obsolete target build_make
......................................................................
crossgcc/Makefile: Remove obsolete target build_make
coreboot does not build gnumake anymore since commit 91fb1399
Change-Id: I0f159fc912d09ebde6ac7ba5be83933aa251f1d5
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M util/crossgcc/Makefile
1 file changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/59397/8
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59397 )
Change subject: crossgcc/Makefile: Remove obsolete target build_make
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59397/comment/19bada18_1836ac23
PS7, Line 9: commit 91fb139956bcbd5771fd7ec1e474c16122c1b547
> Please move this to the next line
Or just shorten the commit hash.
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Change subject: crossgcc/Makefile: Remove obsolete target build_make
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59397/comment/50ff054a_9e016a6a
PS7, Line 9: commit 91fb139956bcbd5771fd7ec1e474c16122c1b547
Please move this to the next line
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Change subject: soc/intel/common/cse: Add support to get CSME timestamps
......................................................................
Removed reviewer Subrata Banik.
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Change subject: soc/intel/common/cse: Add support to get CSME timestamps
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/58993/comment/e8f4324b_828d27f4
PS4, Line 440: while
> `during the last platform boot flow`
Done
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Hello build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
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Change subject: soc/intel/common/cse: Add support to get CSME timestamps
......................................................................
soc/intel/common/cse: Add support to get CSME timestamps
This command retrieves a set of early boot performance
timestamps CSME collected during the platform last boot flow
BUG=b:182575295
TEST=Verify CSME timestamps after S3 and boot.
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: Ic6f7962c49b38d458680d51ee1cd709805f73b66
---
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 166 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/58993/5
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Change subject: soc/intel/alderlake: Add option to make MRC log silent
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> > > This is what my understanding is: […]
@Nico: Address your review comment here CB:60470 and CB:60471. Please let me know if this is what you meant?
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Add option to make MRC log silent
......................................................................
soc/intel/alderlake: Add option to make MRC log silent
Typically, FSP-M aka MRC debug log level is default set to `3`
meaning prints all `Load, Error, Warnings & Info` Messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implemented `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless `HAVE_DEBUG_RAM_SETUP` config is enabled.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While the user selects `HAVE_DEBUG_RAM_SETUP`
config `SerialDebugMrcLevel` UPD value is overridden to '5'
aka verbose.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60441/3
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