coreboot-gerrit November 2021

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64)
by Arthur Heymans (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Subrata Banik, Andrey Petrov, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59744 ) Change subject: drivers/intel/fsp2_0: Add support for FSP runs in long mode (x86_64) ...................................................................... Patch Set 4: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/59744/comment/23f17663_18c6a9f9 PS4, Line 36: default y if !HAVE_EXP_X86_64_SUPPORT This depends on the platforms FSP release. Not on the possibility to build coreboot with 64bit. -- To view, visit https://review.coreboot.org/c/coreboot/+/59744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If12b63a282c660da6f57fe23b0b848e2d155853f Gerrit-Change-Number: 59744 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 15:25:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/amd/agesa/family15tn/model_15_init.c: create correct MTRR solution
by Arthur Heymans (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Michał Żygowski, Angel Pons, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53991 ) Change subject: cpu/amd/agesa/family15tn/model_15_init.c: create correct MTRR solution ...................................................................... Patch Set 3: (1 comment) File src/cpu/amd/agesa/family15tn/model_15_init.c: https://review.coreboot.org/c/coreboot/+/53991/comment/8525fc21_03b3d168 PS3, Line 39: execution > `AGESA execution`? > > I was wondering why Intel platforms don't need this. I suppose it's because AGESA is executed in-place, as opposed to post-RAM coreboot stages and blobs (refcode, FSP-S). Ramstage is not executed in place. Caching the ROM is not needed at this point. -- To view, visit https://review.coreboot.org/c/coreboot/+/53991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3efcd4bb62953cae378e725d10a4b7e240dd4251 Gerrit-Change-Number: 53991 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Nov 2021 15:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add missing PM_ACPI_* bit definitions
by Felix Held (Code Review) 30 Nov '21

30 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59588 ) Change subject: soc/amd/cezanne: add missing PM_ACPI_* bit definitions ...................................................................... soc/amd/cezanne: add missing PM_ACPI_* bit definitions This part was copied from Picasso but Cezanne has some more bits used so add the definitions now. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/include/soc/southbridge.h 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index b492088..3bba559 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -44,6 +44,7 @@ #define PM_ACPI_DECODE_STD BIT(0) #define PM_ACPI_GLOBAL_EN BIT(1) #define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_SLPBTN_EN_EN BIT(3) #define PM_ACPI_TIMER_EN_EN BIT(4) #define PM_ACPI_MASK_ARB_DIS BIT(6) #define PM_ACPI_BIOS_RLS BIT(7) @@ -51,11 +52,26 @@ #define PM_ACPI_REDUCED_HW_EN BIT(9) #define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10) #define PM_ACPI_S5_LPC_PIN_MODE BIT(11) +#define PM_ACPI_LPC_RST_DIS BIT(12) +#define PM_ACPI_SEL_PWRGD_PAD BIT(13) +#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14) +#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15) +#define PM_ACPI_SW_S5PWRMUX BIT(16) +#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17) +#define PM_ACPI_EN_SYNC_FLOOD BIT(18) +#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19) +#define PM_ACPI_EN_DF_INTRWAKE BIT(20) +#define PM_ACPI_MASK_USB_S5_RST BIT(21) +#define PM_ACPI_USE_RSMU_RESET BIT(22) +#define PM_ACPI_RST_USB_S5 BIT(23) #define PM_ACPI_BLOCK_PCIE_PME BIT(24) #define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26) #define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_RTC_WAKE_EN BIT(29) +#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30) +#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31) #define PM_SPI_PAD_PU_PD 0x90 #define PM_ESPI_CS_USE_DATA2 BIT(16) #define PM_LPC_GATING 0xec -- To view, visit https://review.coreboot.org/c/coreboot/+/59588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd128dca1ec30e7c70501c0e64482159be71cc7b Gerrit-Change-Number: 59588 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
by Felix Held (Code Review) 30 Nov '21

30 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59674 ) Change subject: soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs ...................................................................... soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/block/include/amdblocks/lpc.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index c5f3c78..173cbd1 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -10,6 +10,8 @@ #define LEGACY_DMA_EN BIT(2) #define VW_ROM_SHARING_EN BIT(3) #define EXT_ROM_SHARING_EN BIT(4) +#define SPI_ROM_BIOS_SEMAPHORE BIT(5) +#define SPI_ROM_EC_SEMAPHORE BIT(6) #define LPC_IO_PORT_DECODE_ENABLE 0x44 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/59674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Gerrit-Change-Number: 59674 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
by Mark Hsieh (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Marco Chen, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59580 ) Change subject: mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Hi Tim, Please help to review it, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7 Gerrit-Change-Number: 59580 Gerrit-PatchSet: 7 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Nov 2021 14:28:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Select number of I/O for ADL-N
by Sridhar Siricilla (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Krishna P Bhat D, Usha P, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 ) Change subject: soc/intel/alderlake: Select number of I/O for ADL-N ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/59752/comment/f985af61_46036137 PS1, Line 177: SOC_INTEL_ALDERLAKE_PCH_N ADL-N support max of 5 PCIE ports (upto 9 PCIe lanes). Please check once. -- To view, visit https://review.coreboot.org/c/coreboot/+/59752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904 Gerrit-Change-Number: 59752 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 14:23:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/i440bx: Use PARALLEL_MP
by Arthur Heymans (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Keith Hui, Branden Waldner, Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59693 ) Change subject: nb/intel/i440bx: Use PARALLEL_MP ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59693/comment/75683ff2_41c2f57f PS4, Line 10: always > This is not true, see `src/mainboard/asus/p2b/Kconfig`. Although the CPUs only have one core, there are mainboards with two CPU sockets. It took me some time to understand the code but it looks like previously there were 2 ways of adding more 'cores/APIC' to the devicetree linked list and have the lapic init code do its thing: Have a scan_bus operation for the cpu bus (see northbridge/amd/agesa/fam14/northbridge.c l816) or have it somewhere inside the cpu init code ( cpu/intel/model_f2x_init.c initel_sibling_init()). The i440bx code seems to have neither so I don't think multiple CPUs worked on that platform. File src/northbridge/intel/i440bx/northbridge.c: https://review.coreboot.org/c/coreboot/+/59693/comment/b9179b00_cfa3c741 PS4, Line 76: 1 > Not true for mainboards with two CPU sockets, see comment in commit message. > > I'm not sure if there's a generic procedure to detect which CPU sockets are populated. In any case, returning `CONFIG_MAX_CPUS` would at least be slightly more correct. I don't really know it either... It looks like multi socket CPU would be a new feature on this board anyway so maybe a TODO comment here fits the job? If things regress it's likely not hard to fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/59693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Gerrit-Change-Number: 59693 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Nov 2021 14:11:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/hda: Remove the weak function
by Felix Held (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58772 ) Change subject: amd/hda: Remove the weak function ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: hm, here i would introduce a kconfig option SOC_AMD_COMMON_BLOCK_HDA_HAS_SOC_QUIRKS and only call hda_soc_ssdt_quirks when that option is set and then set that option in the stoneyridge Konfig. that would avoid having to add an empty function for quirks that are only needed on one SoC family to all SoC code. for the i2c thing the situation was different and there the additional function is only empty on stoneyridge, but needed on all other platforms -- To view, visit https://review.coreboot.org/c/coreboot/+/58772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b089b9fe4742b29686198f20fc7c1a2dae6f015 Gerrit-Change-Number: 58772 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 30 Nov 2021 13:57:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/oprom: Add support for x86_64 mode
by Subrata Banik (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59753 ) Change subject: device/oprom: Add support for x86_64 mode ...................................................................... Patch Set 1: (1 comment) File src/device/oprom/realmode/x86.c: https://review.coreboot.org/c/coreboot/+/59753/comment/1c83789d_6d2801da PS1, Line 97: X86_EIP not sure if this is the right way to fix the compilation issue as X86_RIP doesn't exist but we still need to have .rip instead .eip for x86_64. -- To view, visit https://review.coreboot.org/c/coreboot/+/59753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0284bb92521de2a8acc55897ea4eb2a5c5b56c7 Gerrit-Change-Number: 59753 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph Gerrit-Comment-Date: Tue, 30 Nov 2021 13:42:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add template for deprecation notices
by Name of user not set (Code Review) 30 Nov '21

30 Nov '21

Attention is currently required from: Patrick Georgi, Martin Roth. awokd(a)danwin1210.me has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59677 ) Change subject: Documentation: Add template for deprecation notices ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2cc4f799804c7d56db572823246c487cd19a726 Gerrit-Change-Number: 59677 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: awokd(a)danwin1210.me Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 30 Nov 2021 13:22:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021