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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mainboard/dell: Add Latitude E7440
by Pablo Stebler (Code Review) 20 Apr '22

20 Apr '22

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46540 ) Change subject: mainboard/dell: Add Latitude E7440 ...................................................................... mainboard/dell: Add Latitude E7440 Based on autoport output. Untested for now. Signed-off-by: Pablo Stebler <pablo(a)stebler.xyz> Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e --- M src/mainboard/dell/latitude_e7x40/Kconfig M src/mainboard/dell/latitude_e7x40/Kconfig.name A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb 6 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46540/1 diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig b/src/mainboard/dell/latitude_e7x40/Kconfig index 05ed643..9b9bae7 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig +++ b/src/mainboard/dell/latitude_e7x40/Kconfig @@ -23,10 +23,12 @@ config VARIANT_DIR string default "latitude_e7240" if BOARD_DELL_LATITUDE_E7240 + default "latitude_e7440" if BOARD_DELL_LATITUDE_E7440 config MAINBOARD_PART_NUMBER string default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 + default "Latitude E7440" if BOARD_DELL_LATITUDE_E7440 config VGA_BIOS_FILE string diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig.name b/src/mainboard/dell/latitude_e7x40/Kconfig.name index 5eefdf7..4532758 100644 --- a/src/mainboard/dell/latitude_e7x40/Kconfig.name +++ b/src/mainboard/dell/latitude_e7x40/Kconfig.name @@ -4,3 +4,8 @@ bool "Latitude E7240" select BOARD_DELL_LATITUDE_E7x40 + +config BOARD_DELL_LATITUDE_E7440 + bool "Latitude E7440" + + select BOARD_DELL_LATITUDE_E7x40 diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt new file mode 100644 index 0000000..6d6a545 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/board_info.txt @@ -0,0 +1 @@ +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c new file mode 100644 index 0000000..89531a3 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/gpio.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = LP_GPIO_NATIVE, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c new file mode 100644 index 0000000..e358006 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805cb, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805cb), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb new file mode 100644 index 0000000..cc31dc8 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7440/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + device domain 0x0 on + subsystemid 0x1028 0x05cb inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9459d8dac9552529fc90633eaadd89f5118b237e Gerrit-Change-Number: 46540 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: lenovo/g505s: enable device 14.5 FCH USB OHCI Controller
by Mike Banon (Code Review) 20 Apr '22

20 Apr '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47916 ) Change subject: lenovo/g505s: enable device 14.5 FCH USB OHCI Controller ...................................................................... lenovo/g505s: enable device 14.5 FCH USB OHCI Controller I enabled this device hoping to get a webcam working. It still doesn't but there aren't any downsides. For a coreboot master to be a slightly better foundation for getting it working eventually, please merge. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I37547eb951a0afc5da5a12618769975d7071e283 --- M src/mainboard/lenovo/g505s/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47916/1 diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 4b4df36..fba2300 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -41,7 +41,7 @@ end end device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 + device pci 14.5 on end # FCH USB OHCI Controller device pci 14.6 off end # Gec device pci 14.7 off end # SD device pci 15.0 off end # PCIe 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/47916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37547eb951a0afc5da5a12618769975d7071e283 Gerrit-Change-Number: 47916 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Revert "util: Remove 'getpir' and 'mptable' tools"
by Mike Banon (Code Review) 20 Apr '22

20 Apr '22

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Alexandru Gagniuc, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48322 to review the following change. Change subject: Revert "util: Remove 'getpir' and 'mptable' tools" ...................................................................... Revert "util: Remove 'getpir' and 'mptable' tools" This reverts commit 6c90f3334e65ff4b0ff4900df77bc33d53beb677. Reason for revert: Although the output of these tools is indeed far from being perfect, still it could be used as a nice starting point. Change-Id: Ieff7673387ae9275b8271f4a483926b774697a8d --- A util/getpir/Makefile A util/getpir/README A util/getpir/checkpir.c A util/getpir/checksum.c A util/getpir/checksum.h A util/getpir/code_gen.c A util/getpir/code_gen.h A util/getpir/getpir.c A util/getpir/pirq_routing.h A util/mptable/Makefile A util/mptable/mptable.c 11 files changed, 1,708 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48322/1 diff --git a/util/getpir/Makefile b/util/getpir/Makefile new file mode 100644 index 0000000..94270f5 --- /dev/null +++ b/util/getpir/Makefile @@ -0,0 +1,24 @@ +# +# +# + +CC=gcc +CFLAGS=-O2 -D_GNU_SOURCE -DGETPIR -Wall + +all: getpir + +getpir: getpir.o checksum.o code_gen.o + $(CC) $(CFLAGS) -o getpir $^ + +checkpir: checkpir.c checksum.o irq_tables.o + $(CC) $(CFLAGS) -o checkpir $^ + +irq_tables.c: getpir + ./getpir + +clean: + rm -f getpir checkpir *.o *~ + +distclean: clean + rm -f irq_tables.o irq_tables.c + diff --git a/util/getpir/README b/util/getpir/README new file mode 100644 index 0000000..6514585 --- /dev/null +++ b/util/getpir/README @@ -0,0 +1,30 @@ +ABOUT: + +This utility will help to create irq_table.c file, that is very hard to create +manually, specialy when you are testing new motherboards, changing your +hardware often, placing new cards, etc.. + +USAGE: + +Steps +1. make distclean; +2. make getpir +3. ./getpir + + Will dump irq table to the file called irq_tables.c, ready to use with + coreboot. Just move the file to corresponding place in the coreboot tree. + + +4. CHECKING CUSTOM irq_tables.c: + + make checkpir + ./checkpir + + checkpir.c Will verify the irq_tables.c, currently it only checks the + checksum. In case of wrong checksum, a good value is proposed, so you can + edit irq_tables.c manualy and replace checksum. + + +Do not run make checkpir and ./checkpir directly because it needs to be linked +to irq_table.o first. + diff --git a/util/getpir/checkpir.c b/util/getpir/checkpir.c new file mode 100644 index 0000000..c9703c6 --- /dev/null +++ b/util/getpir/checkpir.c @@ -0,0 +1,31 @@ +/* checkpir.c : This software is released under GPL + * For coreboot use only + * Aug 26 2001 , Nikolai Vladychevski, <niko(a)isl.net.mx> + */ + +#include <stdio.h> +#include "pirq_routing.h" +#include "checksum.h" + +struct irq_routing_table *rt; + +int main(void) +{ + uint8_t sum, newsum; + + rt = (struct irq_routing_table *) &intel_irq_routing_table; + sum = calc_checksum(rt); + + printf("Validating checksum, file: irq_tables.c that was in ./ at compile time...\n"); + printf("(no other tests are done)\n"); + + if (!sum) { + printf("Checksum for IRQ Routing table is ok. You can use irq_tables.c in coreboot now.\n"); + } else { + newsum = rt->checksum - sum; + printf("BAD CHECKSUM for IRQ Routing table !!!!\n"); + printf("If you want to make it valid, change the checksum to: %#x\n", + newsum); + } + return 0; +} diff --git a/util/getpir/checksum.c b/util/getpir/checksum.c new file mode 100644 index 0000000..bcf3425 --- /dev/null +++ b/util/getpir/checksum.c @@ -0,0 +1,13 @@ +#include "pirq_routing.h" +#include "checksum.h" + +int calc_checksum(struct irq_routing_table *rt) +{ + long i; + uint8_t *addr, sum = 0; + + addr = (uint8_t *) rt; + for (i = 0; i < rt->size; i++) + sum += addr[i]; + return (sum); +} diff --git a/util/getpir/checksum.h b/util/getpir/checksum.h new file mode 100644 index 0000000..2acc433 --- /dev/null +++ b/util/getpir/checksum.h @@ -0,0 +1,6 @@ +#ifndef __CHECKSUM_H__ +#define __CHECKSUM_H__ + +int calc_checksum(struct irq_routing_table *rt); + +#endif /* __CHECKSUM_H__ */ diff --git a/util/getpir/code_gen.c b/util/getpir/code_gen.c new file mode 100644 index 0000000..d15715c --- /dev/null +++ b/util/getpir/code_gen.c @@ -0,0 +1,88 @@ +#include <stdio.h> +#include <stdlib.h> +#include "pirq_routing.h" + +static char *preamble[] = { + + "/*\n", + " * This file is part of the coreboot project.\n", + " *\n", + " * Copyright (C) 200x TODO <TODO@TODO>\n", + " *\n", + " * This program is free software; you can redistribute it and/or modify\n", + " * it under the terms of the GNU General Public License as published by\n", + " * the Free Software Foundation; either version 2 of the License, or\n", + " * (at your option) any later version.\n", + " *\n", + " * This program is distributed in the hope that it will be useful,\n", + " * but WITHOUT ANY WARRANTY; without even the implied warranty of\n", + " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n", + " * GNU General Public License for more details.\n", + " *\n", + " * You should have received a copy of the GNU General Public License\n", + " * along with this program; if not, write to the Free Software\n", + " * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\n", + " */\n\n", + "#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */\n", + "#include \"pirq_routing.h\" /* TODO: Drop this when copying to coreboot. */\n", + "#else /* TODO: Drop this when copying to coreboot. */\n" + "#include <arch/pirq_routing.h>\n", + "#endif /* TODO: Drop this when copying to coreboot. */\n\n" + "const struct irq_routing_table intel_irq_routing_table = {\n", + "\tPIRQ_SIGNATURE, /* u32 signature */\n", + "\tPIRQ_VERSION, /* u16 version */\n", + 0 +}; + +void code_gen(char *filename, struct irq_routing_table *rt) +{ + char **code = preamble; + struct irq_info *se_arr = (struct irq_info *) ((char *) rt + 32); + int i, ts = (rt->size - 32) / 16; + FILE *fpir; + + if ((fpir = fopen(filename, "w")) == NULL) { + printf("Failed creating file!\n"); + exit(2); + } + + while (*code) + fprintf(fpir, "%s", *code++); + + fprintf(fpir, "\t32 + 16 * %d, /* Max. number of devices on the bus */\n", + ts); + fprintf(fpir, "\t0x%02x, /* Interrupt router bus */\n", + rt->rtr_bus); + fprintf(fpir, "\t(0x%02x << 3) | 0x%01x, /* Interrupt router dev */\n", + rt->rtr_devfn >> 3, rt->rtr_devfn & 7); + fprintf(fpir, "\t%#x, /* IRQs devoted exclusively to PCI usage */\n", + rt->exclusive_irqs); + fprintf(fpir, "\t%#x, /* Vendor */\n", rt->rtr_vendor); + fprintf(fpir, "\t%#x, /* Device */\n", rt->rtr_device); + fprintf(fpir, "\t%#x, /* Miniport */\n", + rt->miniport_data); + fprintf(fpir, "\t{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */\n"); + fprintf(fpir, "\t%#x, /* Checksum (has to be set to some value that\n * would give 0 after the sum of all bytes\n * for this structure (including checksum).\n */\n", + rt->checksum); + fprintf(fpir, "\t{\n"); + fprintf(fpir, "\t\t/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */\n"); + for (i = 0; i < ts; i++) { + fprintf(fpir, "\t\t{0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", + (se_arr+i)->bus, (se_arr+i)->devfn >> 3, + (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, + (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link, + (se_arr+i)->irq[1].bitmap, (se_arr+i)->irq[2].link, + (se_arr+i)->irq[2].bitmap, (se_arr+i)->irq[3].link, + (se_arr+i)->irq[3].bitmap, (se_arr+i)->slot, + (se_arr+i)->rfu); + } + fprintf(fpir, "\t}\n"); + fprintf(fpir, "};\n"); + + fprintf(fpir, "\nunsigned long write_pirq_routing_table(unsigned long addr)\n"); + fprintf(fpir, "{\n"); + fprintf(fpir, "\treturn copy_pirq_routing_table(addr);\n"); + fprintf(fpir, "}\n"); + + fclose(fpir); +} diff --git a/util/getpir/code_gen.h b/util/getpir/code_gen.h new file mode 100644 index 0000000..93bdaec --- /dev/null +++ b/util/getpir/code_gen.h @@ -0,0 +1,6 @@ +#ifndef __CODE_GEN_H__ +#define __CODE_GEN_H__ + +void code_gen(char *filename, struct irq_routing_table *rt); + +#endif /* __CODE_GEN_H__ */ diff --git a/util/getpir/getpir.c b/util/getpir/getpir.c new file mode 100644 index 0000000..9853d7c --- /dev/null +++ b/util/getpir/getpir.c @@ -0,0 +1,189 @@ +/* getpir.c : This software is released under GPL + * For coreboot use only + * Aug 26 2001 , Nikolai Vladychevski, <niko(a)isl.net.mx> + * 2007.04.09 Jeremy Jackson <jerj(a)coplanar.net> + * updated for amd64 and general 64 bit portability + * 2010.04.24 Marc Bertens <mbertens(a)xs4all.nl> + * Added functionality to read a image file for checking the checksum of the PIR + */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> + +#include "pirq_routing.h" +#include "checksum.h" +#include "code_gen.h" + +#if defined (__sun) && (defined(__i386) || defined(__amd64)) +# define MEM_DEV "/dev/xsvc" +#else +# define MEM_DEV "/dev/mem" +#endif + +/** + * The probe_table() is now called with the pointer to the memory, + * this is to handle both the assessing memory and a file. + * + * This function now dumps the table found to the stdout, with + * descriptions, it is special handy when building a PIRQ table + * for a board to check the checksum. + */ +static struct irq_routing_table *probe_table(char* ptr) +{ + /** + * Signature to search for $PIR<2-byte-version> + * + * this is to be sure that we find the correct table. + */ + char signature[] = "$PIR\x00\x01"; + /** cast the pointer */ + struct irq_routing_table *rt = (struct irq_routing_table *)ptr; + int size = 16; + int checksum_result; + do { + /** find the PIRQ table */ + rt = (struct irq_routing_table *) memmem(ptr + size, 16, signature, 6); + if (rt != NULL) { + /** found the table */ + int i, ts = (rt->size - 32) / 16; + struct irq_info *se_arr; + se_arr = (struct irq_info *) ((char *) rt + 32); + /** Dump the table information to the stdout */ + printf("Found PCI IRQ routing table signature at %p.\n", (void *) ((char *) rt - ptr + 0xf0000)); + printf("SIGNATURE = %s\n", (char*)&rt->signature); + printf("VERSION = %04x\n", rt->version); + printf("SIZE = %i\n", rt->size); + printf("MAX_DEVICES_ON_BUS = 32 + 16 * %d\n", ts); + printf("INT_ROUTER_BUS = 0x%02x\n", rt->rtr_bus); + printf("INT_ROUTER DEVICE = (0x%02x << 3) | 0x%01x\n", rt->rtr_devfn >> 3, rt->rtr_devfn & 7); + printf("IRQ_DEVOTED_TO_PCI = %#x\n", rt->exclusive_irqs); + printf("VENDOR = %#x\n", rt->rtr_vendor); + printf("DEVICE = %#x\n", rt->rtr_device); + printf("MINIPORT = %#x\n", rt->miniport_data); + printf("CHECKSUM = %#x\n", rt->checksum); + printf("\tbus , dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu\n"); + for (i = 0; i < ts; i++) { + printf("\t0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", + (se_arr+i)->bus, (se_arr+i)->devfn >> 3, + (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, + (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link, + (se_arr+i)->irq[1].bitmap, (se_arr+i)->irq[2].link, + (se_arr+i)->irq[2].bitmap, (se_arr+i)->irq[3].link, + (se_arr+i)->irq[3].bitmap, (se_arr+i)->slot, + (se_arr+i)->rfu); + } + /** A table should not be over 0x400 bytes */ + if (rt->size > 0x400) { + return NULL; + } + printf("Validating...\n"); + /** Calculate the checksum value */ + checksum_result = calc_checksum(rt); + /** Show the calculatedchecksum value */ + printf("CHECKSUM = %#x\n", 0x100-((checksum_result - rt->checksum) & 0xFF)); + /** and the result of the calculation */ + if (!checksum_result) { + printf("checksum is ok.\n"); + break; + } else { + printf("checksum is wrong.\n"); + } + } + size += 16; + } while (size < 0xFFFF); + if (size >= 0xFFFF) { + /** When the functions comes here there is no PIRQ table found. */ + printf("No PCI IRQ routing table signature found.\n"); + return NULL; + } + + return rt; +} + +int main(int argc, char* argv[]) +{ + char* ptr; + int fd_mem = -1; + struct irq_routing_table* rt = NULL; + void* bios_image = NULL; + if ( argc > 1 ) + { + /** there a paramater passed to the program, assume that it is a menory file */ + printf("Opening memory image file '%s'\n", argv[1]); + /** Open the file */ + fd_mem = open(argv[1], O_RDONLY); + if (fd_mem > 0) { + /** get tyhe size of the file */ + int file_size = lseek(fd_mem, 0, SEEK_END); + printf("Memory image '%i'\n", file_size); + /** get a memory block for it. */ + bios_image = malloc(file_size); + if (bios_image) { + /** Fill the created buffer */ + lseek(fd_mem, 0, SEEK_SET); + read(fd_mem, bios_image, file_size); + /** set the pointer for the probe function */ + ptr = (char*)bios_image; + } else { + /* no memory available ? */ + perror("Failed to open imagefile\n"); + return (-3); + } + } else { + /** An error occourd, just exit with a message */ + perror("Failed to open imagefile"); + return (-2); + } + } else { + /** No paramaters means that the program will access the system memory */ + printf("Accessing memory\n"); + if (getuid()) { + /** i'm not root message !!!! */ + fprintf(stderr, "Run me as root, I need access to " MEM_DEV ".\n"); + } + /** open the system memory */ + fd_mem = open(MEM_DEV, O_RDONLY); + if (fd_mem < 0) { + /** could not open the system memory, exit with a message */ + perror("Could not open " MEM_DEV ":"); + exit(1); + } + printf("Probing PIRQ table in memory.\n"); + ptr = mmap(0, 0x10000, PROT_READ, MAP_SHARED, fd_mem, (off_t)0xf0000); + if (ptr == MAP_FAILED) { + /** could not map the system memory, exit with a message */ + perror("Mapping system memory failed: "); + close(fd_mem); + return (1); + } + } + if (ptr) { + /** now do the actual probe function */ + rt = probe_table(ptr); + if (rt != NULL && bios_image == NULL) { + /** when probing system memory we write the 'irq_tables.c' code file */ + printf("Creating irq_tables.c ...\n"); + code_gen("irq_tables.c", rt); + printf("Done, you can move the file to the coreboot tree now.\n"); + } + } else { + printf("invalid memory pointer\n"); + } + if (bios_image) { + /** when we are reading from a file the memory must be released */ + free(bios_image); + } else { + /** when reading from the system memory, it must be unmapped */ + munmap(ptr, 0x10000); + } + /** Close the file handle */ + close(fd_mem); + /** return 0 as OK ) */ + return 0; +} diff --git a/util/getpir/pirq_routing.h b/util/getpir/pirq_routing.h new file mode 100644 index 0000000..88adc21 --- /dev/null +++ b/util/getpir/pirq_routing.h @@ -0,0 +1,55 @@ +#ifndef ARCH_PIRQ_ROUTING_H +#define ARCH_PIRQ_ROUTING_H + +#include <stdint.h> + +#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) +#define PIRQ_VERSION 0x0100 + +struct irq_info { + uint8_t bus, devfn; /* Bus, device and function */ + struct { + uint8_t link; /* IRQ line ID, chipset dependent, 0=not routed */ + uint16_t bitmap; /* Available IRQs */ + } __attribute__((packed)) irq[4]; + uint8_t slot; /* Slot number, 0=onboard */ + uint8_t rfu; +} __attribute__((packed)); + +#if defined(CONFIG_IRQ_SLOT_COUNT) +#define IRQ_SLOTS_COUNT CONFIG_IRQ_SLOT_COUNT +#elif (__GNUC__ < 3) +#define IRQ_SLOTS_COUNT 1 +#else +#define IRQ_SLOTS_COUNT +#endif + +struct irq_routing_table { + uint32_t signature; /* PIRQ_SIGNATURE should be here */ + uint16_t version; /* PIRQ_VERSION */ + uint16_t size; /* Table size in bytes */ + uint8_t rtr_bus, rtr_devfn; /* Where the interrupt router lies */ + uint16_t exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ + uint16_t rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */ + uint32_t miniport_data; /* Miniport data */ + uint8_t rfu[11]; + uint8_t checksum; /* Modulo 256 checksum must give zero */ + struct irq_info slots[IRQ_SLOTS_COUNT]; +} __attribute__((packed)); + +extern const struct irq_routing_table intel_irq_routing_table; + +#ifdef GETPIR +#define copy_pirq_routing_table(start) (start) +unsigned long write_pirq_routing_table(unsigned long start); +#else +#if CONFIG_HAVE_PIRQ_TABLE==1 +unsigned long copy_pirq_routing_table(unsigned long start); +unsigned long write_pirq_routing_table(unsigned long start); +#else +#define copy_pirq_routing_table(start) (start) +#define write_pirq_routing_table(start) (start) +#endif +#endif + +#endif /* ARCH_PIRQ_ROUTING_H */ diff --git a/util/mptable/Makefile b/util/mptable/Makefile new file mode 100644 index 0000000..f88367e --- /dev/null +++ b/util/mptable/Makefile @@ -0,0 +1,8 @@ +CC=gcc +CFLAGS=-O2 -Wall -Wextra -Wshadow -Wno-sign-compare + +mptable: mptable.c + $(CC) $(CFLAGS) -o $@ $< + +clean: + rm -f mptable diff --git a/util/mptable/mptable.c b/util/mptable/mptable.c new file mode 100644 index 0000000..5b8a59d --- /dev/null +++ b/util/mptable/mptable.c @@ -0,0 +1,1258 @@ +/* + * Copyright (c) 1996, by Steve Passe + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. The name of the developer may NOT be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * mptable.c + */ + +#define VMAJOR 2 +#define VMINOR 0 +#define VDELTA 15 + +/* + * this will cause the raw mp table to be dumped to /tmp/mpdump + * +#define RAW_DUMP + */ + +#define MP_SIG 0x5f504d5f /* _MP_ */ +#define EXTENDED_PROCESSING_READY +#define OEM_PROCESSING_READY_NOT + +#include <sys/types.h> +#include <err.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <stdint.h> + +#define ARRAY_SIZE(_x) (sizeof(_x) / sizeof(_x[0])) +#define SEP_LINE \ +"\n-------------------------------------------------------------------------------\n" + +#define SEP_LINE2 \ +"\n===============================================================================\n" + +/* EBDA is @ 40:0e in real-mode terms */ +#define EBDA_POINTER 0x040e /* location of EBDA pointer */ + +/* CMOS 'top of mem' is @ 40:13 in real-mode terms */ +#define TOPOFMEM_POINTER 0x0413 /* BIOS: base memory size */ + +#define DEFAULT_TOPOFMEM 0xa0000 + +#define BIOS_BASE 0xf0000 +#define BIOS_BASE2 0xe0000 +#define BIOS_SIZE 0x10000 +#define ONE_KBYTE 1024 + +#define GROPE_AREA1 0x80000 +#define GROPE_AREA2 0x90000 +#define GROPE_SIZE 0x10000 + +#define PROCENTRY_FLAG_EN 0x01 +#define PROCENTRY_FLAG_BP 0x02 +#define IOAPICENTRY_FLAG_EN 0x01 + +#define MAXPNSTR 132 + +#define COREBOOT_MP_TABLE 0 + +enum busTypes { + CBUS = 1, + CBUSII = 2, + EISA = 3, + ISA = 6, + PCI = 13, + XPRESS = 18, + MAX_BUSTYPE = 18, + UNKNOWN_BUSTYPE = 0xff +}; + +typedef struct BUSTYPENAME { + uint8_t type; + char name[7]; +} busTypeName; + +static busTypeName busTypeTable[] = { + {CBUS, "CBUS"}, + {CBUSII, "CBUSII"}, + {EISA, "EISA"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {ISA, "ISA"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {PCI, "PCI"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"}, + {UNKNOWN_BUSTYPE, "---"} +}; + +char *whereStrings[] = { + "Extended BIOS Data Area", + "BIOS top of memory", + "Default top of memory", + "BIOS", + "Extended BIOS", + "GROPE AREA #1", + "GROPE AREA #2" +}; + +typedef struct TABLE_ENTRY { + uint8_t type; + uint8_t length; + char name[32]; +} tableEntry; + +tableEntry basetableEntryTypes[] = { + {0, 20, "Processor"}, + {1, 8, "Bus"}, + {2, 8, "I/O APIC"}, + {3, 8, "I/O INT"}, + {4, 8, "Local INT"} +}; + +tableEntry extendedtableEntryTypes[] = { + {128, 20, "System Address Space"}, + {129, 8, "Bus Heirarchy"}, + {130, 8, "Compatibility Bus Address"} +}; + +/* MP Floating Pointer Structure */ +typedef struct MPFPS { + uint8_t signature[4]; + uint32_t pap; + uint8_t length; + uint8_t spec_rev; + uint8_t checksum; + uint8_t mpfb1; + uint8_t mpfb2; + uint8_t mpfb3; + uint8_t mpfb4; + uint8_t mpfb5; +} mpfps_t; + +/* MP Configuration Table Header */ +typedef struct MPCTH { + uint8_t signature[4]; + uint16_t base_table_length; + uint8_t spec_rev; + uint8_t checksum; + uint8_t oem_id[8]; + uint8_t product_id[12]; + uint32_t oem_table_pointer; + uint16_t oem_table_size; + uint16_t entry_count; + uint32_t apic_address; + uint16_t extended_table_length; + uint8_t extended_table_checksum; + uint8_t reserved; +} mpcth_t; + +typedef struct PROCENTRY { + uint8_t type; + uint8_t apicID; + uint8_t apicVersion; + uint8_t cpuFlags; + uint32_t cpuSignature; + uint32_t featureFlags; + uint32_t reserved1; + uint32_t reserved2; +} ProcEntry; + +typedef struct BUSENTRY { + uint8_t type; + uint8_t busID; + uint8_t busType[6]; +} BusEntry; + +typedef struct IOAPICENTRY { + uint8_t type; + uint8_t apicID; + uint8_t apicVersion; + uint8_t apicFlags; + uint32_t apicAddress; +} IOApicEntry; + +typedef struct INTENTRY { + uint8_t type; + uint8_t intType; + uint16_t intFlags; + uint8_t srcBusID; + uint8_t srcBusIRQ; + uint8_t dstApicID; + uint8_t dstApicINT; +} IntEntry; + +/* + * extended entry type structures + */ + +typedef struct SASENTRY { + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t addressType; + uint64_t addressBase; + uint64_t addressLength; +} SasEntry; + +typedef struct BHDENTRY { + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t busInfo; + uint8_t busParent; + uint8_t reserved[3]; +} BhdEntry; + +typedef struct CBASMENTRY { + uint8_t type; + uint8_t length; + uint8_t busID; + uint8_t addressMod; + uint32_t predefinedRange; +} CbasmEntry; + +typedef uint32_t vm_offset_t; + +static void apic_probe(vm_offset_t * paddr, int *where); + +static void MPConfigDefault(int featureByte); + +static void MPFloatingPointer(vm_offset_t paddr, int where, mpfps_t * mpfps); +static void MPConfigTableHeader(uint32_t pap); + +static int readType(void); +static void seekEntry(vm_offset_t addr); +static void readEntry(void *entry, int size); + +static void processorEntry(void); +static void busEntry(void); +static void ioApicEntry(void); +static void intEntry(void); +static void lintEntry(void); + +static void sasEntry(void); +static void bhdEntry(void); +static void cbasmEntry(void); + +static void doOptionList(void); +static void doDmesg(void); +static void pnstr(uint8_t * s, int c); + +/* global data */ +int pfd; /* physical /dev/mem fd */ + +int busses[32]; +int apics[16]; + +int ncpu; +int nbus; +int napic; +int nintr; + +int dmesg = 0; +int grope = 0; +int verbose = 0; +int noisy = 0; +/* preamble to the mptable. This is fixed for all coreboots */ + +char *preamble[] = { + "#include <console/console.h>", + "#include <arch/smp/mpspec.h>", + "#include <arch/ioapic.h>", + "#include <device/pci.h>", + "#include <string.h>", + "#include <stdint.h>", + "", + "#define INTA 0x00", + "#define INTB 0x01", + "#define INTC 0x02", + "#define INTD 0x03", + "", + "static void *smp_write_config_table(void *v)", + "{", + " struct mp_config_table *mc;", + "", + " mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);", + "", + " mptable_init(mc, \"TODO \", LOCAL_APIC_ADDR);", + "", + " smp_write_processors(mc);", + "", + 0 +}; + +char *postamble[] = { + " /* Compute the checksums. */", + " mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);", + " mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);", + " printk(BIOS_DEBUG, \"Wrote the mp table end at: %p - %p\\n\",", + " mc, smp_next_mpe_entry(mc));", + " return smp_next_mpe_entry(mc);", + "}", + "", + "unsigned long write_smp_table(unsigned long addr)", + "{", + " void *v;", + " v = smp_write_floating_table(addr);", + " return (unsigned long)smp_write_config_table(v);", + "}", + 0 +}; + +static void usage(void) +{ + fprintf(stderr, + "usage: mptable [-dmesg] [-verbose] [-grope] [-help]\n"); + exit(0); +} + +void write_code(char **code) +{ + while (*code) + printf("%s\n", *code++); +} + +/* + * + */ +int main(int argc, char *argv[]) +{ + vm_offset_t paddr; + int where; + mpfps_t mpfps; + int defaultConfig; + + /* announce ourselves */ + + if (verbose) + puts(SEP_LINE2); + + printf("/* generated by MPTable, version %d.%d.%d*/\n", VMAJOR, VMINOR, + VDELTA); + printf("/* as modified by RGM for coreboot */\n"); + write_code(preamble); + + /* Ron hates getopt() */ + + for (argc--, argv++; argc; argc--, argv++) { + if (strcmp(argv[0], "-dmesg") == 0) { + dmesg = 1; + } else if (strcmp(argv[0], "-help") == 0) { + usage(); + } else if (strcmp(argv[0], "-grope") == 0) { + grope = 1; + } else if (strcmp(argv[0], "-verbose") == 0) + verbose = 1; + else if (strcmp(argv[0], "-noisy") == 0) + noisy = 1; + else + usage(); + } + + /* open physical memory for access to MP structures */ + if ((pfd = open("/dev/mem", O_RDONLY)) < 0) + err(1, "mem open"); + + /* probe for MP structures */ + apic_probe(&paddr, &where); + if (where <= 0) { + fprintf(stderr, "\n MP FPS NOT found,\n"); + fprintf(stderr, " suggest trying -grope option!!!\n\n"); + return 1; + } + + if (verbose) + printf("\n MP FPS found in %s @ physical addr: 0x%08x\n", + whereStrings[where - 1], paddr); + + if (verbose) + puts(SEP_LINE); + + /* analyze the MP Floating Pointer Structure */ + MPFloatingPointer(paddr, where, &mpfps); + + if (verbose) + puts(SEP_LINE); + + /* check whether an MP config table exists */ + if ((defaultConfig = mpfps.mpfb1)) + MPConfigDefault(defaultConfig); + else + MPConfigTableHeader(mpfps.pap); + + /* build "options" entries for the kernel config file */ + if (noisy) + doOptionList(); + + write_code(postamble); + /* do a dmesg output */ + if (dmesg) + doDmesg(); + + if (verbose) + puts(SEP_LINE2); + + return 0; +} + +/* + * set PHYSICAL address of MP floating pointer structure + */ +#define NEXT(X) ((X) += 4) +static void apic_probe(vm_offset_t * paddr, int *where) +{ + /* + * c rewrite of apic_probe() by Jack F. Vogel + */ + + int x; + u_short segment; + vm_offset_t target; + u_int buffer[BIOS_SIZE / sizeof(int)]; + + if (verbose) + printf("\n"); + + /* search Extended Bios Data Area, if present */ + if (verbose) + printf(" looking for EBDA pointer @ 0x%04x, ", EBDA_POINTER); + seekEntry((vm_offset_t) EBDA_POINTER); + readEntry(&segment, 2); + if (segment) { /* search EBDA */ + target = (vm_offset_t) segment << 4; + if (verbose) + printf("found, searching EBDA @ 0x%08x\n", target); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 1; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + } else { + if (verbose) + printf("NOT found\n"); + } + + target = 0; + segment = 0; + if (verbose) + printf(" searching for coreboot MP table @ 0x%08x (%dK)\n", + target, segment); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 2; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + + /* read CMOS for real top of mem */ + seekEntry((vm_offset_t) TOPOFMEM_POINTER); + readEntry(&segment, 2); + --segment; /* less ONE_KBYTE */ + target = segment * 1024; + if (verbose) + printf(" searching CMOS 'top of mem' @ 0x%08x (%dK)\n", + target, segment); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 2; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + + /* we don't necessarily believe CMOS, check base of the last 1K of 640K */ + if (target != (DEFAULT_TOPOFMEM - 1024)) { + target = (DEFAULT_TOPOFMEM - 1024); + if (verbose) + printf + (" searching default 'top of mem' @ 0x%08x (%dK)\n", + target, (target / 1024)); + seekEntry(target); + readEntry(buffer, ONE_KBYTE); + + for (x = 0; x < ONE_KBYTE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 3; + *paddr = (x * sizeof(unsigned int)) + target; + return; + } + } + } + + /* search the BIOS */ + if (verbose) + printf(" searching BIOS @ 0x%08x\n", BIOS_BASE); + seekEntry(BIOS_BASE); + readEntry(buffer, BIOS_SIZE); + + for (x = 0; x < BIOS_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 4; + *paddr = (x * sizeof(unsigned int)) + BIOS_BASE; + return; + } + } + + /* search the extended BIOS */ + if (verbose) + printf(" searching extended BIOS @ 0x%08x\n", BIOS_BASE2); + seekEntry(BIOS_BASE2); + readEntry(buffer, BIOS_SIZE); + + for (x = 0; x < BIOS_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 5; + *paddr = (x * sizeof(unsigned int)) + BIOS_BASE2; + return; + } + } + + if (grope) { + /* search additional memory */ + target = GROPE_AREA1; + if (verbose) + printf(" groping memory @ 0x%08x\n", target); + seekEntry(target); + readEntry(buffer, GROPE_SIZE); + + for (x = 0; x < GROPE_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 6; + *paddr = + (x * sizeof(unsigned int)) + GROPE_AREA1; + return; + } + } + + target = GROPE_AREA2; + if (verbose) + printf(" groping memory @ 0x%08x\n", target); + seekEntry(target); + readEntry(buffer, GROPE_SIZE); + + for (x = 0; x < GROPE_SIZE / sizeof(unsigned int); NEXT(x)) { + if (buffer[x] == MP_SIG) { + *where = 7; + *paddr = + (x * sizeof(unsigned int)) + GROPE_AREA2; + return; + } + } + } + + *where = 0; + *paddr = (vm_offset_t) 0; +} + +/* + * + */ +static void MPFloatingPointer(vm_offset_t paddr, int where, mpfps_t * mpfps) +{ + + /* read in mpfps structure */ + seekEntry(paddr); + readEntry(mpfps, sizeof(mpfps_t)); + + /* show its contents */ + if (verbose) { + printf("MP Floating Pointer Structure:\n\n"); + + printf(" location:\t\t\t"); + switch (where) { + case 1: + printf("EBDA\n"); + break; + case 2: + printf("BIOS base memory\n"); + break; + case 3: + printf("DEFAULT base memory (639K)\n"); + break; + case 4: + printf("BIOS\n"); + break; + case 5: + printf("Extended BIOS\n"); + break; + + case 0: + printf("NOT found!\n"); + exit(1); + default: + printf("BOGUS!\n"); + exit(1); + } + printf(" physical address:\t\t0x%08x\n", paddr); + + printf(" signature:\t\t\t'"); + pnstr(mpfps->signature, 4); + printf("'\n"); + + printf(" length:\t\t\t%d bytes\n", mpfps->length * 16); + printf(" version:\t\t\t1.%1d\n", mpfps->spec_rev); + printf(" checksum:\t\t\t0x%02x\n", mpfps->checksum); + + /* bits 0:6 are RESERVED */ + if (mpfps->mpfb2 & 0x7f) { + printf(" warning, MP feature byte 2: 0x%02x\n", + mpfps->mpfb2); + } + + /* bit 7 is IMCRP */ + printf(" mode:\t\t\t\t%s\n", (mpfps->mpfb2 & 0x80) ? + "PIC" : "Virtual Wire"); + + /* MP feature bytes 3-5 are expected to be ZERO */ + if (mpfps->mpfb3) + printf(" warning, MP feature byte 3 NONZERO!\n"); + if (mpfps->mpfb4) + printf(" warning, MP feature byte 4 NONZERO!\n"); + if (mpfps->mpfb5) + printf(" warning, MP feature byte 5 NONZERO!\n"); + } +} + +/* + * + */ +static void MPConfigDefault(int featureByte) +{ + printf(" MP default config type: %d\n\n", featureByte); + switch (featureByte) { + case 1: + printf(" bus: ISA, APIC: 82489DX\n"); + break; + case 2: + printf(" bus: EISA, APIC: 82489DX\n"); + break; + case 3: + printf(" bus: EISA, APIC: 82489DX\n"); + break; + case 4: + printf(" bus: MCA, APIC: 82489DX\n"); + break; + case 5: + printf(" bus: ISA+PCI, APIC: Integrated\n"); + break; + case 6: + printf(" bus: EISA+PCI, APIC: Integrated\n"); + break; + case 7: + printf(" bus: MCA+PCI, APIC: Integrated\n"); + break; + default: + printf(" future type\n"); + break; + } + + switch (featureByte) { + case 1: + case 2: + case 3: + case 4: + nbus = 1; + break; + case 5: + case 6: + case 7: + nbus = 2; + break; + default: + printf(" future type\n"); + break; + } + + ncpu = 2; + napic = 1; + nintr = 16; +} + +/* + * + */ +static void MPConfigTableHeader(uint32_t pap) +{ + vm_offset_t paddr; + mpcth_t cth; + int x; + int totalSize; + int count, c; + int type; + + if (pap == 0) { + printf("MP Configuration Table Header MISSING!\n"); + exit(1); + } + + /* convert physical address to virtual address */ + paddr = (vm_offset_t) pap; + + /* read in cth structure */ + seekEntry(paddr); + readEntry(&cth, sizeof(cth)); + + if (verbose) { + printf("MP Config Table Header:\n\n"); + + printf(" physical address:\t\t0x%08x\n", pap); + + printf(" signature:\t\t\t'"); + pnstr(cth.signature, 4); + printf("'\n"); + + printf(" base table length:\t\t%d\n", cth.base_table_length); + + printf(" version:\t\t\t1.%1d\n", cth.spec_rev); + printf(" checksum:\t\t\t0x%02x\n", cth.checksum); + + printf(" OEM ID:\t\t\t'"); + pnstr(cth.oem_id, 8); + printf("'\n"); + + printf(" Product ID:\t\t\t'"); + pnstr(cth.product_id, 12); + printf("'\n"); + + printf(" OEM table pointer:\t\t0x%08x\n", + cth.oem_table_pointer); + printf(" OEM table size:\t\t%d\n", cth.oem_table_size); + + printf(" entry count:\t\t\t%d\n", cth.entry_count); + + printf(" local APIC address:\t\t0x%08x\n", cth.apic_address); + + printf(" extended table length:\t%d\n", + cth.extended_table_length); + printf(" extended table checksum:\t%d\n", + cth.extended_table_checksum); + } + + totalSize = cth.base_table_length - sizeof(struct MPCTH); + count = cth.entry_count; + + if (verbose) { + if (verbose) + puts(SEP_LINE); + + printf("MP Config Base Table Entries:\n\n"); + } + + /* initialze tables */ + for(x = 0; x < ARRAY_SIZE(busses); x++) + busses[x] = UNKNOWN_BUSTYPE; + for(x = 0; x < ARRAY_SIZE(apics); x++) + apics[x] = 0xff; + + ncpu = 0; + nbus = 0; + napic = 0; + nintr = 0; + + /* process all the CPUs */ + if (verbose) { + printf("--\nProcessors:\tAPIC ID\tVersion\tState" + "\t\tFamily\tModel\tStep\tFlags\n"); + } + for (c = count; c; c--) { + if (readType() == 0) + processorEntry(); + totalSize -= basetableEntryTypes[0].length; + } + + /* process all the busses */ + printf("\t/* Bus: Bus ID Type */\n"); + for (c = count; c; c--) { + if (readType() == 1) + busEntry(); + totalSize -= basetableEntryTypes[1].length; + } + + /* process all the apics */ + printf("\t/* I/O APICs: APIC ID Version State Address */\n"); + for (c = count; c; c--) { + if (readType() == 2) + ioApicEntry(); + totalSize -= basetableEntryTypes[2].length; + } + + /* process all the I/O Ints */ + printf("\t/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ \n"); + for (c = count; c; c--) { + if (readType() == 3) + intEntry(); + totalSize -= basetableEntryTypes[3].length; + } + + /* process all the Local Ints */ + printf + ("\t/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */\n"); + for (c = count; c; c--) { + if (readType() == 4) + lintEntry(); + totalSize -= basetableEntryTypes[4].length; + } + +#if defined( EXTENDED_PROCESSING_READY ) + /* process any extended data */ + if ((totalSize = cth.extended_table_length)) { + if (verbose) + puts(SEP_LINE); + + printf("MP Config Extended Table Entries:\n\n"); + + while (totalSize > 0) { + switch (type = readType()) { + case 128: + sasEntry(); + break; + case 129: + bhdEntry(); + break; + case 130: + cbasmEntry(); + break; + default: + printf("Extended Table HOSED!\n"); + exit(1); + } + + totalSize -= extendedtableEntryTypes[type - 128].length; + } + } +#endif /* EXTENDED_PROCESSING_READY */ + + /* process any OEM data */ + if (cth.oem_table_pointer && (cth.oem_table_size > 0)) { +#if defined( OEM_PROCESSING_READY ) +#error your on your own here! + /* convert OEM table pointer to virtual address */ + poemtp = (vm_offset_t) cth.oem_table_pointer; + + /* read in oem table structure */ + if ((oemdata = (void *)malloc(cth.oem_table_size)) == NULL) + err(1, "oem malloc"); + + seekEntry(poemtp); + readEntry(oemdata, cth.oem_table_size); + + /** process it */ + + free(oemdata); +#else + printf + ("\nyou need to modify the source to handle OEM data!\n\n"); +#endif /* OEM_PROCESSING_READY */ + } + + fflush(stdout); + +#if defined( RAW_DUMP ) + { + int ofd; + u_char dumpbuf[4096]; + + ofd = open("/tmp/mpdump", O_CREAT | O_RDWR); + seekEntry(paddr); + readEntry(dumpbuf, 1024); + write(ofd, dumpbuf, 1024); + close(ofd); + } +#endif /* RAW_DUMP */ +} + +/* + * + */ +static int readType(void) +{ + u_char type; + + if (read(pfd, &type, sizeof(u_char)) != sizeof(u_char)) + err(1, "type read; pfd: %d", pfd); + + if (lseek(pfd, -1, SEEK_CUR) < 0) + err(1, "type seek"); + + return (int)type; +} + +/* + * + */ +static void seekEntry(vm_offset_t addr) +{ + if (lseek(pfd, (off_t) addr, SEEK_SET) < 0) + err(1, "/dev/mem seek"); +} + +/* + * + */ +static void readEntry(void *entry, int size) +{ + if (read(pfd, entry, size) != size) + err(1, "readEntry"); +} + +static void processorEntry(void) +{ + ProcEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + ++ncpu; + if (noisy) { + printf("\t\t%2d", entry.apicID); + printf("\t 0x%2x", entry.apicVersion); + + printf("\t %s, %s", + (entry.cpuFlags & PROCENTRY_FLAG_BP) ? "BSP" : "AP", + (entry. + cpuFlags & PROCENTRY_FLAG_EN) ? "usable" : "unusable"); + + printf("\t %d\t %d\t %d", + (entry.cpuSignature >> 8) & 0x0f, + (entry.cpuSignature >> 4) & 0x0f, + entry.cpuSignature & 0x0f); + + printf("\t 0x%04x\n", entry.featureFlags); + } +} + +/* + * + */ +static int lookupBusType(char *name) +{ + int x; + + for (x = 0; x < MAX_BUSTYPE; ++x) + if (strcmp(busTypeTable[x].name, name) == 0) + return busTypeTable[x].type; + + return UNKNOWN_BUSTYPE; +} + +static void busEntry(void) +{ + char name[8]; + BusEntry entry; + int i; + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + ++nbus; + + if (verbose) { + printf("\t\t%2d", entry.busID); + printf("\t "); + pnstr(entry.busType, 6); + printf("\n"); + } + + memset(name, '\0', sizeof(name)); + for(i = 0; i < 6; i++) { + switch(entry.busType[i]) { + case ' ': + case '\0': + break; + default: + name[i] = entry.busType[i]; + break; + } + } + + if (entry.busID > ARRAY_SIZE(busses)) { + fprintf(stderr, "busses array to small!\n"); + exit(1); + } + + busses[entry.busID] = lookupBusType(name); + printf("\tsmp_write_bus(mc, %d, \"", entry.busID); + pnstr(entry.busType, 6); + printf("\");\n"); +} + +static void ioApicEntry(void) +{ + IOApicEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + ++napic; + + if (noisy) { + printf("\t\t%2d", entry.apicID); + printf("\t 0x%02x", entry.apicVersion); + printf("\t %s", + (entry. + apicFlags & IOAPICENTRY_FLAG_EN) ? "usable" : + "unusable"); + printf("\t\t 0x%x\n", entry.apicAddress); + } + + apics[entry.apicID] = entry.apicID; + + if (entry.apicFlags & IOAPICENTRY_FLAG_EN) + printf("\tsmp_write_ioapic(mc, 0x%x, 0x%x, 0x%x);\n", + entry.apicID, entry.apicVersion, entry.apicAddress); +} + +char *intTypes[] = { + "mp_INT", "mp_NMI", "mp_SMI", "mp_ExtINT" +}; + +char *polarityMode[] = { + "MP_IRQ_POLARITY_DEFAULT", "MP_IRQ_POLARITY_HIGH", "reserved", + "MP_IRQ_POLARITY_LOW" +}; + +char *triggerMode[] = { + "MP_IRQ_TRIGGER_DEFAULT", "MP_IRQ_TRIGGER_EDGE", "reserved", + "MP_IRQ_TRIGGER_LEVEL" +}; + +static void intEntry(void) +{ + IntEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + if ((int)entry.type == 3) + ++nintr; + + if (noisy) { + printf("\n\t\t%s", intTypes[(int)entry.intType]); + + printf("\t%9s", polarityMode[(int)entry.intFlags & 0x03]); + printf("%12s", triggerMode[((int)entry.intFlags >> 2) & 0x03]); + + printf("\t %5d", (int)entry.srcBusID); + if (busses[(int)entry.srcBusID] == PCI) + printf("\t%2d:%c", + ((int)entry.srcBusIRQ >> 2) & 0x1f, + ((int)entry.srcBusIRQ & 0x03) + 'A'); + else + printf("\t 0x%x:0x%x(0x%x)", + (int)entry.srcBusIRQ >> 2, + (int)entry.srcBusIRQ & 3, (int)entry.srcBusIRQ); + printf("\t %6d", (int)entry.dstApicID); + printf("\t %3d\n", (int)entry.dstApicINT); + } + + if (busses[(int)entry.srcBusID] == PCI) { + printf("\tsmp_write_intsrc(mc, %s, %s|%s, 0x%x, (0x%02x << 2) | INT%c, 0x%x, 0x%x);\n", + intTypes[(int)entry.intType], + triggerMode[((int)entry.intFlags >> 2) & 0x03], + polarityMode[(int)entry.intFlags & 0x03], + (int)entry.srcBusID, + (int)entry.srcBusIRQ >> 2, + ((int)entry.srcBusIRQ & 3) + 'A', + (int)entry.dstApicID, (int)entry.dstApicINT); + } else { + printf("\tsmp_write_intsrc(mc, %s, %s|%s, 0x%x, 0x%x, 0x%x, 0x%x);\n", + intTypes[(int)entry.intType], + triggerMode[((int)entry.intFlags >> 2) & 0x03], + polarityMode[(int)entry.intFlags & 0x03], + (int)entry.srcBusID, + (int)entry.srcBusIRQ, + (int)entry.dstApicID, (int)entry.dstApicINT); + } +} + +static void lintEntry(void) +{ + IntEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + /* count it */ + if ((int)entry.type == 3) + ++nintr; + + if (noisy) { + printf("\t\t%s", intTypes[(int)entry.intType]); + + printf("\t%9s", polarityMode[(int)entry.intFlags & 0x03]); + printf("%12s", triggerMode[((int)entry.intFlags >> 2) & 0x03]); + + printf("\t %5d", (int)entry.srcBusID); + if (busses[(int)entry.srcBusID] == PCI) + printf("\t%2d:%c", + ((int)entry.srcBusIRQ >> 2) & 0x1f, + ((int)entry.srcBusIRQ & 0x03) + 'A'); + else + printf("\t %3d", (int)entry.srcBusIRQ); + printf("\t %6d", (int)entry.dstApicID); + printf("\t %3d\n", (int)entry.dstApicINT); + } + printf + ("\tsmp_write_lintsrc(mc, %s, %s|%s, 0x%x, 0x%x, MP_APIC_ALL, 0x%x);\n", + intTypes[(int)entry.intType], + triggerMode[((int)entry.intFlags >> 2) & 0x03], + polarityMode[(int)entry.intFlags & 0x03], (int)entry.srcBusID, + (int)entry.srcBusIRQ, (int)entry.dstApicINT); + +} + +static void sasEntry(void) +{ + SasEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + printf("--\n%s\n", extendedtableEntryTypes[entry.type - 128].name); + printf(" bus ID: %d", entry.busID); + printf(" address type: "); + switch (entry.addressType) { + case 0: + printf("I/O address\n"); + break; + case 1: + printf("memory address\n"); + break; + case 2: + printf("prefetch address\n"); + break; + default: + printf("UNKNOWN type\n"); + break; + } + + printf(" address base: 0x%lx\n", entry.addressBase); + printf(" address range: 0x%lx\n", entry.addressLength); +} + +static void bhdEntry(void) +{ + BhdEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + printf("--\n%s\n", extendedtableEntryTypes[entry.type - 128].name); + printf(" bus ID: %d", entry.busID); + printf(" bus info: 0x%02x", entry.busInfo); + printf(" parent bus ID: %d", entry.busParent); +} + +static void cbasmEntry(void) +{ + CbasmEntry entry; + + /* read it into local memory */ + readEntry(&entry, sizeof(entry)); + + printf("--\n%s\n", extendedtableEntryTypes[entry.type - 128].name); + printf(" bus ID: %d", entry.busID); + printf(" address modifier: %s\n", (entry.addressMod & 0x01) ? + "subtract" : "add"); + printf(" predefined range: 0x%08x", entry.predefinedRange); +} + +/* + * do a dmesg output + */ +static void doDmesg(void) +{ + if (verbose) + puts(SEP_LINE); + + printf("dmesg output:\n\n"); + fflush(stdout); + system("dmesg"); +} + +/* + * build "options" entries for the kernel config file + */ +static void doOptionList(void) +{ + if (verbose) + puts(SEP_LINE); + + printf("# SMP kernel config file options:\n\n"); + printf("\n# Required:\n"); + printf("options SMP\t\t\t# Symmetric MultiProcessor Kernel\n"); + printf("options APIC_IO\t\t\t# Symmetric (APIC) I/O\n"); + + printf("\n# Optional (built-in defaults will work in most cases):\n"); + printf("#options NCPU=%d\t\t\t# number of CPUs\n", ncpu); + printf("#options NBUS=%d\t\t\t# number of busses\n", + nbus); + printf("#options NAPIC=%d\t\t\t# number of IO APICs\n", + napic); + printf("#options NINTR=%d\t\t# number of INTs\n", + (nintr < 24) ? 24 : nintr); +} + +/* + * + */ +static void pnstr(uint8_t * s, int c) +{ + uint8_t string[MAXPNSTR + 1]; + + if (c > MAXPNSTR) + c = MAXPNSTR; + strncpy((char *)string, (char *)s, c); + string[c] = '\0'; + printf("%s", string); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieff7673387ae9275b8271f4a483926b774697a8d Gerrit-Change-Number: 48322 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 8,1 support
by Evgeny Zinoviev (Code Review) 18 Apr '22

18 Apr '22

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33151 Change subject: mb/apple: Add MacBook Pro 8,1 support ...................................................................... mb/apple: Add MacBook Pro 8,1 support MacBook Pro 13'' Early 2011 (A1278). Works: - Graphics initialization (libgfxinit) - GRUB payload - Linux (it boots) Mostly untested for now. This board has SOIC-8 chip, 25Q064A in my case. WARNING: do not just use a clip to flash the chip as usual. There is a capacitor and a resistor right near the VCC pin. They prevent the clip from being properly attached. You can very easily break them. Either cut off some plasic from the clip so that it doesn't touch them, or don't use clip at all. Change-Id: I7a7dc6d6c16751403ce276d2778dc915cd69f3f2 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/mainboard/apple/macbookpro8_1/Kconfig A src/mainboard/apple/macbookpro8_1/Kconfig.name A src/mainboard/apple/macbookpro8_1/Makefile.inc A src/mainboard/apple/macbookpro8_1/acpi/ec.asl A src/mainboard/apple/macbookpro8_1/acpi/platform.asl A src/mainboard/apple/macbookpro8_1/acpi/superio.asl A src/mainboard/apple/macbookpro8_1/acpi_tables.c A src/mainboard/apple/macbookpro8_1/board_info.txt A src/mainboard/apple/macbookpro8_1/cmos.default A src/mainboard/apple/macbookpro8_1/cmos.layout A src/mainboard/apple/macbookpro8_1/devicetree.cb A src/mainboard/apple/macbookpro8_1/dsdt.asl A src/mainboard/apple/macbookpro8_1/gpio.c A src/mainboard/apple/macbookpro8_1/hda_verb.c A src/mainboard/apple/macbookpro8_1/mainboard.c A src/mainboard/apple/macbookpro8_1/romstage.c 16 files changed, 816 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33151/1 diff --git a/src/mainboard/apple/macbookpro8_1/Kconfig b/src/mainboard/apple/macbookpro8_1/Kconfig new file mode 100644 index 0000000..c838bea --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/Kconfig @@ -0,0 +1,43 @@ +if BOARD_APPLE_MACBOOKPRO8_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default apple/macbookpro8_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro8,1" + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 +endif diff --git a/src/mainboard/apple/macbookpro8_1/Kconfig.name b/src/mainboard/apple/macbookpro8_1/Kconfig.name new file mode 100644 index 0000000..06a7de5 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO8_1 + bool "MacBookPro8,1" diff --git a/src/mainboard/apple/macbookpro8_1/Makefile.inc b/src/mainboard/apple/macbookpro8_1/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro8_1/acpi/ec.asl b/src/mainboard/apple/macbookpro8_1/acpi/ec.asl new file mode 100644 index 0000000..cd74865 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi/ec.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac_60.asl> +#include <ec/apple/acpi/lid_60.asl> diff --git a/src/mainboard/apple/macbookpro8_1/acpi/platform.asl b/src/mainboard/apple/macbookpro8_1/acpi/platform.asl new file mode 100644 index 0000000..3603581 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi/platform.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/apple/macbookpro8_1/acpi/superio.asl b/src/mainboard/apple/macbookpro8_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro8_1/acpi_tables.c b/src/mainboard/apple/macbookpro8_1/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro8_1/board_info.txt b/src/mainboard/apple/macbookpro8_1/board_info.txt new file mode 100644 index 0000000..8e0e321 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2011 diff --git a/src/mainboard/apple/macbookpro8_1/cmos.default b/src/mainboard/apple/macbookpro8_1/cmos.default new file mode 100644 index 0000000..53e85a3 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/cmos.default @@ -0,0 +1 @@ +debug_level=Debug diff --git a/src/mainboard/apple/macbookpro8_1/cmos.layout b/src/mainboard/apple/macbookpro8_1/cmos.layout new file mode 100644 index 0000000..aa9f563 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/cmos.layout @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/apple/macbookpro8_1/devicetree.cb b/src/mainboard/apple/macbookpro8_1/devicetree.cb new file mode 100644 index 0000000..db21a62 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/devicetree.cb @@ -0,0 +1,113 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "600" + register "gpu_pch_backlight" = "0x13121312" + + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x8086 0x7270 + end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00db + end + device pci 01.0 off # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00db + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00db + end + device pci 01.1 on + subsystemid 0x106b 0x00db + end + device pci 1a.7 on + subsystemid 0x8086 0x7270 + end + device pci 1d.7 on + subsystemid 0x8086 0x7270 + end + end +end diff --git a/src/mainboard/apple/macbookpro8_1/dsdt.asl b/src/mainboard/apple/macbookpro8_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro8_1/gpio.c b/src/mainboard/apple/macbookpro8_1/gpio.c new file mode 100644 index 0000000..d3555ef --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro8_1/hda_verb.c b/src/mainboard/apple/macbookpro8_1/hda_verb.c new file mode 100644 index 0000000..d6cb85e --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b1c00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b1c00), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x012b4030), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100121), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be040), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro8_1/mainboard.c b/src/mainboard/apple/macbookpro8_1/mainboard.c new file mode 100644 index 0000000..fe63303 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/mainboard.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro8_1/romstage.c b/src/mainboard/apple/macbookpro8_1/romstage.c new file mode 100644 index 0000000..4dffacb --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/romstage.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <arch/byteorder.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7dc6d6c16751403ce276d2778dc915cd69f3f2 Gerrit-Change-Number: 33151 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

5 38

Change in ...coreboot[master]: drivers/apple: Add hybrid graphics driver
by Evgeny Zinoviev (Code Review) 18 Apr '22

18 Apr '22

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32719 Change subject: drivers/apple: Add hybrid graphics driver ...................................................................... drivers/apple: Add hybrid graphics driver Hybrid graphics driver for Apple MacBook Pro. Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/drivers/apple/hybrid_graphics/Kconfig A src/drivers/apple/hybrid_graphics/Makefile.inc A src/drivers/apple/hybrid_graphics/chip.h A src/drivers/apple/hybrid_graphics/gmux.c A src/drivers/apple/hybrid_graphics/gmux.h A src/drivers/apple/hybrid_graphics/hybrid_graphics.c A src/drivers/apple/hybrid_graphics/hybrid_graphics.h A src/drivers/apple/hybrid_graphics/romstage.c 8 files changed, 417 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32719/1 diff --git a/src/drivers/apple/hybrid_graphics/Kconfig b/src/drivers/apple/hybrid_graphics/Kconfig new file mode 100644 index 0000000..252373f --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_APPLE_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/apple/hybrid_graphics/Makefile.inc b/src/drivers/apple/hybrid_graphics/Makefile.inc new file mode 100644 index 0000000..ea45b45 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/Makefile.inc @@ -0,0 +1,15 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c romstage.c +ramstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c hybrid_graphics.c diff --git a/src/drivers/apple/hybrid_graphics/chip.h b/src/drivers/apple/hybrid_graphics/chip.h new file mode 100644 index 0000000..39434f8 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _APPLE_HYBRID_GRAPHICS_CHIP_H_ +#define _APPLE_HYBRID_GRAPHICS_CHIP_H_ + +enum hybrid_graphics_req { + HYBRID_GRAPHICS_INTEGRATED = 0, + HYBRID_GRAPHICS_DISCRETE = 1 +}; + +#define HYBRID_GRAPHICS_DEFAULT_GPU HYBRID_GRAPHICS_INTEGRATED + +struct drivers_apple_hybrid_graphics_config { + unsigned int gmux_indexed; +}; + +#endif /* _APPLE_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/apple/hybrid_graphics/gmux.c b/src/drivers/apple/hybrid_graphics/gmux.c new file mode 100644 index 0000000..e1f763a --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/gmux.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com> + * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de> + * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de> + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <arch/io.h> +#include <device/device.h> +#include "gmux.h" +#include "chip.h" + +static int gmux_index_wait_ready(void) +{ + int i = 200; + u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + + while (i && (gwr & 0x01)) { + inb(GMUX_IOSTART + GMUX_PORT_READ); + gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + udelay(100); + i--; + } + + return !!i; +} + +static int gmux_index_wait_complete(void) +{ + int i = 200; + u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + + while (i && !(gwr & 0x01)) { + gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + udelay(100); + i--; + } + + if (gwr & 0x01) + inb(GMUX_IOSTART + GMUX_PORT_READ); + + return !!i; +} + +u8 gmux_pio_read8(int port) +{ + return inb(GMUX_IOSTART + port); +} + +u8 gmux_index_read8(int port) +{ + u8 val; + + gmux_index_wait_ready(); + outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ); + gmux_index_wait_complete(); + val = inb(GMUX_IOSTART + GMUX_PORT_VALUE); + + return val; +} + +void gmux_pio_write8(int port, u8 val) +{ + outb(val, GMUX_IOSTART + port); +} + + +void gmux_index_write8(int port, u8 val) +{ + outb(val, GMUX_IOSTART + GMUX_PORT_VALUE); + gmux_index_wait_ready(); + outb(port & 0xff, GMUX_IOSTART + GMUX_PORT_WRITE); + gmux_index_wait_complete(); +} + +u32 gmux_pio_read32(int port) +{ + return inl(GMUX_IOSTART + port); +} + +u32 gmux_index_read32(int port) +{ + u32 val; + + gmux_index_wait_ready(); + outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ); + gmux_index_wait_complete(); + val = inl(GMUX_IOSTART + GMUX_PORT_VALUE); + + return val; +} + +u8 gmux_read8(const struct device *dev, int port) +{ + const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info; + if (config->gmux_indexed) { + return gmux_index_read8(port); + } else { + return gmux_pio_read8(port); + } +} + +void gmux_write8(const struct device *dev, int port, u8 val) +{ + const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info; + if (config->gmux_indexed) { + gmux_index_write8(port, val); + } else { + gmux_pio_write8(port, val); + } +} + +u32 gmux_read32(const struct device *dev, int port) +{ + const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info; + if (config->gmux_indexed) { + return gmux_index_read32(port); + } else { + return gmux_pio_read32(port); + } +} + +void gmux_dgpu_power_enable(const struct device *dev, bool enable) +{ + if (enable) { + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1); + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 3); + } else { + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1); + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 0); + } +} + +void gmux_switch(const struct device *dev, bool dgpu) +{ + if (dgpu) { + gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 2); + gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 3); + } else { + gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 1); + gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 2); + } +} + + diff --git a/src/drivers/apple/hybrid_graphics/gmux.h b/src/drivers/apple/hybrid_graphics/gmux.h new file mode 100644 index 0000000..18f6722 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/gmux.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com> + * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de> + * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de> + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_APPLE_GMUX_H +#define EC_APPLE_GMUX_H + +#define GMUX_PORT_VERSION_MAJOR 0x04 +#define GMUX_PORT_VERSION_MINOR 0x05 +#define GMUX_PORT_VERSION_RELEASE 0x06 + +#define GMUX_PORT_SWITCH_DISPLAY 0x10 +#define GMUX_PORT_SWITCH_DDC 0x28 +#define GMUX_PORT_DISCRETE_POWER 0x50 +#define GMUX_PORT_MAX_BRIGHTNESS 0x70 +#define GMUX_PORT_BRIGHTNESS 0x74 +#define GMUX_PORT_VALUE 0xc2 +#define GMUX_PORT_READ 0xd0 +#define GMUX_PORT_WRITE 0xd4 + +#define GMUX_PORT_INTERRUPT_ENABLE 0x14 +#define GMUX_INTERRUPT_ENABLE 0xff +#define GMUX_INTERRUPT_DISABLE 0x00 + +#define GMUX_BRIGHTNESS_MASK 0x00ffffff +#define GMUX_MAX_BRIGHTNESS GMUX_BRIGHTNESS_MASK + +#define GMUX_IOSTART 0x700 + +u8 gmux_index_read8(int port); +u8 gmux_pio_read8(int port); +u8 gmux_read8(const struct device *dev, int port); + +void gmux_index_write8(int port, u8 val); +void gmux_pio_write8(int port, u8 val); +void gmux_write8(const struct device *dev, int port, u8 val); + +u32 gmux_index_read32(int port); +u32 gmux_pio_read32(int port); +u32 gmux_read32(const struct device *dev, int port); + +void gmux_switch(const struct device *dev, bool dgpu); +void gmux_dgpu_power_enable(const struct device *dev, bool enable); + +#endif /* EC_APPLE_GMUX_H */ diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.c b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c new file mode 100644 index 0000000..804eb76 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <option.h> +#include <device/device.h> + +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include "chip.h" +#include "gmux.h" + +static void enable_dev(struct device *dev) +{ + printk(BIOS_INFO, "Hybrid graphics enable_dev\n"); + + const struct drivers_lenovo_hybrid_graphics_config *config; + enum hybrid_graphics_req mode; + u8 ver_major, ver_minor, ver_release; + u32 version, max_brightness, brightness; + + /* Don't confuse anyone else and disable the fake device */ + dev->enabled = 0; + + config = dev->chip_info; + if (!config) { + printk(BIOS_INFO, "Hybrid graphics: Not installed\n"); + return; + } + + version = gmux_index_read32(GMUX_PORT_VERSION_MAJOR); + ver_major = (version >> 24) & 0xff; + ver_minor = (version >> 16) & 0xff; + ver_release = (version >> 8) & 0xff; + max_brightness = gmux_index_read32(GMUX_PORT_MAX_BRIGHTNESS); + brightness = gmux_index_read32(GMUX_PORT_BRIGHTNESS) & GMUX_BRIGHTNESS_MASK; + + printk(BIOS_INFO, "gmux version: %d.%d.%d\n", + ver_major, ver_minor, ver_release); + printk(BIOS_INFO, "gmux max brightness: %d\n", max_brightness); + printk(BIOS_INFO, "gmux brightness: %d\n", brightness); + + mode = HYBRID_GRAPHICS_DEFAULT_GPU; + get_option(&mode, "hybrid_graphics_mode"); + + gmux_switch(dev, mode == HYBRID_GRAPHICS_DISCRETE); +} + +struct chip_operations drivers_apple_hybrid_graphics_ops = { + CHIP_NAME("Apple hybrid graphics driver") + .enable_dev = enable_dev +}; diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.h b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h new file mode 100644 index 0000000..782be44 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_APPLE_HYBRID_GRAPHICS_H_ +#define _DRIVERS_APPLE_HYBRID_GRAPHICS_H_ + +#define HYBRID_GRAPHICS_PORT 0xff +#define HYBRID_GRAPHICS_DEVICE 0xf + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); + +#endif /* _DRIVERS_APPLE_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/apple/hybrid_graphics/romstage.c b/src/drivers/apple/hybrid_graphics/romstage.c new file mode 100644 index 0000000..9cd5098 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <option.h> +#include <device/device.h> +#include <console/console.h> +#include "hybrid_graphics.h" +#include "chip.h" +#include "gmux.h" + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg) +{ + const struct drivers_apple_hybrid_graphics_config *config; + const struct device *dev; + + enum hybrid_graphics_req mode = HYBRID_GRAPHICS_DEFAULT_GPU; + + printk(BIOS_INFO, "Hybrid graphics early_hybrid_graphics\n"); + + /* TODO: Use generic device instead of dummy PNP device */ + dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "Hybrid graphics: ERROR\n"); + *enable_igd = true; + *enable_peg = false; + return; + } + + config = dev->chip_info; + + get_option(&mode, "hybrid_graphics_mode"); + + if (mode == HYBRID_GRAPHICS_DISCRETE) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling integrated GPU.\n"); + + *enable_igd = false; + *enable_peg = true; + } else if (mode == HYBRID_GRAPHICS_INTEGRATED) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling discrete GPU.\n"); + + *enable_igd = true; + *enable_peg = false; + } + + gmux_dgpu_power_enable(dev, *enable_peg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc Gerrit-Change-Number: 32719 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

7 26

Change in coreboot[master]: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) p...
by Mike Banon (Code Review) 17 Apr '22

17 Apr '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48427 ) Change subject: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply seven changes for improving the IRQ routing on these AMD boards: 1) CB:48161, CB:48162, CB:48163, CB:48179 - for AMD Lenovo G505S; 2) CB:48424, CB:48425, CB:48426 - for ASUS A88XM-E; 3) Not ready yet - for ASUS AM1I-A. Save to ./coreboot/ then run ./get_irq_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 --- A apply_irq_patches.sh A check_irq_patches.sh A get_irq_patches.sh A sha256sums_irq_correct.txt 4 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48427/1 diff --git a/apply_irq_patches.sh b/apply_irq_patches.sh new file mode 100755 index 0000000..8fc5318 --- /dev/null +++ b/apply_irq_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +patch -p1 < "./08638df.diff" +### diff --git a/check_irq_patches.sh b/check_irq_patches.sh new file mode 100755 index 0000000..3a2bb16 --- /dev/null +++ b/check_irq_patches.sh @@ -0,0 +1,18 @@ +#!/bin/sh +rm -f "./sha256sums_irq_my.txt" +sha256sum "./cd096f9.diff" > "./sha256sums_irq_my.txt" +sha256sum "./42aeed4.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./c6ab05e.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./8517e5a.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./cfc8288.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./489e510.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./08638df.diff" >> "./sha256sums_irq_my.txt" +if cmp -s "./sha256sums_irq_my.txt" "./sha256sums_irq_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_irq_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_irq_my.txt and ./sha256sums_irq_correct.txt" + exit 1 +fi +# diff --git a/get_irq_patches.sh b/get_irq_patches.sh new file mode 100755 index 0000000..97da6b5 --- /dev/null +++ b/get_irq_patches.sh @@ -0,0 +1,51 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +rm -f "./cd096f9.diff" +wget "https://review.coreboot.org/changes/48161/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +rm -f "./42aeed4.diff" +wget "https://review.coreboot.org/changes/48162/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +rm -f "./c6ab05e.diff" +wget "https://review.coreboot.org/changes/48163/revisions/3/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +rm -f "./8517e5a.diff" +wget "https://review.coreboot.org/changes/48179/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +rm -f "./cfc8288.diff" +wget "https://review.coreboot.org/changes/48424/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +rm -f "./489e510.diff" +wget "https://review.coreboot.org/changes/48425/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +rm -f "./08638df.diff" +wget "https://review.coreboot.org/changes/48426/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./08638df.diff" +### diff --git a/sha256sums_irq_correct.txt b/sha256sums_irq_correct.txt new file mode 100755 index 0000000..a06b640 --- /dev/null +++ b/sha256sums_irq_correct.txt @@ -0,0 +1,7 @@ +9fd4cca063bb6e6c9063f00f4c972c019d616560883b9bda76177a462817ae8e ./cd096f9.diff +357a1e1e9f250149127fa8f7aac089e481a39f96b313ae1a0310c7e5d22faa72 ./42aeed4.diff +e350591056f1a10b5922cc7180a07e1142f14fe8af41f6c545317a37c12880ed ./c6ab05e.diff +ab0b347af164e5c50c580f036e7ed55757e90158ad3cb04fc2f8154b5392f804 ./8517e5a.diff +358c3a5fcce7085ca49154370c21cd95396fa8fa9d0b30e1de8625fe1db0f36d ./cfc8288.diff +669bd10d74229f3e2200a9e206fad49326928348a6ad3f261f14ebe920b63c56 ./489e510.diff +fab791e93eb63b880d2692eff527979051dadcf504018f58346c6f0c4c6173b6 ./08638df.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/48427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 Gerrit-Change-Number: 48427 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 7

Change in coreboot[master]: asus/a88xm-e: properly program the IRQ tables
by Mike Banon (Code Review) 17 Apr '22

17 Apr '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48424 ) Change subject: asus/a88xm-e: properly program the IRQ tables ...................................................................... asus/a88xm-e: properly program the IRQ tables IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table. With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 207 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/1 diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c index 2e08188..5caf224 100644 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -6,26 +6,54 @@ #include <device/device.h> #include <southbridge/amd/common/amd_pci_util.h> -static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, -}; -static const u8 mainboard_intr_data[84] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> + +extern const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE]; +extern const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE]; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D} }, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ }; /* PIRQ Setup */ static void pirq_setup(void) { + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -36,6 +64,7 @@ msr_t msr; printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); msr = rdmsr(LS_CFG_MSR); diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c index b9e743c..5d9731f 100644 --- a/src/mainboard/asus/a88xm-e/mptable.c +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -1,10 +1,61 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <stdint.h> #include <string.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> + +/* + * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms: + * + * SCI - System Controller Interrupt, + * SMBUS - System Management Bus, + * ASF - Advanced Synchronization Facility, + * HDA - HD Audio, + * SD - SD Flash Controller, + * GEC - Gigabit Ethernet Controller, + * PerMon - Performance Monitor, + * IMC - Integrated Memory Controller, + * GPP - PCIe General Purpose Ports. + */ + +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05, + /* IDE, SATA */ + [0x40] = 0x1F, 0x07, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, + /* IDE, SATA */ + [0x40] = 0x1F, 0x13, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { @@ -37,92 +88,150 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ - bus_isa, (intr), (apicid), (pin)) + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ - (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) - /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); + /* IOMMU: 0:00.02 - IRQ 3 */ + PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]); - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]); - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]); + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x06, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x06, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x06, 0x3, intr_data_ptr[PIRQ_A]); - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); + /* SATA: 0:11.00 - IRQ 7 */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + /* USB OHCI1: 0:12.00 - IRQ 5 */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + /* USB EHCI1: 0:12.02 - IRQ 4 */ + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + /* USB OHCI2: 0:13.00 - IRQ 5 */ + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + /* USB EHCI2: 0:13.02 - IRQ 4 */ + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + /* USB OHCI3: 0:16.00 - IRQ 5 */ + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + /* USB EHCI3: 0:16.02 - IRQ 4 */ + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + /* USB OHCI4: 0:14.05 - IRQ 5 */ + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]); /* PCI slots */ struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); + /* PCI slot 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); } - /* PCIe Lan */ - PCI_INT(0x0, 0x06, 0x0, 0x13); + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_B]); + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_C]); + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_D]); + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_A]); - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]); - /* Local Ints: Type IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]); + + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x4, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x4, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x4, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d Gerrit-Change-Number: 48424 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 ) Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage ...................................................................... [TESTONLY]nb/intel/x4x: Cache cbmem in romstage Probably not a good idea to avoid eviction in romstage. TESTED: works fine on P5QL-EM. Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/raminit.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e24..6665eb0 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -27,6 +27,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8013af9..e8729fb 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -33,6 +33,7 @@ #include <mrc_cache.h> #include <timestamp.h> #include <types.h> +#include <cpu/x86/mtrr.h> #include "iomap.h" #include "x4x.h" @@ -718,6 +719,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); if (!fast_boot) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, -- To view, visit https://review.coreboot.org/c/coreboot/+/37213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Gerrit-Change-Number: 37213 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021