coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6387 discussions

Change in ...coreboot[master]: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33107 Change subject: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2 ...................................................................... [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2 BOOT_MEDIA_PARAMS2 exposes the boot media MMIO address if it's memory mapped in addition to various regions inside the bootmedia. That information can be used by payloads to: * Support VBOOT on SeaBIOS, as it otherwise uses the RO CBFS only * Support Intel Apollolake and platforms that don't map the end of the BIOS region to the end of the address space * Support fwupd and flashrom finding the FMAP in memory Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 2 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33107/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 198ad27..a854e44 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -392,6 +392,81 @@ struct mac_address mac_addrs[0]; }; +/** + * coreboot boot media params2 + * + * The coreboot 'boot media params2' contain information about the + * bootmedia layout, allowing a payload to read the boot media + * without the need to parse (platform specific) layout files. + * + * It extends 'boot media params' by MMIO addresses and a second CBFS + * pointer. + * + * If the boot media is memory mapped, as it's usually done on x86 platforms, + * the FMAP and CBFS can be easily accessed by any software without the need + * for platform specific drivers. + * + * If the boot media is not memory mapped, the `mmap_mmio_address` is set + * to ~0ULL. In that case the software must use platform specific drivers + * to access the boot media (like flashrom or Linux's MTD). + * + * The memory mapped area is `mmap_size` bytes in size, starting `mmap_offset` + * bytes from `mmap_mmio_address`. + * The memory mapped area might be smaller than `boot_media_size` bytes, + * which gives the total size in bytes as seen by an external programmer. + * + * Software utilizing the coreboot boot media params2 shall check if the + * region to be access falls completely within the memory mapped region, + * before trying to access them. + * In addition it should not assume that the whole boot media is memory mapped. + * + * Example on Intel Apollolake: + * + * physical memory boot media + * +-----------+ + * | | + * | | + * +-----------+ MMAP MMIO address +-----------------+ -------- + * | ~UNAVAIL~ | | | IFD | | | | | + * | | MMAP offset | | | | | | + * | | | | | | | | | + * +-----------+ --- <<< +-----------------+ | | | | + * | BIOS REG | | | BIOS | | | | | + * | | | | | | | | | + * | | | |+---------------+| --+-+-+-+CBFS offset + * | | | || CBFS Active || | | | + * | | MMAP size |+---------------+| --+-+-+FMAP offset + * | | | || FMAP || | | + * | | | |+---------------+| --+-+CBFS legacy offset + * | | | || COREBOOT(CBFS)|| | + * +-----------+ --- <<< |+---------------+| | + * | TXE SRAM | || BIOS UNUSABLE || | + * | | |+---------------+| | + * +-----------+ +-----------------+ | + * |DEVICE EXTENSION | | + * | | | + * +-----------------+ -+Boot media size + */ + +#define LB_TAG_BOOT_MEDIA_PARAMS2 0x0036 +struct lb_boot_media_params2 { + uint32_t tag; + uint32_t size; + /* offsets are relative to start of boot media */ + uint64_t fmap_offset; + uint64_t cbfs_offset; + uint64_t cbfs_legacy_offset; + uint64_t mmap_offset; + /* Size is in bytes */ + uint64_t cbfs_size; + uint64_t fmap_size; + uint64_t boot_media_size; + uint64_t cbfs_legacy_size; + uint64_t mmap_size; + /* MMIO address of MMAPed boot media, ~0ULL if not MMAPed.*/ + uint64_t mmap_mmio_address; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d..c5807fd 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -261,8 +261,10 @@ static void lb_boot_media_params(struct lb_header *header) { struct lb_boot_media_params *bmp; + struct lb_boot_media_params2 *bmp2; struct cbfs_props props; const struct region_device *boot_dev; + struct region ar; struct region_device fmrd; boot_device_init(); @@ -285,6 +287,47 @@ bmp->fmap_offset = ~(uint64_t)0; if (find_fmap_directory(&fmrd) == 0) bmp->fmap_offset = region_device_offset(&fmrd); + + /* LB_TAG_BOOT_MEDIA_PARAMS2 exposes additional parameters: + * - MMAPed boot media address + * - legacy CBFS position (RO partition in case of VBOOT) + */ + bmp2 = (struct lb_boot_media_params2 *)lb_new_record(header); + bmp2->tag = LB_TAG_BOOT_MEDIA_PARAMS2; + bmp2->size = sizeof(*bmp2); + + bmp2->cbfs_offset = bmp->cbfs_offset; + bmp2->cbfs_size = bmp->cbfs_size; + bmp2->boot_media_size = bmp->boot_media_size; + bmp2->fmap_offset = bmp->fmap_offset; + + if (find_fmap_directory(&fmrd) == 0) + bmp2->fmap_size = region_device_size(&fmrd); + + if (fmap_locate_area("COREBOOT", &ar)) { + printk(BIOS_INFO, "Can't find 'COREBOOT' area in FMAP\n"); + bmp2->cbfs_legacy_offset = ~(uint64_t)0; + bmp2->cbfs_legacy_size = 0; + } else { + bmp2->cbfs_legacy_offset = ar.offset; + bmp2->cbfs_legacy_size = ar.size; + } + + if (CONFIG(COMMON_CBFS_SPI_WRAPPER)) { + /* rdev_mmap will return a pointer to _postram_cbfs_cache */ + bmp2->mmap_offset = ~(uint64_t)0; + bmp2->mmap_size = 0; + bmp2->mmap_mmio_address = ~(uint64_t)0; + } else { + /* FIXME: Introduce API to set correct values here */ + bmp2->mmap_offset = 0; + bmp2->mmap_size = bmp2->boot_media_size; + /* Get address to MMAP boot media */ + uintptr_t off = (uintptr_t)rdev_mmap(boot_dev, 0, + bmp2->mmap_size); + bmp2->mmap_mmio_address = off; + rdev_munmap(boot_dev, (void *)off); + } } static void lb_ram_code(struct lb_header *header) -- To view, visit https://review.coreboot.org/c/coreboot/+/33107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570 Gerrit-Change-Number: 33107 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 22

Change in coreboot[master]: x86: Prevent Kconfig errors resulting in a brick
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34709 ) Change subject: x86: Prevent Kconfig errors resulting in a brick ...................................................................... x86: Prevent Kconfig errors resulting in a brick Always select USE_LEGACY_8254_TIMER if we know we have to. Fixes boot failure (Linux kernel/GRUB2 hangs with no console output) on X11SSH-TF using SeaBIOS as payload. Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/GRUB2/Kconfig.name M payloads/external/SeaBIOS/Kconfig.name M src/device/Kconfig M src/soc/intel/common/block/timer/Kconfig 4 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34709/1 diff --git a/payloads/external/GRUB2/Kconfig.name b/payloads/external/GRUB2/Kconfig.name index fe60d76..40629ad 100644 --- a/payloads/external/GRUB2/Kconfig.name +++ b/payloads/external/GRUB2/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_GRUB2 bool "GRUB2" depends on ARCH_X86 || ARCH_ARM + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a GRUB2 payload. If you don't know what this is diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name index bb1f30c..8f92997 100644 --- a/payloads/external/SeaBIOS/Kconfig.name +++ b/payloads/external/SeaBIOS/Kconfig.name @@ -1,6 +1,7 @@ config PAYLOAD_SEABIOS bool "SeaBIOS" depends on ARCH_X86 + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is diff --git a/src/device/Kconfig b/src/device/Kconfig index e605bc2..ebf6bfb 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -86,6 +86,7 @@ bool "Run VGA Option ROMs" depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER + select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK help Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a214ef0..66bf9cf 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -5,7 +5,6 @@ config USE_LEGACY_8254_TIMER bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN default n help This sets the FSP UPD to enable Legacy 8254 clock gating. As per -- To view, visit https://review.coreboot.org/c/coreboot/+/34709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e Gerrit-Change-Number: 34709 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 29

Change in coreboot[master]: sb/intel/common: Add AHCI code
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37137 ) Change subject: sb/intel/common: Add AHCI code ...................................................................... sb/intel/common: Add AHCI code Implement a clean implementation based on AHCI spec 1.0-1.3 and the Intel ICH/PCH datasheets. The common implementation should combine all features of the duplicated code present in the various southbridge implementations. It compiles on x86_64, uses less magic values and detects the AHCI version at runtime. Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/include/ahci.h M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/ahci.c A src/southbridge/intel/common/ahci.h 5 files changed, 252 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37137/1 diff --git a/src/include/ahci.h b/src/include/ahci.h new file mode 100644 index 0000000..e7818fb --- /dev/null +++ b/src/include/ahci.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AHCI_H__ +#define __AHCI_H__ + +/* Serial ATA AHCI 1.3.1 Specification */ + +#define AHCI_CAP 0x00 +#define AHCI_CAP_NP 0x1f +#define AHCI_CAP_PSC (1u << 13) +#define AHCI_CAP_SSC (1u << 14) +#define AHCI_CAP_PMD (1u << 15) +#define AHCI_CAP_SPM (1u << 17) +#define AHCI_CAP_SAM (1u << 18) +#define AHCI_CAP_SNZO (1u << 19) +#define AHCI_CAP_ISS(x) ((x) << 20) +#define AHCI_CAP_SCLO (1u << 24) +#define AHCI_CAP_SAL (1u << 25) +#define AHCI_CAP_SALP (1u << 26) +#define AHCI_CAP_SSS (1u << 27) +#define AHCI_CAP_SIS (1u << 28) +#define AHCI_CAP_SNCQ (1u << 30) +#define AHCI_CAP_S64A (1u << 31) +/* Added in AHCI 1.1 */ +#define AHCI_CAP_SXS (1u << 5) +#define AHCI_CAP_EMS (1u << 6) +#define AHCI_CAP_CCCS (1u << 7) +/* Added in AHCI 1.2 */ +#define AHCI_CAP_SSNTF (1u << 29) + +#define AHCI_GHC 0x04 +#define AHCI_GHC_AE (1u << 31) +#define AHCI_PI 0x0c +#define AHCI_VS 0x10 +#define AHCI_VS_MAJOR(x) ((x >> 16) & 0xf) +#define AHCI_VS_MINOR(x) ((x >> 8) & 0xf) + +/* Added in AHCI 1.1 */ +#define AHCI_CCC_CTL 0x14 +#define AHCI_CCC_PORTS 0x18 +#define AHCI_EM_LOC 0x1c +#define AHCI_EM_CTL 0x20 +/* Added in AHCI 1.2 */ +#define AHCI_CAP2 0x24 +#define AHCI_CAP2_BOH (1u << 0) +/* Added in AHCI 1.3 */ +#define AHCI_CAP2_NVMP (1u << 1) +#define AHCI_CAP2_APST (1u << 2) +#define AHCI_CAP2_SDS (1u << 3) +#define AHCI_CAP2_SADM (1u << 4) +#define AHCI_CAP2_DESO (1u << 5) + +#define AHCI_BOHC 0x28 + +#define AHCI_VENDOR 0xa0 +#define AHCI_PORT 0x100 +#define AHCI_PORT_PxCMD 0x18 +#define AHCI_PORT_LEN 0x80 + + +#endif diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 18bcd2e..376f077 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -2,6 +2,10 @@ def_bool n select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_AHCI + def_bool n + depends on PCI + config SOUTHBRIDGE_INTEL_COMMON_RTC def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index c8521e1..e87ae82 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -18,6 +18,8 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_AHCI) += ahci.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/ahci.c b/src/southbridge/intel/common/ahci.c new file mode 100644 index 0000000..ca20d30 --- /dev/null +++ b/src/southbridge/intel/common/ahci.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ahci.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> + +#include "ahci.h" + +/** + * Initialize the AHCI config space. + * @param port_map The ports to enable + * @param sam Set SAM bit (no legacy device support) + * @param cccs Set CCCS bit + * @param iss Limit the controller to sata gen x + * @param devslp Enable DEVSLP feature if supported + * @param clear_vnd Clear bits in vendor config space + */ +void sb_ahci_init(struct device *const dev, + const u32 port_map, + const bool sam, + const bool cccs, + const u8 iss, + const bool devslp, + const u32 clear_vnd) +{ + u32 reg32; + u8 major, minor; + struct resource *res; + u8 *abar; + unsigned int ports; + + /* Initialize AHCI memory-mapped space */ + res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + abar = res2mmio(res, 0, 0); + /* + * Set AHCI access mode. + * Spec: "No other ABAR registers should be accessed before this." + */ + reg32 = read32(abar + AHCI_GHC); + if (!(reg32 & AHCI_GHC_AE)) { + reg32 |= AHCI_GHC_AE; + write32(abar + AHCI_GHC, reg32); + } + + /* Get AHCI version */ + reg32 = read32(abar + AHCI_VS); + major = AHCI_VS_MAJOR(reg32); + minor = AHCI_VS_MINOR(reg32); + printk(BIOS_DEBUG, "AHCI: implements AHCI %d.%d\n", major, minor); + + reg32 = read32(abar + AHCI_CAP); + printk(BIOS_DEBUG, "AHCI: supports SATA Gen%d\n", (reg32 >> 20) & 0xf); + + ports = reg32 & AHCI_CAP_NP; + printk(BIOS_DEBUG, "AHCI: supports up to %d ports\n", ports); + + /* CAP (HBA Capabilities) : enable power management */ + /* Program Write-Once bits (this isn't part of the AHCI spec, but PCH). */ + if (sam) + reg32 |= AHCI_CAP_SAM; + if (cccs && major >= 1 && minor >= 1) + reg32 |= AHCI_CAP_CCCS; + if (iss) { + u8 max_iss; + if (major >= 1 && minor >= 2) + max_iss = MIN(iss, 3); + else + max_iss = MIN(iss, 2); + reg32 &= ~AHCI_CAP_ISS(0xf); + reg32 |= AHCI_CAP_ISS(max_iss); + printk(BIOS_DEBUG, "AHCI: limited to Gen%d\n", max_iss); + } + reg32 |= AHCI_CAP_PSC; + reg32 |= AHCI_CAP_SSC; + reg32 |= AHCI_CAP_SALP; + reg32 |= AHCI_CAP_SSS; + if (major >= 1 && minor >= 1) { + reg32 &= ~AHCI_CAP_SXS; + reg32 &= ~AHCI_CAP_EMS; + reg32 &= ~AHCI_CAP_SPM; + } + write32(abar + AHCI_CAP, reg32); + + if (major >= 1 && minor >= 2) { + reg32 = read32(abar + AHCI_CAP2); + /* Clear BIOS handoff support */ + reg32 &= ~AHCI_CAP2_BOH; + if (major >= 1 && minor >= 3) { + /* Configure DEVSLP support */ + if (devslp) { + reg32 |= AHCI_CAP2_APST; + reg32 |= AHCI_CAP2_SDS; + reg32 |= AHCI_CAP2_SADM; + reg32 |= AHCI_CAP2_DESO; + } else { + reg32 &= ~AHCI_CAP2_SDS; + } + /* Disable NVMHCI */ + reg32 &= ~AHCI_CAP2_NVMP; + } + write32(abar + AHCI_CAP2, reg32); + } + + if (port_map & ~((1 << ports) - 1)) + printk(BIOS_ERR, "AHCI: Invalid port map given!\n"); + + write32(abar + AHCI_PI, port_map & ((1 << ports) - 1)); + /* PCH code reads back twice, do we need it, too? */ + (void) read32(abar + AHCI_PI); /* Read back 1 */ + (void) read32(abar + AHCI_PI); /* Read back 2 */ + + /* Clear vendor specific bits */ + reg32 = read32(abar + AHCI_VENDOR); + reg32 &= ~clear_vnd; + write32(abar + AHCI_VENDOR, reg32); + + /* Lock R/WO bits in Port command registers. */ + for (size_t i = 0; i < ports; ++i) { + if (!((1 << i) & port_map)) + continue; + u8 *addr = abar + AHCI_PORT + (i * AHCI_PORT_LEN); + write32(addr, read32(addr + AHCI_PORT_PxCMD)); + } +} diff --git a/src/southbridge/intel/common/ahci.h b/src/southbridge/intel/common/ahci.h new file mode 100644 index 0000000..9d4a025 --- /dev/null +++ b/src/southbridge/intel/common/ahci.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_AHCI_H +#define SOUTHBRIDGE_INTEL_COMMON_AHCI_H + +#include <device/device.h> + +void sb_ahci_init(struct device *const dev, + const u32 port_map, + const bool sam, + const bool cccs, + const u8 iss, + const bool devslp, + const u32 clear_vnd); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_AHCI_H */ + -- To view, visit https://review.coreboot.org/c/coreboot/+/37137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8 Gerrit-Change-Number: 37137 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 13

Change in coreboot[master]: mb/google/zork/vilboz: enable LTE function
by Peichao Li (Code Review) 07 Aug '23

07 Aug '23

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43663 ) Change subject: mb/google/zork/vilboz: enable LTE function ...................................................................... mb/google/zork/vilboz: enable LTE function BUG=b:161736991 TEST=flash the BIOS and insure LTE function work properly Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I130bd76aad0a4b8f3a82090d97f140a0a7ed958e --- M src/mainboard/google/zork/variants/vilboz/Makefile.inc A src/mainboard/google/zork/variants/vilboz/gpio.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43663/1 diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index dc1e411..51d19fe 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += ./spd +ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c new file mode 100644 index 0000000..4d292c2 --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +static const struct soc_amd_gpio lte_gpio_set_stage_ram[] = { + /* LTE POWER ENABLE */ + PAD_GPO(GPIO_32, HIGH), +}; + + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(lte_gpio_set_stage_ram); + return lte_gpio_set_stage_ram; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130bd76aad0a4b8f3a82090d97f140a0a7ed958e Gerrit-Change-Number: 43663 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/common/gpio_defs: Remove incorrent GPO macro
by Maxim Polyakov (Code Review) 07 Aug '23

07 Aug '23

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44471 ) Change subject: soc/intel/common/gpio_defs: Remove incorrent GPO macro ...................................................................... soc/intel/common/gpio_defs: Remove incorrent GPO macro GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. For this reason, this patch removes the PAD_CFG_GPO_GPIO_DRIVER macro as it is not correct. This has also been removed from the pad configuration in the follow boards and this patch should be added after: [1] Change-Id: I5aed5769600bb9c442ad13a2efbcf9d5fd8da537 [2] Change-Id: Iac7d674e79e0caee467fc087e6d36192e84a12d8 [3] Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea [4] Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c Change-Id: I74c318897647836f4604a937543254f44b470433 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/getting_started/gpio.md M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44471/1 diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 13aeed5..339289b 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -92,8 +92,6 @@ #define PAD_CFG_GPO(pad, val, rst) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) - /* General purpose output, no pullup/down. */ - #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) ``` diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 3d3c831..4dcf04c 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -229,14 +229,6 @@ PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) -/* General purpose output, no pullup/down. */ -#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ - PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | \ - PAD_CFG_OWN_GPIO(DRIVER)) - /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/44471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c318897647836f4604a937543254f44b470433 Gerrit-Change-Number: 44471 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: WIP: soc/amd/picasso: Add ACPI AC/DC Wake Alarm
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45966 ) Change subject: WIP: soc/amd/picasso: Add ACPI AC/DC Wake Alarm ...................................................................... WIP: soc/amd/picasso: Add ACPI AC/DC Wake Alarm This adds the ACPI entry for the ACPI AC/DC Wake Alarm. This is different than the RTC wake alarm, because it waits until the system has entered S3 before firing the wake event. This prevents race conditions between setting the alarm and suspending in time. This is WIP because the SCI map is not getting set correctly. BUG=b:157533281 BRANCH=zork TEST=On Morphius try suspending and watching the system wake up localhost /sys/devices/platform/ACPI000E:00 # tail ac_* dc_* ==> ac_alarm <== disabled ==> ac_policy <== never ==> ac_status <== 0x00 ==> dc_alarm <== disabled ==> dc_policy <== never ==> dc_status <== 0x00 localhost /sys/devices/platform/ACPI000E:00 # echo 15 > ac_alarm localhost /sys/devices/platform/ACPI000E:00 # powerd_dbus_suspend <Device Resumes> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia99aaba98405f9b6e50b33936716da9a71338f58 --- M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/acdc.c M src/soc/amd/picasso/acpi/soc.asl A src/soc/amd/picasso/acpi/wake_alarm.asl 5 files changed, 280 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/45966/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 758a5562..f3836ad 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -123,7 +123,6 @@ #define ACPIMMIO_GPIO1_BANK 0x1600 #define ACPIMMIO_GPIO2_BANK 0x1700 #define ACPIMMIO_XHCIPM_BANK 0x1c00 -#define ACPIMMIO_ACDCTMR_BANK 0x1d00 #define ACPIMMIO_AOAC_BANK 0x1e00 /* FIXME: Passing host base for SMBUS is not long-term solution. */ @@ -132,4 +131,6 @@ #endif +#define ACPIMMIO_ACDCTMR_BANK 0x1d00 + #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 1e9ba4a..6048691 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -80,6 +80,7 @@ ramstage-y += graphics.c ramstage-y += pcie_gpp.c ramstage-y += xhci.c +ramstage-y += acdc.c ramstage-y += dmi.c smm-y += smihandler.c diff --git a/src/soc/amd/picasso/acdc.c b/src/soc/amd/picasso/acdc.c new file mode 100644 index 0000000..08c8404 --- /dev/null +++ b/src/soc/amd/picasso/acdc.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/gpio_banks.h> +#include <bootstate.h> +#include <soc/smi.h> +#include <soc/soc_util.h> + +static const struct sci_source acdc_sci_sources[] = { + { + .scimap = SMITYPE_ACDC_TIMER, + .gpe = GEVENT_30, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, +}; + +static void configure_acdc_sci(void *unused) +{ + gpe_configure_sci(acdc_sci_sources, ARRAY_SIZE(acdc_sci_sources)); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_acdc_sci, NULL); diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index b3b036e..a92d1e0 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -14,6 +14,9 @@ /* Describe the AOAC devices */ #include "aoac.asl" +/* Describe the Wake Alarm Device devices */ +#include "wake_alarm.asl" + /* Describe the devices in the Southbridge */ #include "sb_fch.asl" diff --git a/src/soc/amd/picasso/acpi/wake_alarm.asl b/src/soc/amd/picasso/acpi/wake_alarm.asl new file mode 100644 index 0000000..e5cd866 --- /dev/null +++ b/src/soc/amd/picasso/acpi/wake_alarm.asl @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/acpimmio_map.h> + +Device(AWAK) { + Name(_HID, "ACPI000E") + OperationRegion (ACDC, SystemMemory, AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ACDCTMR_BANK, 0x24) + Field (ACDC, WordAcc, NoLock, Preserve) { + /* + * AC Timer Value + * + * Writing the register with a value other than FFFF_FFFFh + * starts the AC timer. Reading this register returns the + * current value of the AC timer. + */ + ACTV, 32, + + /* + * AC Expired Timer Policy + */ + ACTP, 32, + + /* + * AC Timer Status + */ + ACST, 32, + + Offset (0x10), + /* + * DC Timer Value + * + * Writing the register with a value other than FFFF_FFFFh + * starts the DC timer. Reading this register returns the + * current value of the DC timer. + */ + DCTV, 32, + + /* + * DC Expired Timer Policy + */ + DCTP, 32, + + /* + * DC Timer Status + */ + DCST, 32, + + Offset (0x20), + BUSY, 1, + , 7, /* Reserved */ + + ACEN, 1, /* Enable AC Timer to wake up system. */ + DCEN, 1, /* Enable DC Timer to wake up system. */ + , 22, /* Reserved */ + + } + + // _PRW: Power Resources for Wake + Name (_PRW, Package () { + 0x1E, + 0x03 + }) + + /** + * Get Capability + * + * Return Value: + * 31:9 - Reserved + * 8 - 1 = Wake supported from S5 on DC + * 7 - 1 = Wake supported from S4 on DC + * 6 - 1 = Wake supported from S5 on AC + * 5 - 1 = Wake supported from S4 on AC + * 4 - 1 = _GWS returns correct values for wakes from S4/S5 caused by + * timer + * 3 - 1 = Real time accuracy in milliseconds + * 0 = Real time accuracy in seconds + * 2 - 1 = Get/Set real time features implemented + * 1 - 1 = DC wake implemented + * 0 - 1 = AC wake implemented + * Bit [9] to Bit [31] are reserved and must be 0. + */ + Name (_GCP, 0x03) + + /** + * Get Wake alarm status + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 31:2 - Reserved + * 1 - 1 = Timer caused a platform wake + * 0 - 1 = Timer expired + */ + Method(_GWS, 1) { + If (Arg0) { + Return (DCST) + } Else { + Return (ACST) + } + } + + /** + * Clear Wake alarm status + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 1 - Failure + * 0 - Success + */ + Method(_CWS, 1) { + If (Arg0) { + DCST = 0x3 + } Else { + ACST = 0x3 + } + Return(0) + } + + /** + * Set Expired Timer Wake Policy + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Args1: Expired Timer Wake Policy + * 0 = The timer will wake up the system instantly after the power + * source changes. + * 1 - 0xFFFFFFFE = Time between the power source changes and the + * timer wakes up the system (in units of second). + * 0xFFFFFFFF = The timer will never wake up the system after the + * power source changes. + * Return: + * 1 - Failure + * 0 - Success + */ + Method(_STP, 2) { + If (Arg0) { + DCTP = Arg1 + } Else { + ACTP = Arg1 + } + Return(0) + } + + /** + * Get Expired Timer Wake Policy + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 0 = The timer will wake up the system instantly after the power + * source changes. + * 1 - 0xFFFFFFFE = Time between the power source changes and the + * timer wakes up the system (in units of second). + * 0xFFFFFFFF = The timer will never wake up the system after the + * power source changes. + */ + Method(_TIP, 1) { + If (Arg0) { + Return (DCTP) + } Else { + Return (ACTP) + } + } + + /** + * Set Timer Value + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Args1: Timer Value + * + * Return: + * 1 - Failure + * 0 - Success + */ + Method(_STV, 2, Serialized) { + If (Arg0) { + DCEN = 1 + While (BUSY) { + Printf ("Waiting for DC Timer") + Stall (100) + } + DCTV = Arg1 + While (BUSY) { + Printf ("Waiting for DC Timer to initialize") + Stall (100) + } + } Else { + ACEN = 1 + While (BUSY) { + Printf ("Waiting for AC Timer") + Stall (100) + } + ACTV = Arg1 + While (BUSY) { + Printf ("Waiting for AC Timer to initialize") + Stall (100) + } + } + Return(0) + } + + /** + * Get Timer Value + * + * Args0: Timer Identifier + * 0 = AC Timer + * 1 = DC Timer + * + * Return: + * 0 - 0xFFFFFFFE = The current timer value. + * 0xFFFFFFFF = The timer is disabled. + */ + Method(_TIV, 1) { + If (Arg0) { + Return (DCTV) + } Else { + Return (ACTV) + } + } +} + + +Scope(\_GPE) { + Method(_L30, 0, Serialized) { + Local0 = 0 + If (\_SB.AWAK._GWS(1) & 0x2) { /* DC timer caused wake */ + \_SB.AWAK._CWS(1) /* Clear DC timer wake */ + Local0 = 1 + } + + If (\_SB.AWAK._GWS(0) & 0x2) { /* AC timer caused wake */ + \_SB.AWAK._CWS(0) /* Clear AC timer wake */ + Local0 = 1 + } + + If (Local0) { + Notify(\_SB.AWAK, 0x2) //notify the OSPM of device wake + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia99aaba98405f9b6e50b33936716da9a71338f58 Gerrit-Change-Number: 45966 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/dell/latitude_e7240: Transform into variant
by Pablo Stebler (Code Review) 07 Aug '23

07 Aug '23

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46539 ) Change subject: mb/dell/latitude_e7240: Transform into variant ...................................................................... mb/dell/latitude_e7240: Transform into variant In preparation for E7440 support. Untested for now. Something like "hsw_bdw_laptops" could be a better name from a git history POV if other boards like E5450 or M4800 are subsequently added. Signed-off-by: Pablo Stebler <pablo(a)stebler.xyz> Change-Id: I95a9d72a285f296309f4c0d11ec0de6079ac383d --- D src/mainboard/dell/latitude_e7240/Kconfig.name D src/mainboard/dell/latitude_e7240/Makefile.inc D src/mainboard/dell/latitude_e7240/board_info.txt R src/mainboard/dell/latitude_e7x40/Kconfig A src/mainboard/dell/latitude_e7x40/Kconfig.name A src/mainboard/dell/latitude_e7x40/Makefile.inc R src/mainboard/dell/latitude_e7x40/acpi/ec.asl R src/mainboard/dell/latitude_e7x40/acpi/platform.asl R src/mainboard/dell/latitude_e7x40/acpi/superio.asl R src/mainboard/dell/latitude_e7x40/acpi_tables.c A src/mainboard/dell/latitude_e7x40/board_info.txt R src/mainboard/dell/latitude_e7x40/bootblock.c R src/mainboard/dell/latitude_e7x40/devicetree.cb R src/mainboard/dell/latitude_e7x40/dsdt.asl R src/mainboard/dell/latitude_e7x40/gma-mainboard.ads R src/mainboard/dell/latitude_e7x40/mainboard.c R src/mainboard/dell/latitude_e7x40/romstage.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt R src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/gpio.c R src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/hda_verb.c A src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb 21 files changed, 39 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46539/1 diff --git a/src/mainboard/dell/latitude_e7240/Kconfig.name b/src/mainboard/dell/latitude_e7240/Kconfig.name deleted file mode 100644 index 83ab935..0000000 --- a/src/mainboard/dell/latitude_e7240/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_DELL_LATITUDE_E7240 - bool "Latitude E7240" diff --git a/src/mainboard/dell/latitude_e7240/Makefile.inc b/src/mainboard/dell/latitude_e7240/Makefile.inc deleted file mode 100644 index ec8ca22..0000000 --- a/src/mainboard/dell/latitude_e7240/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -bootblock-y += bootblock.c -bootblock-y += gpio.c -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/board_info.txt b/src/mainboard/dell/latitude_e7240/board_info.txt deleted file mode 100644 index 46e950a..0000000 --- a/src/mainboard/dell/latitude_e7240/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: laptop -Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… -ROM protocol: SPI -ROM package: SOIC-8 -ROM socketed: n -Flashrom support: n -Release year: 2013 diff --git a/src/mainboard/dell/latitude_e7240/Kconfig b/src/mainboard/dell/latitude_e7x40/Kconfig similarity index 65% rename from src/mainboard/dell/latitude_e7240/Kconfig rename to src/mainboard/dell/latitude_e7x40/Kconfig index 2e3b4b4..05ed643 100644 --- a/src/mainboard/dell/latitude_e7240/Kconfig +++ b/src/mainboard/dell/latitude_e7x40/Kconfig @@ -1,7 +1,7 @@ -if BOARD_DELL_LATITUDE_E7240 +## SPDX-License-Identifier: GPL-2.0-only -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_DELL_LATITUDE_E7x40 + def_bool n select BOARD_ROMSIZE_KB_8192 select EC_DELL_MEC5055 select HAVE_ACPI_RESUME @@ -14,13 +14,19 @@ select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP +if BOARD_DELL_LATITUDE_E7x40 + config MAINBOARD_DIR string - default "dell/latitude_e7240" + default "dell/latitude_e7x40" + +config VARIANT_DIR + string + default "latitude_e7240" if BOARD_DELL_LATITUDE_E7240 config MAINBOARD_PART_NUMBER string - default "Latitude E7240" + default "Latitude E7240" if BOARD_DELL_LATITUDE_E7240 config VGA_BIOS_FILE string diff --git a/src/mainboard/dell/latitude_e7x40/Kconfig.name b/src/mainboard/dell/latitude_e7x40/Kconfig.name new file mode 100644 index 0000000..5eefdf7 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/Kconfig.name @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_LATITUDE_E7240 + bool "Latitude E7240" + + select BOARD_DELL_LATITUDE_E7x40 diff --git a/src/mainboard/dell/latitude_e7x40/Makefile.inc b/src/mainboard/dell/latitude_e7x40/Makefile.inc new file mode 100644 index 0000000..eb2cc792 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/acpi/ec.asl b/src/mainboard/dell/latitude_e7x40/acpi/ec.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi/ec.asl rename to src/mainboard/dell/latitude_e7x40/acpi/ec.asl diff --git a/src/mainboard/dell/latitude_e7240/acpi/platform.asl b/src/mainboard/dell/latitude_e7x40/acpi/platform.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi/platform.asl rename to src/mainboard/dell/latitude_e7x40/acpi/platform.asl diff --git a/src/mainboard/dell/latitude_e7240/acpi/superio.asl b/src/mainboard/dell/latitude_e7x40/acpi/superio.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi/superio.asl rename to src/mainboard/dell/latitude_e7x40/acpi/superio.asl diff --git a/src/mainboard/dell/latitude_e7240/acpi_tables.c b/src/mainboard/dell/latitude_e7x40/acpi_tables.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/acpi_tables.c rename to src/mainboard/dell/latitude_e7x40/acpi_tables.c diff --git a/src/mainboard/dell/latitude_e7x40/board_info.txt b/src/mainboard/dell/latitude_e7x40/board_info.txt new file mode 100644 index 0000000..6ad3641 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/dell/latitude_e7240/bootblock.c b/src/mainboard/dell/latitude_e7x40/bootblock.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/bootblock.c rename to src/mainboard/dell/latitude_e7x40/bootblock.c diff --git a/src/mainboard/dell/latitude_e7240/devicetree.cb b/src/mainboard/dell/latitude_e7x40/devicetree.cb similarity index 98% rename from src/mainboard/dell/latitude_e7240/devicetree.cb rename to src/mainboard/dell/latitude_e7x40/devicetree.cb index 345d504..ce7ef7a 100644 --- a/src/mainboard/dell/latitude_e7240/devicetree.cb +++ b/src/mainboard/dell/latitude_e7x40/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip northbridge/intel/haswell register "ec_present" = "true" register "gfx" = "GMA_STATIC_DISPLAYS(0)" @@ -24,8 +26,6 @@ end end device domain 0x0 on - subsystemid 0x1028 0x05ca inherit - device pci 00.0 on end # Host bridge Host bridge device pci 02.0 on end # Internal graphics VGA controller device pci 03.0 on end # Mini-HD audio diff --git a/src/mainboard/dell/latitude_e7240/dsdt.asl b/src/mainboard/dell/latitude_e7x40/dsdt.asl similarity index 100% rename from src/mainboard/dell/latitude_e7240/dsdt.asl rename to src/mainboard/dell/latitude_e7x40/dsdt.asl diff --git a/src/mainboard/dell/latitude_e7240/gma-mainboard.ads b/src/mainboard/dell/latitude_e7x40/gma-mainboard.ads similarity index 100% rename from src/mainboard/dell/latitude_e7240/gma-mainboard.ads rename to src/mainboard/dell/latitude_e7x40/gma-mainboard.ads diff --git a/src/mainboard/dell/latitude_e7240/mainboard.c b/src/mainboard/dell/latitude_e7x40/mainboard.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/mainboard.c rename to src/mainboard/dell/latitude_e7x40/mainboard.c diff --git a/src/mainboard/dell/latitude_e7240/romstage.c b/src/mainboard/dell/latitude_e7x40/romstage.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/romstage.c rename to src/mainboard/dell/latitude_e7x40/romstage.c diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt new file mode 100644 index 0000000..cacaa17 --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/board_info.txt @@ -0,0 +1 @@ +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7… diff --git a/src/mainboard/dell/latitude_e7240/gpio.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/gpio.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/gpio.c rename to src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/gpio.c diff --git a/src/mainboard/dell/latitude_e7240/hda_verb.c b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/hda_verb.c similarity index 100% rename from src/mainboard/dell/latitude_e7240/hda_verb.c rename to src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/hda_verb.c diff --git a/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb new file mode 100644 index 0000000..416e09e --- /dev/null +++ b/src/mainboard/dell/latitude_e7x40/variants/latitude_e7240/overridetree.cb @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + device domain 0x0 on + subsystemid 0x1028 0x05ca inherit + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/46539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9d72a285f296309f4c0d11ec0de6079ac383d Gerrit-Change-Number: 46539 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: soc/intel/common/basecode: Move block/acpi to basecode/acpi
by Subrata Banik (Code Review) 07 Aug '23

07 Aug '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45560 ) Change subject: soc/intel/common/basecode: Move block/acpi to basecode/acpi ...................................................................... soc/intel/common/basecode: Move block/acpi to basecode/acpi This patch ensures that all required code changes been done due to common code movement from block/acpi to basecode/acpi code block. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: Ia18ee1a8c5e795f9dbbc086cb6b39fbf59fc1655 --- M src/mainboard/google/dedede/dsdt.asl M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/cedarisland_crb/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/jasperlake_rvp/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/mainboard/prodrive/hermes/dsdt.asl M src/mainboard/purism/librem_whl/dsdt.asl M src/mainboard/system76/lemp9/dsdt.asl M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/basecode/Kconfig R src/soc/intel/common/basecode/acpi/Kconfig A src/soc/intel/common/basecode/acpi/Makefile.inc R src/soc/intel/common/basecode/acpi/acpi.c R src/soc/intel/common/basecode/acpi/acpi/globalnvs.asl R src/soc/intel/common/basecode/acpi/acpi/ipu.asl R src/soc/intel/common/basecode/acpi/acpi/lpc.asl R src/soc/intel/common/basecode/acpi/acpi/northbridge.asl R src/soc/intel/common/basecode/acpi/acpi/pmc.asl R src/soc/intel/common/basecode/include/intelbasecode/acpi.h D src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/jasperlake/chip.c M src/soc/intel/skylake/acpi/ipu.asl M src/soc/intel/skylake/acpi/lpc.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/skx/acpi.c 60 files changed, 74 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45560/1 diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 933ca1a..2f36703 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -16,7 +16,7 @@ #include <soc/intel/jasperlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/jasperlake/acpi/southbridge.asl> } diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index fac58bd..6a216e6 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -16,14 +16,14 @@ #include <soc/intel/tigerlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index ef2a94e..a699ce1 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -15,7 +15,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -23,7 +23,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index d43a499..88fb977 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -16,7 +16,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index b666fbc..8631e55 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -15,7 +15,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -23,7 +23,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } /* Per board variant mainboard hooks. */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index d0bab1a..0a51a7f 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -16,7 +16,7 @@ #include <soc/intel/tigerlake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index 5a06a45..b992cab 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -13,12 +13,12 @@ #include <soc/intel/cannonlake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 6f408b3..62492da 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -22,7 +22,7 @@ Device (PCI0) { #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> - #include <soc/intel/common/block/acpi/acpi/lpc.asl> + #include <soc/intel/common/basecode/acpi/acpi/lpc.asl> } diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 121012e..5e1c836 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -13,12 +13,12 @@ #include <soc/intel/cannonlake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index a3c93e2..743850f 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -16,7 +16,7 @@ #include <soc/intel/icelake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index be883b4c..9f4f431 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -16,7 +16,7 @@ #include <soc/intel/jasperlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/jasperlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index e34fd58..ce960a1 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -16,7 +16,7 @@ #include <soc/intel/tigerlake/acpi/platform.asl> /* global NVS and variables */ - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } diff --git a/src/mainboard/prodrive/hermes/dsdt.asl b/src/mainboard/prodrive/hermes/dsdt.asl index 4d8d170..b7dfd26 100644 --- a/src/mainboard/prodrive/hermes/dsdt.asl +++ b/src/mainboard/prodrive/hermes/dsdt.asl @@ -13,11 +13,11 @@ #include <soc/intel/cannonlake/acpi/platform.asl> // global NVS and variables - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> Scope (\_SB) { Device (PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } } diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl index 296be17..a72bcfd 100644 --- a/src/mainboard/purism/librem_whl/dsdt.asl +++ b/src/mainboard/purism/librem_whl/dsdt.asl @@ -11,12 +11,12 @@ ) { #include <soc/intel/cannonlake/acpi/platform.asl> - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> Device (\_SB.PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl index eac27b5..779843d 100644 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ b/src/mainboard/system76/lemp9/dsdt.asl @@ -11,12 +11,12 @@ ) { #include <soc/intel/cannonlake/acpi/platform.asl> - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/basecode/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> Device (\_SB.PCI0) { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/common/basecode/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> } diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a30333b..7f85b78 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -60,9 +60,9 @@ select SA_ENABLE_IMR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_DSP diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ee1a543..60985aa 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,7 +11,7 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <gpio.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/pmclib.h> #include <intelblocks/sgx.h> #include <intelblocks/p2sb.h> diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f4d1497..5aee870b 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "xhci.asl" /* LPC */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> /* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9f73727..bdce049 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -9,7 +9,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 596de41..77046ce 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -102,8 +102,8 @@ select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index f061c30..666a770 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -11,7 +11,7 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/p2sb.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index a6b0237..715b565 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -20,7 +20,7 @@ #include "gfx.asl" /* LPC 0:1f.0 */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" @@ -47,4 +47,4 @@ #include "pch_glan.asl" /* PMC Core */ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +#include <soc/intel/common/basecode/acpi/acpi/pmc.asl> diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index ef85215..1015ce3 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig index 1c93244..50dd258 100644 --- a/src/soc/intel/common/basecode/Kconfig +++ b/src/soc/intel/common/basecode/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BASECODE bool + select SOC_INTEL_COMMON_BASECODE_ACPI help Common coreboot stages and non-IP block for Intel platform diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/basecode/acpi/Kconfig similarity index 77% rename from src/soc/intel/common/block/acpi/Kconfig rename to src/soc/intel/common/basecode/acpi/Kconfig index ff59172..48ee919 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/basecode/acpi/Kconfig @@ -1,4 +1,4 @@ -config SOC_INTEL_COMMON_BLOCK_ACPI +config SOC_INTEL_COMMON_BASECODE_ACPI depends on SOC_INTEL_COMMON_BLOCK_CPU depends on SOC_INTEL_COMMON_BLOCK_PMC bool diff --git a/src/soc/intel/common/basecode/acpi/Makefile.inc b/src/soc/intel/common/basecode/acpi/Makefile.inc new file mode 100644 index 0000000..1b73cd8 --- /dev/null +++ b/src/soc/intel/common/basecode/acpi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_ACPI) += acpi.c diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/basecode/acpi/acpi.c similarity index 99% rename from src/soc/intel/common/block/acpi/acpi.c rename to src/soc/intel/common/basecode/acpi/acpi.c index 5951b30..7cf3457 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/basecode/acpi/acpi.c @@ -10,7 +10,7 @@ #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/x86/smm.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/msr.h> #include <intelblocks/pmclib.h> #include <intelblocks/uart.h> diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/basecode/acpi/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/common/block/acpi/acpi/globalnvs.asl rename to src/soc/intel/common/basecode/acpi/acpi/globalnvs.asl diff --git a/src/soc/intel/common/block/acpi/acpi/ipu.asl b/src/soc/intel/common/basecode/acpi/acpi/ipu.asl similarity index 100% rename from src/soc/intel/common/block/acpi/acpi/ipu.asl rename to src/soc/intel/common/basecode/acpi/acpi/ipu.asl diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/basecode/acpi/acpi/lpc.asl similarity index 100% rename from src/soc/intel/common/block/acpi/acpi/lpc.asl rename to src/soc/intel/common/basecode/acpi/acpi/lpc.asl diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/basecode/acpi/acpi/northbridge.asl similarity index 100% rename from src/soc/intel/common/block/acpi/acpi/northbridge.asl rename to src/soc/intel/common/basecode/acpi/acpi/northbridge.asl diff --git a/src/soc/intel/common/block/acpi/acpi/pmc.asl b/src/soc/intel/common/basecode/acpi/acpi/pmc.asl similarity index 100% rename from src/soc/intel/common/block/acpi/acpi/pmc.asl rename to src/soc/intel/common/basecode/acpi/acpi/pmc.asl diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/basecode/include/intelbasecode/acpi.h similarity index 93% rename from src/soc/intel/common/block/include/intelblocks/acpi.h rename to src/soc/intel/common/basecode/include/intelbasecode/acpi.h index 21664c8..09fb3f4 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/basecode/include/intelbasecode/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef SOC_INTEL_COMMON_BLOCK_ACPI_H -#define SOC_INTEL_COMMON_BLOCK_ACPI_H +#ifndef SOC_INTEL_COMMON_BASECODE_ACPI_H +#define SOC_INTEL_COMMON_BASECODE_ACPI_H #include <acpi/acpi.h> #include <device/device.h> @@ -71,4 +71,4 @@ */ void soc_power_states_generation(int core_id, int cores_per_package); -#endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */ +#endif /* _SOC_INTEL_COMMON_BASECODE_ACPI_H_ */ diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc deleted file mode 100644 index c6bdac5..0000000 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 212fd70..b66f583 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -4,7 +4,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/lpc_lib.h> #include <soc/pm.h> diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 6fb7722..b0a4256 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -6,7 +6,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/systemagent.h> #include <smbios.h> diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 47f2567..7b7b383 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -6,7 +6,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/usb/acpi/chip.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/xhci.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 91b45dc..6597f1b 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -26,9 +26,9 @@ select PARALLEL_MP select PCR_COMMON_IOSF_1_0 select INTEL_DESCRIPTOR_MODE_CAPABLE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOC_INTEL_COMMON_BLOCK_FAST_SPI diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 944e8eb..d52c1ec 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -10,7 +10,7 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/soc_util.h> diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index 133569b..e668f76 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ // Intel LPC Bus Device - 0:1f.0 -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> Scope (\_SB.PCI0.LPCB) { diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..7070d81 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -39,8 +39,8 @@ select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index af837ab..c4679dc 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -10,7 +10,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <ec/google/chromeec/ec.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <soc/cpu.h> diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index fd87469..c0b7426 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -15,7 +15,7 @@ #include "gpio.asl" /* ESPI 0:1f.0 */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" @@ -39,7 +39,7 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +#include <soc/intel/common/basecode/acpi/acpi/pmc.asl> /* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index e4884ef..c738fdd 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1e66e97..3a5d747 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -36,9 +36,9 @@ select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index ff66300..3a4cf6a 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -9,7 +9,7 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 474c6cc..6abfc12 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* ESPI 0:1f.0 */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index a455bfc..6933dc7 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/xdci.h> diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 15dc1b3..3e95ab0 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -38,8 +38,8 @@ select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 8673da1..48a2ee1 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -12,7 +12,7 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 48411e4..243db61 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* ESPI 0:1f.0 */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" @@ -45,7 +45,7 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +#include <soc/intel/common/basecode/acpi/acpi/pmc.asl> /* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 36e0175..e05b7e9 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -4,7 +4,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> diff --git a/src/soc/intel/skylake/acpi/ipu.asl b/src/soc/intel/skylake/acpi/ipu.asl index 59028e6..cb97e9c 100644 --- a/src/soc/intel/skylake/acpi/ipu.asl +++ b/src/soc/intel/skylake/acpi/ipu.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/intel/common/block/acpi/acpi/ipu.asl> +#include <soc/intel/common/basecode/acpi/acpi/ipu.asl> /* IPU3 processing system - Device 14, Function 3 */ Device (CIO2) diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl index 9fb027a..5df6b5d 100644 --- a/src/soc/intel/skylake/acpi/lpc.asl +++ b/src/soc/intel/skylake/acpi/lpc.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ // Intel LPC Bus Device - 0:1f.0 -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> Scope (\_SB.PCI0.LPCB) { diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a722144..2d2b48c 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -39,8 +39,8 @@ select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index c7c5446..87e7fa4 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -12,7 +12,7 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index ff683cf..8fb3dda 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -18,7 +18,7 @@ #include "gpio.asl" /* ESPI 0:1f.0 */ -#include <soc/intel/common/block/acpi/acpi/lpc.asl> +#include <soc/intel/common/basecode/acpi/acpi/lpc.asl> /* PCH HDA */ #include "pch_hda.asl" @@ -42,4 +42,4 @@ #include <soc/intel/common/acpi/pci_osc.asl> /* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +#include <soc/intel/common/basecode/acpi/acpi/pmc.asl> diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index d3c3c62..511896a 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -5,7 +5,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1328257..f0643ff 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -11,7 +11,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/smm.h> #include <device/pci.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <hob_iiouds.h> #include <hob_memmap.h> #include <soc/acpi.h> diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index d984d9f..647e369 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -4,7 +4,7 @@ #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> -#include <intelblocks/acpi.h> +#include <intelbasecode/acpi.h> #include <device/pci.h> #include <cbmem.h> #include <cpu/x86/smm.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18ee1a8c5e795f9dbbc086cb6b39fbf59fc1655 Gerrit-Change-Number: 45560 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: Port of Kontron bSC2 COMe module
by Jose Trujillo (Code Review) 07 Aug '23

07 Aug '23

Jose Trujillo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45658 ) Change subject: Port of Kontron bSC2 COMe module ...................................................................... Port of Kontron bSC2 COMe module Change-Id: I2932af6016b044fa807da00acc7b147ef1c7c45e Signed-off-by: JTCEA <ce.autom(a)protonmail.com> --- A src/mainboard/kontron/bSC2/Kconfig A src/mainboard/kontron/bSC2/Kconfig.name A src/mainboard/kontron/bSC2/Makefile.inc A src/mainboard/kontron/bSC2/acpi/ec.asl A src/mainboard/kontron/bSC2/acpi/platform.asl A src/mainboard/kontron/bSC2/acpi/superio.asl A src/mainboard/kontron/bSC2/acpi_tables.c A src/mainboard/kontron/bSC2/board_info.txt A src/mainboard/kontron/bSC2/cmos.default A src/mainboard/kontron/bSC2/cmos.layout A src/mainboard/kontron/bSC2/devicetree.cb A src/mainboard/kontron/bSC2/devicetree.cb.orig A src/mainboard/kontron/bSC2/dsdt.asl A src/mainboard/kontron/bSC2/early_init.c A src/mainboard/kontron/bSC2/gma-mainboard.ads A src/mainboard/kontron/bSC2/gma-mainboard.ads.orig A src/mainboard/kontron/bSC2/gpio.c A src/mainboard/kontron/bSC2/hda_verb.c A src/mainboard/kontron/bSC2/mainboard.c 19 files changed, 1,259 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45658/1 diff --git a/src/mainboard/kontron/bSC2/Kconfig b/src/mainboard/kontron/bSC2/Kconfig new file mode 100644 index 0000000..66a74cd --- /dev/null +++ b/src/mainboard/kontron/bSC2/Kconfig @@ -0,0 +1,61 @@ +if BOARD_KONTRON_bSC2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select USE_OPTION_TABLE + select SUPERIO_SMSC_SMSCSUPERIO + select DRIVERS_PS2_KEYBOARD + select GFX_GMA_PANEL_1_ON_LVDS + select BOOT_DEVICE_SUPPORTS_WRITES + select SMMSTORE + # select NO_POST + +config MAINBOARD_DIR + string + default kontron/bSC2 + +config MAINBOARD_PART_NUMBER + string + default "COMe-bCS2" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 4 + +config CBFS_SIZE + hex + default 0x300000 + +config INCLUDE_CONFIG_FILE + bool + default n + +config CPU_UCODE_BINARIES + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/06-2a-07" + +config DRIVERS_UART_8250IO + bool + default y + +config CONSOLE_CBMEM + bool + default n + +endif diff --git a/src/mainboard/kontron/bSC2/Kconfig.name b/src/mainboard/kontron/bSC2/Kconfig.name new file mode 100644 index 0000000..b0110b6 --- /dev/null +++ b/src/mainboard/kontron/bSC2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_KONTRON_bSC2 + bool "bCS2-COMe" diff --git a/src/mainboard/kontron/bSC2/Makefile.inc b/src/mainboard/kontron/bSC2/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/kontron/bSC2/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/kontron/bSC2/acpi/ec.asl b/src/mainboard/kontron/bSC2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/kontron/bSC2/acpi/ec.asl diff --git a/src/mainboard/kontron/bSC2/acpi/platform.asl b/src/mainboard/kontron/bSC2/acpi/platform.asl new file mode 100644 index 0000000..afb8abb --- /dev/null +++ b/src/mainboard/kontron/bSC2/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/kontron/bSC2/acpi/superio.asl b/src/mainboard/kontron/bSC2/acpi/superio.asl new file mode 100644 index 0000000..8c920eb --- /dev/null +++ b/src/mainboard/kontron/bSC2/acpi/superio.asl @@ -0,0 +1,262 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +#define SIO_ENABLE_COM1 +#define SIO_ENABLE_COM2 +#define SIO_ENABLE_PS2K +#define SIO_ENABLE_PS2M +#define SIO_ENABLE_COM3 +#define SIO_ENABLE_COM4 + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + IQ01, 8, + } + + Name (SFDC, 0) /* Floppy Disk */ + Name (SPPC, 3) /* Parallel Port */ + Name (SSP1, 4) /* Serial Port 1 */ + Name (SSP2, 5) /* Serial Port 2 */ + Name (SKBC, 7) /* Keyboard & Mouse */ + Name (SRRB, 10) /* Runtime Register Block */ + Name (SSP3, 11) /* Serial Port 3 */ + Name (SSP4, 12) /* Serial Port 4 */ + + Method (ENTR, 0, NotSerialized) + { + Store (0x55, SI2E) + } + + Method (EXIT, 0, NotSerialized) + { + Store (0xaa, SI2E) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) + } + Else + { + Return (0x0D) + } + } + + /* Enable an LDN via the activate register */ + Method (SENA, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (One, SACT) + EXIT () + } + + /* Disable an LDN via the activate register */ + Method (SDIS, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (Zero, SACT) + EXIT () + } + +#ifdef SIO_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP1)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + //IRQNoFlags () {4} + IRQ (Edge, ActiveHigh, Exclusive) {4} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + //IRQNoFlags () {4} + IRQ (Edge, ActiveHigh, Exclusive) {4} + }) + } +#endif + +#ifdef SIO_ENABLE_COM2 + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP2)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + //IRQNoFlags () {3} + IRQ (Edge, ActiveHigh, Exclusive) {3} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + //IRQNoFlags () {3} + IRQ (Edge, ActiveHigh, Exclusive) {3} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQNoFlags () {1} + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SKBC)) + } + + Name (_CRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + IRQNoFlags () {12} + }) + } +#endif + +#ifdef SIO_ENABLE_COM3 + Device (COM3) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP3)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + //IRQNoFlags () {5} + IRQ (Edge, ActiveHigh, Exclusive) {5} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + //IRQNoFlags () {5} + IRQ (Edge, ActiveHigh, Exclusive) {5} + }) + } +#endif + +#ifdef SIO_ENABLE_COM4 + Device (COM4) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (ISEN (SSP4)) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x02E0, 0x02E0, 0x08, 0x08) + //IRQNoFlags () {10} + IRQ (Edge, ActiveHigh, Exclusive) {6} + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x02E0, 0x02E0, 0x08, 0x08) + //IRQNoFlags () {10} + IRQ (Edge, ActiveHigh, Exclusive) {6} + }) + } +#endif + +} diff --git a/src/mainboard/kontron/bSC2/acpi_tables.c b/src/mainboard/kontron/bSC2/acpi_tables.c new file mode 100644 index 0000000..b7f2730 --- /dev/null +++ b/src/mainboard/kontron/bSC2/acpi_tables.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> +//#include "thermal.h" + +/* FIXME: check this function. */ +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/kontron/bSC2/board_info.txt b/src/mainboard/kontron/bSC2/board_info.txt new file mode 100644 index 0000000..2b0447b --- /dev/null +++ b/src/mainboard/kontron/bSC2/board_info.txt @@ -0,0 +1,6 @@ +Category: half +ROM protocol: SPI +ROM package: 8-pin SOIC +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/kontron/bSC2/cmos.default b/src/mainboard/kontron/bSC2/cmos.default new file mode 100644 index 0000000..fa9887f --- /dev/null +++ b/src/mainboard/kontron/bSC2/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +gfx_uma_size=128M +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/kontron/bSC2/cmos.layout b/src/mainboard/kontron/bSC2/cmos.layout new file mode 100644 index 0000000..8f6ae54 --- /dev/null +++ b/src/mainboard/kontron/bSC2/cmos.layout @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +385 3 r 0 reserved +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 5 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +401 3 e 9 gfx_uma_size +#404 4 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 10 power_on_after_fail +411 1 e 8 sata_mode +#412 4 r 0 unused + +# coreboot config options: bootloader +416 424 s 0 boot_devices +840 8 h 0 boot_default +848 1 e 7 cmos_defaults_loaded +#851 5 r 0 unused + +# coreboot config options: mainboard specific options +#856 40 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk +#976 8 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +3 0 Fallback +3 1 Normal +5 0 Emergency +5 1 Alert +5 2 Critical +5 3 Error +5 4 Warning +5 5 Notice +5 6 Info +5 7 Debug +5 8 Spew +6 0 Disable +6 1 Enable +6 2 Keep +7 0 No +7 1 Yes +8 0 AHCI +8 1 Compatible +9 0 32M +9 1 64M +9 2 96M +9 3 128M +9 4 160M +9 5 192M +9 6 224M +10 0 Disable +10 1 Enable +10 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 895 984 diff --git a/src/mainboard/kontron/bSC2/devicetree.cb b/src/mainboard/kontron/bSC2/devicetree.cb new file mode 100644 index 0000000..018b72a --- /dev/null +++ b/src/mainboard/kontron/bSC2/devicetree.cb @@ -0,0 +1,126 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "100" + register "gpu_pch_backlight" = "0x13121312" + + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" # SIO Runtime registers I/O range forwarded to LPC + register "gen2_dec" = "0x000403e9" # COM3 I/O range forwarded to LPC + register "gen3_dec" = "0x000402e1" # COM4 I/O range forwarded to LPC + register "gen4_dec" = "0x000403e9" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x1c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x1c2d + end + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x1c10 + end + device pci 1c.1 on # PCIe Port #2: i82574 + subsystemid 0x8086 0x1c12 + end + device pci 1c.2 on # PCIe Port #3: OXPCIE958 + subsystemid 0x8086 0x1c14 + end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6, 0x8086 0x1c1a: JMB368 + device pci 1c.6 off end # PCIe Port #7, 0x8086 0x1c1c: PEX8112 + device pci 1c.7 off end # PCIe Port #8, already in use by GB LAN + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x1c26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x8086 0x1c4f + chip superio/smsc/smscsuperio + device pnp 2e.0 off end # Floppy + device pnp 2e.3 off end # Parallel Port + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS2 Keyboard & Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.a on # Runtime Regs + io 0x60 = 0x0a00 + drq 0xF0 = 0x0b # no 32kHz + end + device pnp 2e.b on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 5 + end + device pnp 2e.c on # COM4 + io 0x60 = 0x2e0 + irq 0x70 = 6 + end + end # smscsuperio + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x1c01 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x1c22 + end + device pci 1f.5 off end # SATA Controller 2, subsystemid 0x8086 0x1c09 + device pci 1f.6 off end # Thermal + + end + device pci 00.0 on # Host bridge + subsystemid 0x8086 0x0104 + end + device pci 01.0 on # PEG + subsystemid 0x8086 0x0101 + end + device pci 02.0 on # iGPU + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/kontron/bSC2/devicetree.cb.orig b/src/mainboard/kontron/bSC2/devicetree.cb.orig new file mode 100644 index 0000000..39214f9 --- /dev/null +++ b/src/mainboard/kontron/bSC2/devicetree.cb.orig @@ -0,0 +1,109 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "100" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x000403e9" + register "gen3_dec" = "0x000402e1" + register "gen4_dec" = "0x000403e9" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x1c3a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x1c2d + end + device pci 1b.0 off # High Definition Audio + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x1c10 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x1c12 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x8086 0x1c14 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x8086 0x1c1a + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x8086 0x1c1c + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x1c26 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge + subsystemid 0x8086 0x1c4f + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x1c01 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x1c22 + end + device pci 1f.5 on # SATA Controller 2 Unsupported PCI device 8086:1c09 + subsystemid 0x8086 0x1c09 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x8086 0x0104 + end + device pci 01.0 on # PEG + subsystemid 0x8086 0x0101 + end + device pci 02.0 on # iGPU + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/kontron/bSC2/dsdt.asl b/src/mainboard/kontron/bSC2/dsdt.asl new file mode 100644 index 0000000..e648a99 --- /dev/null +++ b/src/mainboard/kontron/bSC2/dsdt.asl @@ -0,0 +1,28 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/kontron/bSC2/early_init.c b/src/mainboard/kontron/bSC2/early_init.c new file mode 100644 index 0000000..f53b749 --- /dev/null +++ b/src/mainboard/kontron/bSC2/early_init.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/smscsuperio/smscsuperio.h> + +#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { +/* enabled, power, oc pin */ + { 1, 1, 0 }, /* P0: USB0 */ + { 1, 1, 0 }, /* P1: USB1 */ + { 1, 1, 1 }, /* P2: USB2 */ + { 1, 1, 1 }, /* P3: USB3 */ + { 0, 0, -1 }, /* P4: - */ + { 0, 0, -1 }, /* P5: - */ + { 0, 0, -1 }, /* P6: - */ + { 0, 0, -1 }, /* P7: - */ + { 1, 1, 4 }, /* P8: USB4 */ + { 1, 1, 4 }, /* P9: USB5 */ + { 1, 0, 5 }, /* P10: USB6 */ + { 1, 0, 5 }, /* P11: USB7 */ + { 0, 0, -1 }, /* P12: - */ + { 0, 0, -1 }, /* P13: - */ +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1403); /* COMA, COMB, KBC and LPC 0x2E enabled */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); /* LPC decode ranges COMA=3F8, COMB=2F8 */ +} + +void mainboard_early_init(int s3resume) +{ + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +/* SPD map */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); /* Read Dimm1 RAM settings */ + read_spd(&spd[2], 0x52, id_only); /* Read Dimm2 RAM settings */ +} diff --git a/src/mainboard/kontron/bSC2/gma-mainboard.ads b/src/mainboard/kontron/bSC2/gma-mainboard.ads new file mode 100644 index 0000000..8bfbab6 --- /dev/null +++ b/src/mainboard/kontron/bSC2/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (LVDS, + DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bSC2/gma-mainboard.ads.orig b/src/mainboard/kontron/bSC2/gma-mainboard.ads.orig new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/kontron/bSC2/gma-mainboard.ads.orig @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bSC2/gpio.c b/src/mainboard/kontron/bSC2/gpio.c new file mode 100644 index 0000000..e93e29f --- /dev/null +++ b/src/mainboard/kontron/bSC2/gpio.c @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_LOW, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/kontron/bSC2/hda_verb.c b/src/mainboard/kontron/bSC2/hda_verb.c new file mode 100644 index 0000000..3804740 --- /dev/null +++ b/src/mainboard/kontron/bSC2/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/kontron/bSC2/mainboard.c b/src/mainboard/kontron/bSC2/mainboard.c new file mode 100644 index 0000000..1b9cd36 --- /dev/null +++ b/src/mainboard/kontron/bSC2/mainboard.c @@ -0,0 +1,139 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <console/console.h> +#include <device/pnp_ops.h> +#include <device/smbus_host.h> + +/* SCH3114 */ +#define SIO_RUNTIME_BASE 0x0A00 + +/* CPLD */ +#define CPLD_IDX 0x0A80 +#define CPLD_DATA (CPLD_IDX + 1) +#define I2C_PRER_LO_IDX 0x0B +#define I2C_CTR_IDX 0x0D +#define CFG_CPLD 0x37 + +/* ADT7490 */ +#define SMBUS_IO_BASE 0x0400 +#define ADT7490_ADDRESS 0x2E +#define REG_VENDID 0x3E +#define REG_DEVID2 0x3F +#define PWM1_DUTY_CYCLE 0x30 +#define PECI_TCON_LIMIT 0x3D +#define CONF_REG_1 0x40 +#define PWM1_CONF_REG 0x5C +#define R2_TRAN_PWM3_FREQ 0x61 +#define PWM1_MIN_DUTY_CYCLE 0x64 +#define PWM3_MIN_DUTY_CYCLE 0x66 +#define R2_TEMP_TMIN 0x69 +#define INT_MASK_1 0x74 +#define INT_MASK_2 0x75 +#define THERM_TIMER_LIMIT 0x7A +#define INT_MASK_3 0x82 +#define INT_MASK_4 0x83 + +static u32 smbus_io_base = SMBUS_IO_BASE; +static u32 adt7490_address = ADT7490_ADDRESS; + +#define adt7490_read_byte(reg) do_smbus_read_byte(smbus_io_base, adt7490_address, reg) +#define adt7490_write_byte(reg, val) do_smbus_write_byte(smbus_io_base, adt7490_address, reg, val) + +/* CPLD I/O operations */ +//static u8 cpld_read8(u8 idx) +//{ +// outb(idx, CPLD_IDX); +// return inb(CPLD_DATA); +//} + +//static u16 cpld_read16(u8 idx) +//{ +// return cpld_read8(idx) | (cpld_read8(idx + 1) << 8); +//} + +static void cpld_write8(u8 idx, u8 value) +{ + outb(idx, CPLD_IDX); + outb(value, CPLD_DATA); +} + +static void cpld_write16(u8 idx, u16 value) +{ + cpld_write8(idx, (u8)value); + cpld_write8(idx + 1, (u8)(value >> 8)); +} + +/* SCH3114 SIO GPIOs. */ +static const u16 sio_init_table[] = { // nibble: hi = offset, lo = value + + // GP5x = COM2 function instead of GPIO + 0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604, + + // GP1x = COM3 function instead of GPIO + 0x2305, 0x2404, 0x2505, 0x2605, 0x2705, 0x2904, 0x2A05, 0x2B04, + + // GP6x = COM4 function instead of GPIO + 0x3405, 0x3704, 0x5405, 0x5505, 0x5605, 0x5704, 0x5805, 0x5904, +}; + +static void mainboard_init(struct device *dev) +{ + int i; + /* Init SCH311x SIO GPIOs. */ + printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE); + for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { + u16 val = sio_init_table[i]; + outb((u8)val, SIO_RUNTIME_BASE + (val >> 8)); + } + + /* Init CPLD */ + cpld_write16(I2C_PRER_LO_IDX, 0x020); // I2C Clock prescaler + cpld_write8(I2C_CTR_IDX, 0x80); // I2C Clock control + + /* Init ADT7490 */ + int vendid, devid2; + + vendid = adt7490_read_byte(REG_VENDID); /* Read VEN & DEV ID */ + devid2 = adt7490_read_byte(REG_DEVID2); + + /* If ADT7490 is present, then initialize it, else exit */ + if ((vendid = 0x41) && // Analog Devices + (devid2 & 0xfc) == 0x6c) { // Device ID + + printk(BIOS_DEBUG, "Found ADT7490 at %x:%x\n", smbus_io_base, adt7490_address); + + adt7490_write_byte(PWM1_DUTY_CYCLE, 0x81); // Half Duty + adt7490_write_byte(PECI_TCON_LIMIT, 0x80); // Disabled + adt7490_write_byte(CONF_REG_1, 0x15); // Monitoring and PWM control outputs enabled + adt7490_write_byte(PWM1_CONF_REG, 0x42); // 250ms spin time, Remote 2 temp. controls PWM1 + adt7490_write_byte(R2_TRAN_PWM3_FREQ, 0xB4); // Frequency = 35.3 Hz, low frequency PWM mode, + // 26.67 C parameter. + adt7490_write_byte(PWM1_MIN_DUTY_CYCLE, 0x54); + adt7490_write_byte(PWM3_MIN_DUTY_CYCLE, 0x8C); + adt7490_write_byte(R2_TEMP_TMIN, 0x37); // When the temperature measured exceeds T MIN , the + // appropriate fan runs at minimum speed and + // increases with temperature according to T RANGE. + adt7490_write_byte(INT_MASK_1, 0xFF); // Mask all #SMBALERT + adt7490_write_byte(INT_MASK_2, 0xFF); // Mask all #SMBALERT + adt7490_write_byte(THERM_TIMER_LIMIT, 0xFF); // Avoid unwanted alerts from being generated. + adt7490_write_byte(INT_MASK_3, 0xFF); // Mask all #SMBALERT + adt7490_write_byte(INT_MASK_4, 0xF8); // Mask all #SMBALERT + + } + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/45658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2932af6016b044fa807da00acc7b147ef1c7c45e Gerrit-Change-Number: 45658 Gerrit-PatchSet: 1 Gerrit-Owner: Jose Trujillo Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: src/superio: Add it8987e
by Sergey Larin (Code Review) 07 Aug '23

07 Aug '23

Sergey Larin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38253 ) Change subject: src/superio: Add it8987e ...................................................................... src/superio: Add it8987e Add support for IT8987E SuperIO. Based on it8528e. Currently untested. Signed-off-by: cerg2010cerg2010 <cerg2010cerg2010(a)mail.ru> Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f --- A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 4 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38253/1 diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..b8e3258 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..01e4d3e --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..4e265df --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..dce7a6f --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> + +#include "it8987e.h" + +static void it8987e_init(struct device *dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f Gerrit-Change-Number: 38253 Gerrit-PatchSet: 1 Gerrit-Owner: Sergey Larin <cerg2010cerg2010(a)mail.ru> Gerrit-MessageType: newchange

4 3

← Newer
1
...
4
5
6
7
8
9
10
...
639
Older →

Jump to page:

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021