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Change subject: drivers/wifi/generic: fix package_size to align with WLAN driver
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Primus doesn't have this flag. But other two have this. I can check on Brya as well.
Hi Eric,
Can you apply below for Brya, see if it is printing 3 or 1 ?
diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index 11fc0e084f..743a313144 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -273,6 +273,7 @@ static void sar_emit_ewrd(const struct sar_profile *sar)
* Emit 'Domain Type' + 'Dynamic SAR Enable' + 'Extended SAR sets count'
* + number of bytes for Set#2 & 3 & 4
*/
+ printk(BIOS_INFO, "sar->dsar_set_count = %d\n", sar->dsar_set_count);
package_size = 1 + 1 + 1 + table_size * sar->dsar_set_count;
acpigen_write_package(package_size);
acpigen_write_dword(DOMAIN_TYPE_WIFI);
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Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h
......................................................................
Patch Set 4: Code-Review+1
(3 comments)
File src/mainboard/google/butterfly/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59000/comment/bc7a211b_90a1726e
PS4, Line 16: #define DEVMODE_GPIO 54
DEVMODE_GPIO is unused
File src/mainboard/google/stout/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59000/comment/439de42f_6a8643c3
PS4, Line 79: CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
Does deduplicating this have any side-effects? At least I'd mention this change in the commit message.
File src/mainboard/intel/strago/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59000/comment/de618976_e8491b8f
PS4, Line 11: #define ACTIVE_LOW 0
: #define ACTIVE_HIGH 1
Already defined in <commonlib/coreboot_tables.h>, included through <boot/coreboot_tables.h>
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Change subject: arch/x86: Add a common romstage entry
......................................................................
Patch Set 5:
(9 comments)
File src/arch/x86/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/011bb3fb_1bdb4a7b
PS2, Line 7: static void _romstage_main(void)
> Does this need to be a separate function?
Done
File src/arch/x86/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/f53726cd_ca7173a0
PS5, Line 3: #include <arch/cpu.h>
: #include <console/console.h>
: #include <timestamp.h>
: #include <romstage_common.h>
nit: order includes alphabetically?
File src/include/romstage_common.h:
https://review.coreboot.org/c/coreboot/+/55067/comment/77d6a3c4_6ca35e19
PS5, Line 8: __
nit: remove the leading underscores
File src/include/romstage_common.h:
https://review.coreboot.org/c/coreboot/+/55067/comment/85f4b9da_084f8ade
PS2, Line 3: __ROMSTAGE_COMMON_H
> Identifiers starting with two leading underscores are reserved. […]
Done
File src/soc/amd/cezanne/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/cdff986d_af79a6fe
PS5, Line 4: #include <acpi/acpi.h>
: #include <amdblocks/acpimmio.h>
: #include <amdblocks/memmap.h>
: #include <amdblocks/pmlib.h>
: #include <arch/cpu.h>
: #include <console/console.h>
: #include <fsp/api.h>
: #include <program_loading.h>
: #include <timestamp.h>
Looks like these includes are sorted alphabetically. Would be great if you could preserve this ordering.
https://review.coreboot.org/c/coreboot/+/55067/comment/5f0cc28a_f2f954fd
PS5, Line 16: timestamp_add_now(TS_START_ROMSTAGE);
This needs to be removed
File src/soc/amd/picasso/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/b72f8f45_80cbe59c
PS5, Line 3: #include <acpi/acpi.h>
: #include <amdblocks/memmap.h>
: #include <amdblocks/pmlib.h>
: #include <arch/cpu.h>
: #include <commonlib/helpers.h>
: #include <console/console.h>
: #include <fsp/api.h>
: #include <program_loading.h>
: #include <timestamp.h>
: #include <types.h>
Looks like these includes are sorted alphabetically. Would be great if you could preserve this ordering.
https://review.coreboot.org/c/coreboot/+/55067/comment/69ee4592_ed3b68b1
PS5, Line 17: timestamp_add_now(TS_START_ROMSTAGE);
This needs to be removed
File src/soc/example/min86/romstage.c:
https://review.coreboot.org/c/coreboot/+/55067/comment/8f0ec8bd_2593eab0
PS5, Line 4: #include <arch/cpu.h>
No longer needed
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Change subject: drivers/wifi/generic: fix package_size to align with WLAN driver
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Hi Eric, […]
Primus doesn't have this flag. But other two have this. I can check on Brya as well.
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Change subject: soc/intel/tigerlake/apci: Only use SCM for ChromeOS
......................................................................
Patch Set 13:
(2 comments)
Patchset:
PS12:
> Might have something, just digging now...
Done
File src/soc/intel/tigerlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/58798/comment/4ba78435_9cefa025
PS12, Line 159: *
> nit: line up with the other `*`
Done
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