coreboot-gerrit October 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: Add SHRM firmware support
by Ravi kumar (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49392 to look at the new patch set (#78). Change subject: sc7280: Add SHRM firmware support ...................................................................... sc7280: Add SHRM firmware support SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/include/soc/shrm.h M src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/shrm_load_reset.c 6 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/49392/78 -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 78 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [RFC,WIP] cpu/x86/lapic: Evaluate x2apic_mode just once
by ron minnich (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Kyösti Mälkki. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55198 ) Change subject: [RFC,WIP] cpu/x86/lapic: Evaluate x2apic_mode just once ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: For the future, a bit more information would be helpful. Why does it matter to do this just once? Does it fix a problem? Does it improve something? -- To view, visit https://review.coreboot.org/c/coreboot/+/55198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff4f5dc50999f977eaf9b32e7caebf098a3600fe Gerrit-Change-Number: 55198 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 15:57:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic()
by ron minnich (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Kyösti Mälkki. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55199 ) Change subject: [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic() ...................................................................... Patch Set 12: Code-Review+2 (2 comments) Patchset: PS12: > Very nice! […] ah nvm I was not reading this correctly, I misread. It still seems fine to me, but it would be nice to have someone more knowledgable take a look. PS12: further discussion has convinced me this is fine. I think this text in the commit message could be useful, modified to suit: "Remove code which was only needed for B and C2 stepping of P54C" * See if we have a good local APIC by checking for buggy Pentia, * i.e. all B steppings and the C2 stepping of P54C when using their * integrated APIC (see 11AP erratum in "Pentium Processor * Specification Update"). -- To view, visit https://review.coreboot.org/c/coreboot/+/55199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Gerrit-Change-Number: 55199 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Oct 2021 15:53:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable PCH FIVR support under TPCH device
by Sumeet R Pawnikar (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Tim Wawrzynczak. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58142 ) Change subject: mb/google/brya: Enable PCH FIVR support under TPCH device ...................................................................... mb/google/brya: Enable PCH FIVR support under TPCH device Enable PCH FIVR support under TPCH device for Brya system. Change-Id: Ie5bf9729214eb2222ddc08a55954791e38b92d48 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/58142/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 154f697..3a16ee1 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,6 +19,9 @@ # DPTF enable register "dptf_enable" = "1" + # PCH FIVR enable + register "pch_fivr_enable" = "1" + register "tcc_offset" = "10" # TCC of 90 # Enable heci communication -- To view, visit https://review.coreboot.org/c/coreboot/+/58142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5bf9729214eb2222ddc08a55954791e38b92d48 Gerrit-Change-Number: 58142 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Add PCH FIVR enable support under TPCH device
by Sumeet R Pawnikar (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Patrick Rudolph. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58141 ) Change subject: drivers/intel/dptf: Add PCH FIVR enable support under TPCH device ...................................................................... drivers/intel/dptf: Add PCH FIVR enable support under TPCH device Add PCH FIVR enable support under TPCH device. Change-Id: Ia5eb37d5fd0eb1a4490e810ea802cbecc04ac386 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/dptf.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58141/1 diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index fba73db..e3c1529 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -305,7 +305,17 @@ dptf_write_hid(platform_info->use_eisa_hids, platform_info->tpch_device_hid); acpigen_write_name_string("_STR", DEFAULT_TPCH_STR); acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_TPCH); + acpigen_write_method("_STA", 0); + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("\\PCHE"); + acpigen_emit_byte(ONE_OP); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_else(); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(ZERO_OP); + acpigen_pop_len(); + acpigen_write_method_end(); } static void write_tpch_methods(const struct dptf_platform_info *platform_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/58141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5eb37d5fd0eb1a4490e810ea802cbecc04ac386 Gerrit-Change-Number: 58141 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add enable PCH FIVR entry
by Sumeet R Pawnikar (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58140 ) Change subject: soc/intel/alderlake: Add enable PCH FIVR entry ...................................................................... soc/intel/alderlake: Add enable PCH FIVR entry Add PCH FIVR enable entry for AlderLake based mainboard configuration. Change-Id: I570ef5a741fa96efaee0457815f4ef9808edb10d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/chip.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/58140/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index b28ec12..28739a1 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -272,6 +272,9 @@ /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; + /* Enable PCH FIVR based on mainboard configuration */ + gnvs->pche = config->pch_fivr_enable; + /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 270400b..412cdf5 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -163,6 +163,8 @@ uint8_t TcssD3ColdDisable; /* Enable DPTF support */ int dptf_enable; + /* Enable PCH FIVR support */ + int pch_fivr_enable; /* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; -- To view, visit https://review.coreboot.org/c/coreboot/+/58140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I570ef5a741fa96efaee0457815f4ef9808edb10d Gerrit-Change-Number: 58140 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add enable PCH FIVR entry under GNVS
by Sumeet R Pawnikar (Code Review) 06 Oct '21

06 Oct '21

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58139 ) Change subject: soc/intel/common: Add enable PCH FIVR entry under GNVS ...................................................................... soc/intel/common: Add enable PCH FIVR entry under GNVS Add enable PCH FIVR entry under GNVS Change-Id: I2345e61b6b7afabb8110dd1e9121cb084dadfa40 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58139/1 diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index ab63a5c..a19c3a3 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -25,4 +25,5 @@ A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource , 64, // 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code) + PCHE, 8, // 0x48 - Enable PCH FIVR } diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 5adbdb8..5f1c0ee 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -27,6 +27,7 @@ u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ u64 hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */ + u8 pche; /* 0x48 - Enable PCH FIVR */ }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2345e61b6b7afabb8110dd1e9121cb084dadfa40 Gerrit-Change-Number: 58139 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Add support for PCH methods
by Sumeet R Pawnikar (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57925 to look at the new patch set (#7). Change subject: drivers/intel/dptf: Add support for PCH methods ...................................................................... drivers/intel/dptf: Add support for PCH methods Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/soc/intel/alderlake/dptf.c 3 files changed, 164 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/57925/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/57925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Gerrit-Change-Number: 57925 Gerrit-PatchSet: 7 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe
by Raul Rangel (Code Review) 06 Oct '21

06 Oct '21

Attention is currently required from: Kevin Chiu, Martin Roth, Bhanu Prakash Maiya, Eric Peers, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58135 ) Change subject: mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9 Gerrit-Change-Number: 58135 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 06 Oct 2021 14:59:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Disable unused i2s pins for BT offload
by Sugnan Prabhu S (Code Review) 06 Oct '21

06 Oct '21

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58137 ) Change subject: mb/google/brya: Disable unused i2s pins for BT offload ...................................................................... mb/google/brya: Disable unused i2s pins for BT offload BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/fw_config.c 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/58137/1 diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index 97b460f..17d284a 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -33,22 +33,28 @@ PAD_NC(GPP_S5, NONE), }; -static const struct pad_config i2s_enable_pads[] = { +static const struct pad_config i2s0_enable_pads[] = { PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ +}; + +static const struct pad_config i2s2_enable_pads[] = { PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */ }; -static const struct pad_config i2s_disable_pads[] = { +static const struct pad_config i2s0_disable_pads[] = { PAD_NC(GPP_R0, NONE), PAD_NC(GPP_R1, NONE), PAD_NC(GPP_R2, NONE), PAD_NC(GPP_R3, NONE), +}; + +static const struct pad_config i2s2_disable_pads[] = { PAD_NC(GPP_R4, NONE), PAD_NC(GPP_R5, NONE), PAD_NC(GPP_R6, NONE), @@ -80,7 +86,8 @@ static void enable_i2s(void) { gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); + gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } @@ -88,7 +95,8 @@ { if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); - gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); return; @@ -99,11 +107,13 @@ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); printk(BIOS_INFO, "BT offload enabled\n"); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); } else { printk(BIOS_INFO, "BT offload disabled\n"); - gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads)); + gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads)); gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Gerrit-Change-Number: 58137 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2021