coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2629 discussions

Change in coreboot[master]: nb/intel/nehalem: Introduce macros to reduce indentation level
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36083 ) Change subject: nb/intel/nehalem: Introduce macros to reduce indentation level ...................................................................... nb/intel/nehalem: Introduce macros to reduce indentation level While the indentation of the code is adapted to the new macro's the wrapping is not fixed. A followup commit running this code through clang-format will do that. TEST: build with BUILD_TIMELESS=1, hash of resulting binary is identical before and after. Change-Id: I95358d49b57e771d86a562702403f491a02fe017 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 527 insertions(+), 491 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/36083/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b9d407a..dde51f9 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -50,22 +50,57 @@ #define HECIDEV PCI_DEV(0, 0x16, 0) #define HECIBAR 0x10 -#define FOR_ALL_RANKS \ - for (channel = 0; channel < NUM_CHANNELS; channel++) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ - for (rank = 0; rank < NUM_RANKS; rank++) +#define RANK_IS_POPULATED(info, channel, slot, rank) \ + ((info)->populated_ranks[(channel)][(slot)][(rank)] != 0) -#define FOR_POPULATED_RANKS \ - for (channel = 0; channel < NUM_CHANNELS; channel++) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ - for (rank = 0; rank < NUM_RANKS; rank++) \ - if (info->populated_ranks[channel][slot][rank]) +#define IF_RANK_POPULATED(info, channel, slot, rank) \ + if (RANK_IS_POPULATED(info, channel, slot, rank)) -#define FOR_POPULATED_RANKS_BACKWARDS \ - for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ - for (rank = 0; rank < NUM_RANKS; rank++) \ - if (info->populated_ranks[channel][slot][rank]) +#define FOR_EACH_CHANNEL(channel) \ + for (channel = 0; channel < NUM_CHANNELS; channel++) + +#define FOR_EACH_SLOT(slot) \ + for (slot = 0; slot < NUM_SLOTS; slot++) + +#define FOR_ALL_SLOTS(channel, slot) \ + FOR_EACH_CHANNEL(channel) \ + FOR_EACH_SLOT(slot) + +#define FOR_ALL_POPULATED_SLOTS(info, channel, slot) \ + FOR_ALL_SLOTS(channel, slot) \ + IF_RANK_POPULATED(info, channel, slot, 0) + +#define FOR_EACH_RANK(rank) \ + for (rank = 0; rank < NUM_RANKS; rank++) + +#define FOR_ALL_RANKS(channel, slot, rank) \ + FOR_ALL_SLOTS(channel, slot) \ + FOR_EACH_RANK(rank) + +#define FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \ + FOR_EACH_SLOT(slot) \ + FOR_EACH_RANK(rank) + +#define FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) \ + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \ + IF_RANK_POPULATED(info, channel, slot, rank) + +#define FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) \ + FOR_ALL_RANKS(channel, slot, rank) \ + IF_RANK_POPULATED(info, channel, slot, rank) + +#define FOR_EACH_CHANNEL_BACKWARDS(channel) \ + for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) + +#define FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) \ + FOR_EACH_CHANNEL_BACKWARDS(channel) \ + FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) + +#define FOR_EACH_LANE(lane) \ + for (lane = 0; lane < 8; lane++) + +#define FOR_EACH_LANE_WITH_ECC(lane) \ + for (lane = 0; lane < 9; lane++) /* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */ typedef struct { @@ -315,7 +350,7 @@ program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank) { int lane; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { write_500(info, channel, base + info->training. @@ -363,7 +398,7 @@ int i, lane; for (i = 0; i < 2; i++) - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { write_500(info, channel, info->training.lane_timings[i + 1][channel][slot] @@ -372,24 +407,22 @@ slot, rank), 9, 0); + } write_1d0(1, 0x103, 6, 1); - for (lane = 0; lane < 8; lane++) - write_500(info, channel, - info->training. - lane_timings[0][channel][slot][rank][lane], + FOR_EACH_LANE(lane) { + write_500(info, channel, info->training.lane_timings[0][channel][slot] + [rank][lane], get_timing_register_addr(lane, 0, slot, rank), 9, 0); + } for (i = 0; i < 2; i++) { - for (lane = 0; lane < 8; lane++) - write_500(info, channel, - info->training.lane_timings[i + - 1][channel][slot] - [rank][lane], get_timing_register_addr(lane, - i + 1, - slot, - rank), + FOR_EACH_LANE(lane) { + write_500(info, channel, info->training.lane_timings[i + 1][channel] + [slot] [rank][lane], + get_timing_register_addr(lane, i + 1, slot, rank), 9, 0); + } gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); } @@ -397,7 +430,7 @@ MCHBAR8(0x5ff) = 0x0; MCHBAR8(0x5ff) = 0x80; write_1d0(0x2, 0x142, 3, 1); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); info->training.lane_timings[2][channel][slot][rank][lane] = read_500(info, channel, @@ -413,9 +446,10 @@ { int slot, rank; int res = 0; - for (slot = 0; slot < NUM_SLOTS; slot++) + FOR_EACH_SLOT(slot) { for (rank = 0; rank < NUM_SLOTS; rank++) res += info->populated_ranks[channel][slot][rank]; + } return res; } @@ -465,7 +499,7 @@ const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b }; u32 vd8[2][16]; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { for (j = 0; j < 4; j++) { u32 a = (j == 1) ? 0x29292929 : 0x31313131; u32 lmask = (j == 3) ? 0xffff : 0xffffffff; @@ -559,41 +593,25 @@ /* Find common CAS latency */ supported_cas_latencies = 0x3fe; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - if (info->populated_ranks[channel][slot][0]) - supported_cas_latencies &= - 2 * - (info-> - spd[channel][slot][CAS_LATENCIES_LSB] | - (info-> - spd[channel][slot][CAS_LATENCIES_MSB] << - 8)); + FOR_ALL_POPULATED_SLOTS(info, channel, slot) { + supported_cas_latencies &= 2 * (info->spd[channel][slot][CAS_LATENCIES_LSB] + | (info->spd[channel][slot][CAS_LATENCIES_MSB] + << 8)); + } max_clock_index = min(3, info->max_supported_clock_speed_index); cycletime = min_cycletime[max_clock_index]; cas_latency_time = min_cas_latency_time[max_clock_index]; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - if (info->populated_ranks[channel][slot][0]) { - unsigned timebase; - timebase = - 1000 * - info-> - spd[channel][slot][TIMEBASE_DIVIDEND] / - info->spd[channel][slot][TIMEBASE_DIVISOR]; - cycletime = - max(cycletime, - timebase * - info->spd[channel][slot][CYCLETIME]); - cas_latency_time = - max(cas_latency_time, - timebase * - info-> - spd[channel][slot][CAS_LATENCY_TIME]); - } + FOR_ALL_POPULATED_SLOTS(info, channel, slot) { + unsigned timebase; + timebase = 1000 * info->spd[channel][slot][TIMEBASE_DIVIDEND] / + info->spd[channel][slot][TIMEBASE_DIVISOR]; + cycletime = max(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); + cas_latency_time = max(cas_latency_time, timebase * + info->spd[channel][slot][CAS_LATENCY_TIME]); + } if (cycletime > min_cycletime[0]) die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!"); for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { @@ -633,128 +651,125 @@ extended_silicon_revision = info->silicon_revision; if (info->silicon_revision == 0) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) + FOR_ALL_SLOTS(channel, slot) { + if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3) + extended_silicon_revision = 4; + } + + FOR_EACH_CHANNEL(channel) { + FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) { + int card_timing_2; + if (!info->populated_ranks[channel][slot][rank]) + continue; + + FOR_EACH_LANE_WITH_ECC(lane) { + int tm_reg; + int card_timing; + + card_timing = 0; if ((info-> - spd[channel][slot][MODULE_TYPE] & 0xF) == - 3) - extended_silicon_revision = 4; - - for (channel = 0; channel < NUM_CHANNELS; channel++) { - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_SLOTS; rank++) { - int card_timing_2; - if (!info->populated_ranks[channel][slot][rank]) - continue; - - for (lane = 0; lane < 9; lane++) { - int tm_reg; - int card_timing; - - card_timing = 0; - if ((info-> - spd[channel][slot][MODULE_TYPE] & - 0xF) == 3) { - int reference_card; - reference_card = - info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & - 0x1f; - if (reference_card == 3) - card_timing = - u16_ffd1188[0][lane] - [info-> - clock_speed_index]; - if (reference_card == 5) - card_timing = - u16_ffd1188[1][lane] - [info-> - clock_speed_index]; - } - - info->training. - lane_timings[0][channel][slot][rank] - [lane] = - u8_FFFD1218[info-> - clock_speed_index]; - info->training. - lane_timings[1][channel][slot][rank] - [lane] = 256; - - for (tm_reg = 2; tm_reg < 4; tm_reg++) - info->training. - lane_timings[tm_reg] - [channel][slot][rank][lane] - = - u8_FFFD1240[channel] - [extended_silicon_revision] - [lane][2 * slot + - rank][info-> - clock_speed_index] - + info->max4048[channel] - + - u8_FFFD0C78[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][slot] - [rank][info-> - clock_speed_index] - + card_timing; - for (tm_reg = 0; tm_reg < 4; tm_reg++) - write_500(info, channel, - info->training. - lane_timings[tm_reg] - [channel][slot][rank] - [lane], - get_timing_register_addr - (lane, tm_reg, slot, - rank), 9, 0); + spd[channel][slot][MODULE_TYPE] & + 0xF) == 3) { + int reference_card; + reference_card = + info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1f; + if (reference_card == 3) + card_timing = + u16_ffd1188[0][lane] + [info-> + clock_speed_index]; + if (reference_card == 5) + card_timing = + u16_ffd1188[1][lane] + [info-> + clock_speed_index]; } - card_timing_2 = 0; - if (!(extended_silicon_revision != 4 - || (info-> - populated_ranks_mask[channel] & 5) == - 5)) { - if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & 0x1F) - == 3) - card_timing_2 = - u16_FFFE0EB8[0][info-> - clock_speed_index]; - if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & 0x1F) - == 5) - card_timing_2 = - u16_FFFE0EB8[1][info-> - clock_speed_index]; - } + info->training. + lane_timings[0][channel][slot][rank] + [lane] = + u8_FFFD1218[info-> + clock_speed_index]; + info->training. + lane_timings[1][channel][slot][rank] + [lane] = 256; - for (i = 0; i < 3; i++) + for (tm_reg = 2; tm_reg < 4; tm_reg++) + info->training. + lane_timings[tm_reg] + [channel][slot][rank][lane] + = + u8_FFFD1240[channel] + [extended_silicon_revision] + [lane][2 * slot + + rank][info-> + clock_speed_index] + + info->max4048[channel] + + + u8_FFFD0C78[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][slot] + [rank][info-> + clock_speed_index] + + card_timing; + for (tm_reg = 0; tm_reg < 4; tm_reg++) write_500(info, channel, - (card_timing_2 + - info->max4048[channel] - + - u8_FFFD0EF8[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][info-> - clock_speed_index]), - u16_fffd0c50[i][slot][rank], - 8, 1); - write_500(info, channel, - (info->max4048[channel] + - u8_FFFD0C78[channel] - [extended_silicon_revision][info-> - mode4030 - [channel]] - [slot][rank][info-> - clock_speed_index]), - u16_fffd0c70[slot][rank], 7, 1); + info->training. + lane_timings[tm_reg] + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, tm_reg, slot, + rank), 9, 0); } + + card_timing_2 = 0; + if (!(extended_silicon_revision != 4 + || (info-> + populated_ranks_mask[channel] & 5) == + 5)) { + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 3) + card_timing_2 = + u16_FFFE0EB8[0][info-> + clock_speed_index]; + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 5) + card_timing_2 = + u16_FFFE0EB8[1][info-> + clock_speed_index]; + } + + for (i = 0; i < 3; i++) + write_500(info, channel, + (card_timing_2 + + info->max4048[channel] + + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> + clock_speed_index]), + u16_fffd0c50[i][slot][rank], + 8, 1); + write_500(info, channel, + (info->max4048[channel] + + u8_FFFD0C78[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]] + [slot][rank][info-> + clock_speed_index]), + u16_fffd0c70[slot][rank], 7, 1); + } if (!info->populated_ranks_mask[channel]) continue; for (i = 0; i < 3; i++) @@ -828,12 +843,12 @@ some_delay_3_ps_rounded = 0; extended_silicon_revision = info->silicon_revision; if (!info->silicon_revision) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - if ((info-> - spd[channel][slot][MODULE_TYPE] & 0xF) == - 3) - extended_silicon_revision = 4; + FOR_ALL_SLOTS(channel, slot) { + if ((info-> + spd[channel][slot][MODULE_TYPE] & 0xF) == + 3) + extended_silicon_revision = 4; + } if (info->board_lane_delay[7] < 5) info->board_lane_delay[7] = 5; info->revision_flag_1 = 2; @@ -914,7 +929,7 @@ || (count_ranks_in_channel(info, 1) == 2)) ? 2 : 3; } - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { int max_of_unk; int min_of_unk_2; @@ -945,67 +960,66 @@ [i]; else unk1 = 0; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) { - int a = 0; - int b = 0; + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + int a = 0; + int b = 0; - if (!info-> - populated_ranks[channel][slot] - [rank]) - continue; - if (extended_silicon_revision == 4 - && (info-> - populated_ranks_mask[channel] & - 5) != 5) { + if (!info-> + populated_ranks[channel][slot] + [rank]) + continue; + if (extended_silicon_revision == 4 + && (info-> + populated_ranks_mask[channel] & + 5) != 5) { + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1F) == 3) { + a = u16_ffd1178[0] + [info-> + clock_speed_index]; + b = u16_fe0eb8[0][info-> + clock_speed_index]; + } else if ((info-> spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & - 0x1F) == 3) { - a = u16_ffd1178[0] - [info-> - clock_speed_index]; - b = u16_fe0eb8[0][info-> - clock_speed_index]; - } else - if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] - & 0x1F) == 5) { + [REFERENCE_RAW_CARD_USED] + & 0x1F) == 5) { a = u16_ffd1178[1] - [info-> - clock_speed_index]; + [info-> + clock_speed_index]; b = u16_fe0eb8[1][info-> clock_speed_index]; } - } - min_of_unk_2 = min(min_of_unk_2, a); - min_of_unk_2 = min(min_of_unk_2, b); - if (rank == 0) { - sum += a; - count++; - } - { - int t; - t = b + - u8_FFFD0EF8[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][info-> - clock_speed_index]; - if (unk1 >= t) - max_of_unk = - max(max_of_unk, - unk1 - t); - } } + min_of_unk_2 = min(min_of_unk_2, a); + min_of_unk_2 = min(min_of_unk_2, b); + if (rank == 0) { + sum += a; + count++; + } + { + int t; + t = b + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> + clock_speed_index]; + if (unk1 >= t) + max_of_unk = + max(max_of_unk, + unk1 - t); + } + } { int t = - u8_FFFD17E0[channel] - [extended_silicon_revision][info-> - mode4030 - [channel]] - [info->clock_speed_index] + min_of_unk_2; + u8_FFFD17E0[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]] + [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) max_of_unk = max(max_of_unk, unk1 - t); } @@ -1080,7 +1094,7 @@ } else { write_recovery = 6; } - FOR_POPULATED_RANKS { + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { auto_self_refresh &= (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1; self_refresh_temperature &= @@ -1097,7 +1111,7 @@ total_rank = 0; - for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) { + FOR_EACH_CHANNEL_BACKWARDS(channel) { int rtt, rtt_wr = MR2_RTT_WR_DISABLED; int rzq_reg58e; @@ -1126,31 +1140,31 @@ MCHBAR16(0x58e + (channel << 10)) = rzq_reg58e | 0x82; MCHBAR16(0x590 + (channel << 10)) = 0x1282; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info->populated_ranks[channel][slot][rank]) { - jedec_read(info, channel, slot, rank, - total_rank, 0x28, - rtt_wr | (info-> - clock_speed_index - << 3) - | (auto_self_refresh << 6) | - (self_refresh_temperature << - 7)); - jedec_read(info, channel, slot, rank, - total_rank, 0x38, 0); - jedec_read(info, channel, slot, rank, - total_rank, 0x18, - rtt | MR1_ODS34OHM); - jedec_read(info, channel, slot, rank, - total_rank, 6, - (dll_on << 12) | - (write_recovery << 9) - | ((info->cas_latency - 4) << - 4) | MR0_BT_INTERLEAVED | - MR0_DLL_RESET_ON); - total_rank++; - } + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info->populated_ranks[channel][slot][rank]) { + jedec_read(info, channel, slot, rank, + total_rank, 0x28, + rtt_wr | (info-> + clock_speed_index + << 3) + | (auto_self_refresh << 6) | + (self_refresh_temperature << + 7)); + jedec_read(info, channel, slot, rank, + total_rank, 0x38, 0); + jedec_read(info, channel, slot, rank, + total_rank, 0x18, + rtt | MR1_ODS34OHM); + jedec_read(info, channel, slot, rank, + total_rank, 6, + (dll_on << 12) | + (write_recovery << 9) + | ((info->cas_latency - 4) << + 4) | MR0_BT_INTERLEAVED | + MR0_DLL_RESET_ON); + total_rank++; + } + } } } @@ -1160,7 +1174,7 @@ unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ unsigned int channel_0_non_interleaved; - FOR_ALL_RANKS { + FOR_ALL_RANKS(channel, slot, rank) { if (info->populated_ranks[channel][slot][rank]) { total_mb[channel] += pre_jedec ? 256 : (256 << info-> @@ -1257,7 +1271,7 @@ } if (MCHBAR8(0x2ca9) & 1) some_delay_3_half_cycles = 3; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32_OR(0x220 + (channel << 10), 0x18001117); MCHBAR32(0x224 + (channel << 10)) = (info->max_slots_used_in_channel - 1) | @@ -1314,7 +1328,7 @@ cas_latency_derived = info->cas_latency - info->clock_speed_index + 2; if (info->clock_speed_index > 1) cas_latency_derived++; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x240 + (channel << 10)) = ((info->clock_speed_index == 0) * 0x11000) | 0x1002100 | ((2 + info->clock_speed_index) << 4) | @@ -1518,13 +1532,14 @@ if (capid0[2] & 2) { info->silicon_revision = 0; info->max_supported_clock_speed_index = 2; - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { if (info->populated_ranks[channel][0][0] && (info->spd[channel][0][MODULE_TYPE] & 0xf) == 3) { info->silicon_revision = 2; info->max_supported_clock_speed_index = 1; } + } } else { switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1)) { case 1: @@ -1556,19 +1571,19 @@ return; for (tm = 0; tm < 4; tm++) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) - write_500(info, channel, - info-> - cached_training-> - lane_timings[tm] - [channel][slot][rank] - [lane], - get_timing_register_addr - (lane, tm, slot, - rank), 9, 0); + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + write_500(info, channel, + info-> + cached_training-> + lane_timings[tm] + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, tm, slot, + rank), 9, 0); + } + } write_1d0(info->cached_training->reg_178, 0x178, 7, 1); write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); } @@ -1577,10 +1592,10 @@ { int channel, slot, rank, lane, i; printk(RAM_DEBUG, "Timings:\n"); - FOR_POPULATED_RANKS { + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank); - for (lane = 0; lane < 9; lane++) { + FOR_EACH_LANE_WITH_ECC(lane) { printk(RAM_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { printk(RAM_DEBUG, "%x (%x) ", @@ -1610,16 +1625,19 @@ int channel, slot, rank, lane, i; train = info->training; - FOR_POPULATED_RANKS for (lane = 0; lane < 9; lane++) - for (i = 0; i < 4; i++) - train.lane_timings[i][channel][slot][rank][lane] = - read_500(info, channel, - get_timing_register_addr(lane, i, slot, - rank), 9); + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + for (i = 0; i < 4; i++) + train.lane_timings[i][channel][slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr(lane, i, slot, + rank), 9); + } + } train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { u32 reg32; reg32 = MCHBAR32((channel << 10) + 0x274); train.reg274265[channel][0] = reg32 >> 16; @@ -1912,27 +1930,28 @@ { int i, channel, slot, rank, lane; for (i = 0; i < 2; i++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) - info->training. - lane_timings[0][i][slot][rank][lane] - = 32; + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + info->training. + lane_timings[0][i][slot][rank][lane] + = 32; + } + } - for (i = 1; i < 4; i++) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) { - info->training. - lane_timings[i][channel] - [slot][rank][lane] = - read_500(info, channel, - get_timing_register_addr - (lane, i, slot, - rank), 9) - + (i == 1) * 11; // !!!! - } + for (i = 1; i < 4; i++) { + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + info->training. + lane_timings[i][channel] + [slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr + (lane, i, slot, + rank), 9) + + (i == 1) * 11; // !!!! + } + } + } } @@ -2186,7 +2205,7 @@ { int lane; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { int is_fail = (fail_mask >> lane) & 1; switch (state[lane]) { case BEFORE_USABLE: @@ -2250,7 +2269,7 @@ if (!first_run) { int is_all_ok = 1; - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (timings[reg_178][channel][slot][rank][lane]. smallest == timings[reg_178][channel][slot][rank][lane]. @@ -2261,6 +2280,7 @@ largest = 0; is_all_ok = 0; } + } if (is_all_ok) { for (i = 0; i < 8; i++) state[i] = COMPLETE; @@ -2280,7 +2300,7 @@ if (reg1b3) { write_1d0(0, 0x1b3, 6, 1); write_1d0(0, 0x1a3, 6, 1); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { if (state[lane] == COMPLETE) { timings[reg_178][channel][slot][rank][lane]. smallest = @@ -2299,7 +2319,7 @@ } if (!first_run) { - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (state[lane] == COMPLETE) { write_500(info, channel, timings[reg_178][channel][slot][rank] @@ -2324,7 +2344,7 @@ num_successfully_checked[lane] = 0; } else num_successfully_checked[lane] = -1; - + } do { u8 failmask = 0; for (i = 0; i < niter; i++) { @@ -2338,7 +2358,7 @@ 1); } MCHBAR32_OR(0xfb0, 0x00030000); - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { if (timings[reg_178][channel] @@ -2395,11 +2415,12 @@ num_successfully_checked[lane] ++; } + } } while (!check_bounded(num_successfully_checked, 2)) ; - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { if (state[lane] == COMPLETE) { write_500(info, channel, timings[reg_178][channel][slot][rank] @@ -2424,6 +2445,7 @@ num_successfully_checked[lane] = 0; } else num_successfully_checked[lane] = -1; + } do { int failmask = 0; @@ -2439,7 +2461,7 @@ } MCHBAR32_OR(0xfb0, 0x00030000); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { if (timings[reg_178][channel] @@ -2502,7 +2524,7 @@ while (!check_bounded(num_successfully_checked, 3)) ; - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { write_500(info, channel, info->training. lane_timings[0][channel][slot][rank][lane], @@ -2537,28 +2559,30 @@ write_1d0(val, 0x10b, 6, 1); - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 9; lane++) { - u16 reg_500; - reg_500 = read_500(info, channel, - get_timing_register_addr(lane, 0, slot, - rank), 9); - if (val == 1) { - if (lut16[info->clock_speed_index] <= reg_500) - reg_500 -= lut16[info->clock_speed_index]; - else - reg_500 = 0; - } else { - reg_500 += lut16[info->clock_speed_index]; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { + u16 reg_500; + reg_500 = read_500(info, channel, + get_timing_register_addr(lane, 0, slot, + rank), 9); + if (val == 1) { + if (lut16[info->clock_speed_index] <= reg_500) + reg_500 -= lut16[info->clock_speed_index]; + else + reg_500 = 0; + } else { + reg_500 += lut16[info->clock_speed_index]; + } + write_500(info, channel, reg_500, + get_timing_register_addr(lane, 0, slot, rank), 9, 1); } - write_500(info, channel, reg_500, - get_timing_register_addr(lane, 0, slot, rank), 9, 1); } } static void set_ecc(int onoff) { int channel; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { u8 t; t = MCHBAR8((channel << 10) + 0x5f8); if (onoff) @@ -2585,12 +2609,13 @@ { int lane; - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { write_500(info, channel, info->training. lane_timings[type][channel][slot][rank][lane], get_timing_register_addr(lane, type, slot, rank), 9, 0); + } } static void @@ -2610,11 +2635,12 @@ memset(count, 0, sizeof(count)); - for (lane = 0; lane < 8; lane++) + FOR_EACH_LANE(lane) { write_500(info, channel, info->training. lane_timings[2][channel][slot][rank][lane] + 32, get_timing_register_addr(lane, 3, slot, rank), 9, 1); + } for (timing_offset = 0; !validate_state(state) && timing_offset < 64; timing_offset++) { @@ -2634,7 +2660,7 @@ if (!validate_state(state)) die("Couldn't discover DRAM timings (1)\n"); - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { u8 bias = 0; if (info->silicon_revision) { @@ -2758,13 +2784,15 @@ reg178 < reg178_max[info->clock_speed_index]; reg178 += reg178_step[info->clock_speed_index]) { margin[reg178] = -1; - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { - int curmargin = - timings[reg178][channel][slot][rank][lane].largest - - timings[reg178][channel][slot][rank][lane]. - smallest + 1; - if (curmargin < margin[reg178]) - margin[reg178] = curmargin; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE(lane) { + int curmargin = + timings[reg178][channel][slot][rank][lane].largest - + timings[reg178][channel][slot][rank][lane]. + smallest + 1; + if (curmargin < margin[reg178]) + margin[reg178] = curmargin; + } } if (margin[reg178] >= STANDARD_MIN_MARGIN) { u16 weight; @@ -2816,29 +2844,28 @@ if (!info->cached_training) return 0; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 8 + info->use_ecc; lane++) { - u16 cached_value, estimation_value; - cached_value = - info->cached_training-> - lane_timings[1][channel][slot][rank] - [lane]; - if (cached_value >= 0x18 - && cached_value <= 0x1E7) { - estimation_value = - info->training. - lane_timings[1][channel] - [slot][rank][lane]; - if (estimation_value < - cached_value - 24) - return 0; - if (estimation_value > - cached_value + 24) - return 0; - } - } + FOR_ALL_RANKS(channel, slot, rank) { + for (lane = 0; lane < 8 + info->use_ecc; lane++) { + u16 cached_value, estimation_value; + cached_value = + info->cached_training-> + lane_timings[1][channel][slot][rank] + [lane]; + if (cached_value >= 0x18 + && cached_value <= 0x1E7) { + estimation_value = + info->training. + lane_timings[1][channel] + [slot][rank][lane]; + if (estimation_value < + cached_value - 24) + return 0; + if (estimation_value > + cached_value + 24) + return 0; + } + } + } return 1; } @@ -2885,9 +2912,9 @@ it still works whereas with j == 1 we check that just outside of bound we fail. */ - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { for (i = 0; i < 2; i++) { - for (lane = 0; lane < 8; lane++) { + FOR_EACH_LANE(lane) { write_500(info, channel, info->cached_training-> timing2_bounds[channel][slot] @@ -2982,7 +3009,7 @@ return 1; fail: - FOR_POPULATED_RANKS { + FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) { write_500_timings_type(info, channel, slot, rank, 1); write_500_timings_type(info, channel, slot, rank, 2); write_500_timings_type(info, channel, slot, rank, 3); @@ -3026,7 +3053,7 @@ } set_ecc(0); - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { int i; write_500_timings_type(info, channel, slot, rank, 0); @@ -3051,9 +3078,8 @@ reg_178 += reg178_step[info->clock_speed_index]) { totalrank = 0; set_178(reg_178); - for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) { + FOR_EACH_CHANNEL_BACKWARDS(channel) { + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { memset(&timings[reg_178][channel][slot] [rank][0].smallest, 0, 16); if (info-> @@ -3067,34 +3093,37 @@ timings); totalrank++; } - } + } + } } reg178_center = choose_reg178(info, timings); - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { - info->training.timing_bounds[0][channel][slot][rank][lane]. - smallest = - timings[info->training. - reg178_smallest][channel][slot][rank][lane]. - smallest; - info->training.timing_bounds[0][channel][slot][rank][lane]. - largest = - timings[info->training. - reg178_smallest][channel][slot][rank][lane].largest; - info->training.timing_bounds[1][channel][slot][rank][lane]. - smallest = - timings[info->training. - reg178_largest][channel][slot][rank][lane].smallest; - info->training.timing_bounds[1][channel][slot][rank][lane]. - largest = - timings[info->training. - reg178_largest][channel][slot][rank][lane].largest; - info->training.timing_offset[channel][slot][rank][lane] = - info->training.lane_timings[1][channel][slot][rank][lane] - - - info->training.lane_timings[0][channel][slot][rank][lane] + - 64; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE(lane) { + info->training.timing_bounds[0][channel][slot][rank][lane]. + smallest = + timings[info->training. + reg178_smallest][channel][slot][rank][lane]. + smallest; + info->training.timing_bounds[0][channel][slot][rank][lane]. + largest = + timings[info->training. + reg178_smallest][channel][slot][rank][lane].largest; + info->training.timing_bounds[1][channel][slot][rank][lane]. + smallest = + timings[info->training. + reg178_largest][channel][slot][rank][lane].smallest; + info->training.timing_bounds[1][channel][slot][rank][lane]. + largest = + timings[info->training. + reg178_largest][channel][slot][rank][lane].largest; + info->training.timing_offset[channel][slot][rank][lane] = + info->training.lane_timings[1][channel][slot][rank][lane] + - + info->training.lane_timings[0][channel][slot][rank][lane] + + 64; + } } if (info->silicon_revision == 1 @@ -3108,19 +3137,18 @@ reg_178 <= reg178_center + 18; reg_178 += 18) { totalrank = 0; set_178(reg_178); - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) { - if (info-> - populated_ranks[1][slot][rank]) { - train_ram_at_178(info, 1, slot, - rank, - totalrank, - reg_178, 0, - niter, - timings); - totalrank++; - } + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info-> + populated_ranks[1][slot][rank]) { + train_ram_at_178(info, 1, slot, + rank, + totalrank, + reg_178, 0, + niter, + timings); + totalrank++; } + } } ranks_after_channel1 = totalrank; @@ -3128,18 +3156,18 @@ reg_178 <= reg178_center + 12; reg_178 += 12) { totalrank = ranks_after_channel1; set_178(reg_178); - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info-> - populated_ranks[0][slot][rank]) { - train_ram_at_178(info, 0, slot, - rank, - totalrank, - reg_178, 0, - niter, - timings); - totalrank++; - } + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info-> + populated_ranks[0][slot][rank]) { + train_ram_at_178(info, 0, slot, + rank, + totalrank, + reg_178, 0, + niter, + timings); + totalrank++; + } + } } } else { @@ -3147,7 +3175,7 @@ reg_178 <= reg178_center + 12; reg_178 += 12) { totalrank = 0; set_178(reg_178); - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { train_ram_at_178(info, channel, slot, rank, totalrank, reg_178, 0, niter, timings); @@ -3157,25 +3185,27 @@ } set_178(reg178_center); - FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { - u16 tm0; + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { + FOR_EACH_LANE(lane) { + u16 tm0; - tm0 = - choose_training(info, channel, slot, rank, lane, timings, - reg178_center); - write_500(info, channel, tm0, - get_timing_register_addr(lane, 0, slot, rank), 9, 1); - write_500(info, channel, - tm0 + - info->training. - lane_timings[1][channel][slot][rank][lane] - - info->training. - lane_timings[0][channel][slot][rank][lane], - get_timing_register_addr(lane, 1, slot, rank), 9, 1); + tm0 = + choose_training(info, channel, slot, rank, lane, timings, + reg178_center); + write_500(info, channel, tm0, + get_timing_register_addr(lane, 0, slot, rank), 9, 1); + write_500(info, channel, + tm0 + + info->training. + lane_timings[1][channel][slot][rank][lane] - + info->training. + lane_timings[0][channel][slot][rank][lane], + get_timing_register_addr(lane, 1, slot, rank), 9, 1); + } } totalrank = 0; - FOR_POPULATED_RANKS_BACKWARDS { + FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) { try_timing_offsets(info, channel, slot, rank, totalrank); totalrank++; } @@ -3525,14 +3555,14 @@ if (info->revision < 8) return 256; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info->populated_ranks[channel][slot][rank]) - for (lane = 0; lane < 8 + info->use_ecc; lane++) - ret = max(ret, read_500(info, channel, - get_timing_register_addr - (lane, 0, slot, - rank), 9)); + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + if (info->populated_ranks[channel][slot][rank]) + for (lane = 0; lane < 8 + info->use_ecc; lane++) + ret = max(ret, read_500(info, channel, + get_timing_register_addr + (lane, 0, slot, + rank), 9)); + } return ret; } @@ -3546,7 +3576,7 @@ delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); info->training.reg2ca9_bit0 = 0; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); delay_d_ps = @@ -3634,7 +3664,7 @@ { int channel; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32((channel << 10) + 0x274) = (info->cached_training->reg274265[channel][0] << 16) | info->cached_training->reg274265[channel][1]; @@ -3768,8 +3798,8 @@ memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); info.use_ecc = 1; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) { + FOR_EACH_CHANNEL(channel) { + FOR_EACH_SLOT(slot) { int v; int try; int addr; @@ -3846,16 +3876,17 @@ 0x18)) info.use_ecc = 0; } + } gav(0x55); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { int v = 0; - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - v |= info. - populated_ranks[channel][slot][rank] - << (2 * slot + rank); + FOR_ALL_RANKS_ON_CHANNEL(slot, rank) { + v |= info. + populated_ranks[channel][slot][rank] + << (2 * slot + rank); + } info.populated_ranks_mask[channel] = v; } @@ -4265,10 +4296,11 @@ MCHBAR32(0x160) = 0x5ffffff; MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!! MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!! - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x260 + (channel << 10)) = 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + } + FOR_EACH_CHANNEL(channel) { MCHBAR16(0x31c + (channel << 10)) = 0x101; MCHBAR16(0x360 + (channel << 10)) = 0x909; MCHBAR16(0x3a4 + (channel << 10)) = 0x101; @@ -4296,7 +4328,7 @@ populated_ranks[0] [0][0]) << 0), 0x1d1, 3, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR16(0x38e + (channel << 10)) = 0x5f5f; MCHBAR16(0x3d2 + (channel << 10)) = 0x5f5f; } @@ -4312,13 +4344,14 @@ write_1d0(0x0, 0xeb, 3, 1); write_1d0(0x0, 0xf3, 6, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (lane = 0; lane < 9; lane++) { + FOR_EACH_CHANNEL(channel) { + FOR_EACH_LANE_WITH_ECC(lane) { u16 addr = 0x125 + get_lane_offset(0, 0, lane); u8 a; a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!! write_500(&info, channel, a, addr, 6, 1); } + } udelay(1000); @@ -4333,11 +4366,9 @@ } int tm; info.training = *info.cached_training; - for (tm = 0; tm < 4; tm++) - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - for (lane = 0; lane < 9; lane++) + for (tm = 0; tm < 4; tm++) { + FOR_ALL_RANKS(channel, slot, rank) { + FOR_EACH_LANE_WITH_ECC(lane) { write_500(&info, channel, info.training. @@ -4349,6 +4380,9 @@ (lane, tm, slot, rank), 9, 0); + } + } + } write_1d0(info.cached_training->reg_178, 0x178, 7, 1); write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); } @@ -4374,9 +4408,10 @@ read_1d0(0x328, 6); // = 0xfa018080 // !!!! write_1d0(7, 0x328, 6, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 8 : 0); + } read_1d0(0x116, 4); // = 0x4040432 // !!!! write_1d0(2, 0x116, 4, 1); @@ -4410,9 +4445,10 @@ 1); } - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 1); + } rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!! MCHBAR32(0x144); // !!!! @@ -4424,9 +4460,10 @@ read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!! write_1d0(4, 0x328, 6, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 9 : 0); + } MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30) | (info.populated_ranks[0][0][0] << 29); @@ -4439,15 +4476,16 @@ read_1d0(0x14b, 7); // = 0x810231b0 // !!!! write_1d0(0x35, 0x14b, 7, 1); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { set_4cf(&info, channel, info.populated_ranks[channel][0][0] ? 0xb : 0x2); + } set_334(1); MCHBAR8(0x1e8) = 0x4; - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { write_500(&info, channel, 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2, 1); @@ -4468,27 +4506,26 @@ MCHBAR8(0x271) = 0x2; MCHBAR8(0x671) = 0x2; MCHBAR8(0x1e8) = 0x4; - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; + } MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000); MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000); - for (channel = 0; channel < NUM_CHANNELS; channel++) + FOR_EACH_CHANNEL(channel) { MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 | ((info.populated_ranks_mask[channel] & 3) << 20)); + } if (!s3resume) jedec_init(&info); int totalrank = 0; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info.populated_ranks[channel][slot][rank]) { - jedec_read(&info, channel, slot, rank, - totalrank, 0xa, 0x400); - totalrank++; - } + FOR_ALL_POPULATED_RANKS(&info, channel, slot, rank) { + jedec_read(&info, channel, slot, rank, + totalrank, 0xa, 0x400); + totalrank++; + } MCHBAR8(0x12c) = 0x9f; @@ -4496,7 +4533,7 @@ MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! if (!s3resume) { - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; MCHBAR16(0x298 + (channel << 10)) = @@ -4523,15 +4560,14 @@ MCHBAR32(0x584) = 0xfffff; MCHBAR32(0x984) = 0xfffff; - for (channel = 0; channel < NUM_CHANNELS; channel++) - for (slot = 0; slot < NUM_SLOTS; slot++) - for (rank = 0; rank < NUM_RANKS; rank++) - if (info. - populated_ranks[channel][slot] - [rank]) - config_rank(&info, s3resume, - channel, slot, - rank); + FOR_ALL_RANKS(channel, slot, rank) { + if (info. + populated_ranks[channel][slot] + [rank]) + config_rank(&info, s3resume, + channel, slot, + rank); + } MCHBAR8(0x243) = 0x1; MCHBAR8(0x643) = 0x1; @@ -4545,7 +4581,7 @@ /* end */ if (s3resume) { - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; MCHBAR16(0x298 + (channel << 10)) = @@ -4627,7 +4663,7 @@ MCHBAR32(0x20) = 0x33001; } - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32_AND(0x220 + (channel << 10), ~0x7770); if (info.max_slots_used_in_channel == 1) MCHBAR16_OR(0x237 + (channel << 10), 0x0201); @@ -4654,7 +4690,7 @@ MCHBAR32(0x210) = (al << 16) | 0x20; } - for (channel = 0; channel < NUM_CHANNELS; channel++) { + FOR_EACH_CHANNEL(channel) { MCHBAR32(0x288 + (channel << 10)) = 0x70605040; MCHBAR32(0x28c + (channel << 10)) = 0xfffec080; MCHBAR32(0x290 + (channel << 10)) = 0x282091c | -- To view, visit https://review.coreboot.org/c/coreboot/+/36083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95358d49b57e771d86a562702403f491a02fe017 Gerrit-Change-Number: 36083 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35821 ) Change subject: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table ...................................................................... [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table There is no explicit dependency on an option table since the reboot counter and the normal/fallback byte is at a fixed offset. I don't feel strongly about imposing this... Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35821/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 502e774..9d26692 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -255,6 +255,7 @@ bool "Always load fallback" config BOOTBLOCK_NORMAL + depends on USE_OPTION_TABLE select CONFIGURABLE_CBFS_PREFIX bool "Switch to normal if CMOS says so" -- To view, visit https://review.coreboot.org/c/coreboot/+/35821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Gerrit-Change-Number: 35821 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35823 ) Change subject: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes ...................................................................... [RFC]arch/x86: Only allow normal and fallback cbfs prefixes Using other cbfsprefixes is errorprone: It requires a properly formatted cbfs file to be present (an error in the cbfsfile will render the system unbootable) and to correctly enter the cbfs prefix in menuconfig. Therefore remove this functionality that merely allows to use different names. Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/bootblock_normal.c 2 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35823/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..5b2a615 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -48,13 +48,10 @@ config CBFS_PREFIX_NORMAL bool "normal" -config CBFS_PREFIX_DIY - bool "Define your own cbfs prefix" - endchoice config CBFS_PREFIX - string "CBFS prefix to use" if CBFS_PREFIX_DIY + string default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK default "normal" if CBFS_PREFIX_NORMAL help diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 905ecb2..c55eda2 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -16,18 +16,9 @@ #include <pc80/mc146818rtc.h> #include <halt.h> -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - static void main(unsigned long bist) { u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; if (boot_cpu()) { bootblock_mainboard_init(); @@ -44,20 +35,15 @@ boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - unsigned long entry; if (boot_mode) { - entry = findstage(normal_candidate); + entry = findstage("normal/romstage"); if (entry) call(entry, bist); } - entry = findstage(get_fallback(normal_candidate)); + entry = findstage("fallback/romstage"); if (entry) call(entry, bist); -- To view, visit https://review.coreboot.org/c/coreboot/+/35823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Gerrit-Change-Number: 35823 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [WIP]Makefile.inc: Add Macro to generate cbfs int files
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33353 Change subject: [WIP]Makefile.inc: Add Macro to generate cbfs int files ...................................................................... [WIP]Makefile.inc: Add Macro to generate cbfs int files Add the makefile function 'add-cbfs-int' to generate cbfs files containing a little endian integer. Adding cbfs files containing a 64 bit is usually done with cbfstool add-int, but this requires the coreboot.rom image to be already build which clutters the Makefile. Instead add a method to cleanly generate the cbfsfile containing a 64bit little endian int which integrates better with the rest of the makefile. Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33353/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..d0f47e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -788,6 +788,20 @@ $(call cbfs-add-cmd-for-region,$(1),$(2)) endef +# add-cbfs-int (little endian) +# $(call add-cbfs-int, +# integer +# cbfs-file-name) +define add-cbfs-int + $(eval tmp_int:=$(shell mktemp -u int_file.XXXX)) + $(eval $(obj)/$(tmp_int): + echo -n -e $$$$(printf "%016x" $$$$(($(1))) \ + | sed -re "s/(..)(..)(..)(..)(..)(..)(..)(..)/\\\x\8\\\x\7\\\x\6\\\x\5\\\x\4\\\x\3\\\x\2\\\x\1/") > $$@) + cbfs-files-y += $(2) + $(2)-file := $(obj)/$(tmp_int) + $(2)-type := raw +endef + # list of files to add (using their file system names, not CBFS names), # for dependencies etc. prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) @@ -1064,18 +1078,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efa..24eeba6 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -110,6 +110,18 @@ bootorder-type := raw endif +# Add SeaBIOS PS2 timeout file +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_PS2_TIMEOUT),etc/ps2-keyboard-spinup)) +endif +endif + +# Add SeaBIOS Sercon port file +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_SERCON_PORT_ADDR),etc/sercon-port)) +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/33353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Gerrit-Change-Number: 33353 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 2

Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 ) Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage ...................................................................... [TESTONLY]nb/intel/x4x: Cache cbmem in romstage Probably not a good idea to avoid eviction in romstage. TESTED: works fine on P5QL-EM. Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/raminit.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e24..6665eb0 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -27,6 +27,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8013af9..e8729fb 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -33,6 +33,7 @@ #include <mrc_cache.h> #include <timestamp.h> #include <types.h> +#include <cpu/x86/mtrr.h> #include "iomap.h" #include "x4x.h" @@ -718,6 +719,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); if (!fast_boot) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, -- To view, visit https://review.coreboot.org/c/coreboot/+/37213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Gerrit-Change-Number: 37213 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub
by Arthur Heymans (Code Review) 11 Apr '22

11 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37289 ) Change subject: cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub ...................................................................... cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub This adds a check for LAPIC base twice. One very early check when the CPU is still executing in real mode checks if the LAPIC base is inside the region [smmbase,smmbase + SMM_DEFAULT_SIZE). This cannot use anything but a hardcoded size since even accessing the relocatable parameters is impossible in the state of the CPU. The actual SMI handler is located above smmbase + SMM_DEFAULT_SIZE and before jumping to it the LAPIC base is checked against the whole SMM region. Given that we have a working stack at this point, this is done in C code. UNTESTED. Change-Id: I49927c4f4218552b732bac8aae551d845ad7f079 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/sinkhole.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 4 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37289/1 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..b94f11e 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -45,6 +45,7 @@ postcar-y += tseg_region.c smmstub-y += smm_stub.S +smmstub-y += sinkhole.c smm-y += smm_module_handler.c diff --git a/src/cpu/x86/smm/sinkhole.c b/src/cpu/x86/smm/sinkhole.c new file mode 100644 index 0000000..773549c --- /dev/null +++ b/src/cpu/x86/smm/sinkhole.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/lapic_def.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> + +const extern struct smm_runtime smm_runtime; + +/* Don't try to recover because, if somebody tried to do shenanigans like + these, we have to expect more. */ +void mitigate_sinkhole(void) +{ + msr_t lapic_base_msr = rdmsr(LAPIC_BASE_MSR); + uintptr_t lapic_base = lapic_base_msr.lo & LAPIC_BASE_MSR_ADDR_MASK; + + const uintptr_t smm_end = smm_runtime.smbase + smm_runtime.smm_size; + + if (lapic_base > smm_runtime.smbase && lapic_base < smm_end) { + printk(BIOS_EMERG, "Wrong LAPIC base detected! dying...\n"); + asm("ud2"); + } +} diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 304ea4b..1d39ae1 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -22,6 +22,7 @@ */ #include <cpu/x86/cr.h> +#include <cpu/x86/lapic_def.h> .code32 .section ".module_parameters", "aw", @progbits @@ -39,6 +40,7 @@ fxsave_area_size: .long 0 /* struct smm_runtime begins here. */ +.global smm_runtime smm_runtime: smbase: .long 0 @@ -63,10 +65,51 @@ (CR0_CD | CR0_NW | CR0_PG | CR0_AM | CR0_WP | \ CR0_NE | CR0_TS | CR0_EM | CR0_MP) +#define SMM_DEFAULT_SIZE 0x10000 + .text .code16 .global _start _start: +#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) + /* Check if the LAPIC register block overlaps with SMM. + * This block needs to work without data accesses because they + * may be routed into the LAPIC register block. + * Code accesses, on the other hand, are never routed to LAPIC, + * which is what makes this work in the first place. + * This is a mitigation against the sinkhole vulnerability + * possible on pre sandy bridge Intel hardware. + */ + mov $LAPIC_BASE_MSR, %ecx + rdmsr + and $(~0xfff), %eax + sub $_start, %eax + /* This might cover a bit more than needed but in the case that + this is a stub to the relocated, permanent handler it should + cover some parts of the permanent handler too, so no harm is + done. In the case that this is a stub to a relocation handler + coreboot did something horribly wrong if LAPIC is here. + This has to be 'hardcoded' as the CPU is running in real mode + at this point so it cannot access any relocatable variable. */ + cmp $SMM_DEFAULT_SIZE, %eax + ja untampered_lapic +1: + /* emit "Crash" on serial */ + mov $(CONFIG_TTYS0_BASE), %dx + mov $'C', %al + out %al, (%dx) + mov $'r', %al + out %al, (%dx) + mov $'a', %al + out %al, (%dx) + mov $'s', %al + out %al, (%dx) + mov $'h', %al + out %al, (%dx) + /* now crash for real */ + ud2 +untampered_lapic: +#endif movl $(smm_relocate_gdt), %ebx lgdtl (%ebx) @@ -174,6 +217,12 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) + /* Now that we have a stack, check for against lapic base in + C code before jumping to the permanent handler */ + call mitigate_sinkhole +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2e3c639..884d5cb 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -89,6 +89,9 @@ /* SMM Runtime helpers. */ +/* SMM Runtime sinkhole mitigation check */ +void mitigate_sinkhole(void); + /* Entry point for SMM modules. */ asmlinkage void smm_handler_start(void *params); -- To view, visit https://review.coreboot.org/c/coreboot/+/37289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49927c4f4218552b732bac8aae551d845ad7f079 Gerrit-Change-Number: 37289 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: cpu/x86/smm: SMM module loader version 2
by Rocky Phagura (Code Review) 08 Apr '22

08 Apr '22

Rocky Phagura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43684 ) Change subject: cpu/x86/smm: SMM module loader version 2 ...................................................................... cpu/x86/smm: SMM module loader version 2 Xeon-SP a Skylake Scalable Processor can have 36 CPU threads(18 cores). Current coreboot SMM is unable to handle more than ~32 CPU threads. This patch introduces a version 2 of the SMM module loader which addresses this problem. Having two versions of the SMM module loader prevents any issues to current projects. Future Xeon-SP products will be using this version of the SMM loader. Subsequent patches will enable board specifc functionality for Xeon-SP. The reason for moving to version 2 is the state save area begins to encroach upon the smi handling code when more than 32 CPU threads are in the system. This can cause system hangs, reboots, etc. The second change is related to staggered entry points with simple near jumps. In the current loader, near jumps will not work because the CPU is jumping within the same code segment. In version 2, "far" address jumps are necessary therefore protected mode must is enabled first. The SMM layout and how the CPUs are staggered are documented in the code. By making the modifications above, this allows the smm module loader to expand easily as more CPU threads are added. TEST=build for Tiogapass platform under OCP mainboard. Enable the following in Kconfig. select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON_BLOCK_SMM select SMM_TSEG select HAVE_SMI_HANDLER select ACPI_INTEL_HARDWARE_SLEEP_VALUES Debug console will show all 36 cores relocated. Further tested by generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all cores entering and exiting SMM properly. In addition, booted to Linux 5.4 kernel and observed no issues during mp init. Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/smm_module_loaderv2.c M src/include/cpu/x86/smm.h 4 files changed, 678 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43684/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5394cd0..b3a16bc 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -121,6 +121,14 @@ endif +config X86_SMM_LOADER_VERSION2 + bool + default n + depends on HAVE_SMI_HANDLER + help + This option enables SMM module loader that works with server + platforms which may contain more than 32 CPU threads. + config SMM_LAPIC_REMAP_MITIGATION bool default y if NORTHBRIDGE_INTEL_I945 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index dbe567a..1273a6c 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -1,6 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_X86_SMM_LOADER_VERSION2),y) +ramstage-y += smm_module_loaderv2.c +else ramstage-y += smm_module_loader.c +endif ramstage-y += smi_trigger.c ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c new file mode 100644 index 0000000..d1ccec0 --- /dev/null +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -0,0 +1,648 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <rmodule.h> +#include <cpu/x86/smm.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <security/intel/stm/SmmStm.h> +test +#define FXSAVE_SIZE 512 +#define SMM_CODE_SEGMENT_SIZE 0x10000 +/* FXSAVE area during relocation. While it may not be strictly needed the + SMM stub code relies on the FXSAVE area being non-zero to enable SSE + instructions within SMM mode. */ +static uint8_t fxsave_area_relocation[CONFIG_MAX_CPUS][FXSAVE_SIZE] +__attribute__((aligned(16))); + +/* + * Components that make up the SMRAM: + * 1. Save state - the total save state memory used + * 2. Stack - stacks for the CPUs in the SMM handler + * 3. Stub - SMM stub code for calling into handler + * 4. Handler - C-based SMM handler. + * + * The components are assumed to consist of one consecutive region. + */ + +/* These parameters are used by the SMM stub code. A pointer to the params + * is also passed to the C-base handler. */ +struct smm_stub_params { + u32 stack_size; + u32 stack_top; + u32 c_handler; + u32 c_handler_arg; + u32 fxsave_area; + u32 fxsave_area_size; + struct smm_runtime runtime; +} __packed; + +/* + * The stub is the entry point that sets up protected mode and stacks for each + * CPU. It then calls into the SMM handler module. It is encoded as an rmodule. + */ +extern unsigned char _binary_smmstub_start[]; + +/* Per CPU minimum stack size. */ +#define SMM_MINIMUM_STACK_SIZE 32 + +struct cpu_smm_info { + uint8_t active; + unsigned int smbase; + unsigned int entry; + unsigned int ss_start; + unsigned int code_start; + unsigned int code_end; +}; +struct cpu_smm_info cpus[CONFIG_MAX_CPUS] = { 0 }; + +/* + * This method creates a map of all the CPU entry points, save state locations + * and the beginning and end of code segments for each CPU. This map is used + * during relocation to properly align as many CPUs that can fit into the SMRAM + * region. For more information on how SMRAM works, refer to the latest Intel + * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the + * following regions: + * +-----------------+ Top of SMRAM + * | | <- MSEG, FXSAVE + * +-----------------+ + * | common | + * | smi handler | 64K + * | | + * +-----------------+ + * | CPU 0 code seg | + * +-----------------+ + * | CPU 1 code seg | + * +-----------------+ + * | CPU x code seg | + * +-----------------+ + * | | + * | | + * +-----------------+ + * | stacks | + * +-----------------+ <- START of SMRAM + * + * The code below checks when a code segment is full and begins placing the remainder + * CPUs in the lower segments. The entry point for each CPU is smbase + 8000 + * and save state is smbase + 0x8000 + (0x8000 - state save size). Save state + * area grows downward into the CPUs entry point. Therefore staggering too many + * CPUs in one 32K block will corrupt CPU0's entry code as the save states move + * downward. + * input : smbase of first CPU (all other CPUs + * will go below this address) + * input : num_cpus in the system. The map will + * be created from 0 to num_cpus. + */ +static int smm_create_map(unsigned int smbase, unsigned int num_cpus, + const struct smm_loader_params *params) +{ + unsigned int i; + struct rmodule smm_stub; + unsigned int ss_size = params->per_cpu_save_state_size, stub_size; + unsigned int smm_entry_offset = params->smm_main_entry_offset; + unsigned int seg_count = 0, segments = 0, available; + unsigned int cpus_in_segment = 0; + unsigned int base = smbase; + + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) + printk(BIOS_ERR, "%s : unable to get SMM module size\n", __func__); + + stub_size = rmodule_memory_size(&smm_stub); + /* How many CPUs can fit into one segment? */ + available = 0xFFFF - smm_entry_offset - ss_size - stub_size; + if (available > 0) { + cpus_in_segment = available/ss_size; + /* minimum segments needed will always be 1*/ + segments = num_cpus / cpus_in_segment + 1; + printk(BIOS_DEBUG, + "%s: cpus in one segment %d\n", __func__, cpus_in_segment); + printk(BIOS_DEBUG, + "%s: min # of segments needed %d\n", __func__, segments); + } else { + printk(BIOS_ERR, + "%s: not enough space in SMM to setup all CPUs\n", __func__); + return -1; + } + + if (sizeof(cpus)/sizeof(struct cpu_smm_info) < cpus_in_segment * segments) { + printk(BIOS_ERR, + "%s: more CPUs than originally configured for\n", __func__); + return -1; + } + + for (i = 0; i < num_cpus; i++) { + cpus[i].smbase = base; + cpus[i].entry = base + smm_entry_offset; + cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); + cpus[i].code_start = cpus[i].entry; + cpus[i].code_end = cpus[i].entry + stub_size; + cpus[i].active = 1; + base -= ss_size; + seg_count++; + if (seg_count >= cpus_in_segment) { + base -= smm_entry_offset; + seg_count = 0; + } + } + + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + seg_count = 0; + for (i = 0; i < num_cpus; i++) { + printk(BIOS_DEBUG, "CPU 0x%x\n", i); + printk(BIOS_DEBUG, + " smbase 0x%x entry 0x%x\n", + cpus[i].smbase, cpus[i].entry); + printk(BIOS_DEBUG, + " ss_start 0x%x code_end 0x%x\n", + cpus[i].ss_start, cpus[i].code_end); + seg_count++; + if (seg_count >= cpus_in_segment) { + printk(BIOS_DEBUG, + "-------------NEW CODE SEGMENT --------------\n"); + seg_count = 0; + } + } + } + return 1; +} + +/* + * This method expects the smm relocation map to be complete. + * This method does not read any HW registers, it simply uses a + * map that was created during SMM setup. + * input: cpu_num - cpu number which is used as an index into the + * map to return the smbase + */ +int smm_get_cpu_smbase(unsigned int cpu_num) +{ + if (cpu_num < CONFIG_MAX_CPUS) { + if (cpus[cpu_num].active) + return cpus[cpu_num].smbase; + } + return 0; +} + +/* + * This method assumes that at least 1 CPU has been set up from + * which it will place other CPUs below its smbase ensuring that + * save state does not clobber the first CPUs init code segment. The init + * code which is the smm stub code is the same for all CPUs. They enter + * smm, setup stacks (based on their apic id), enter protected mode + * and then jump to the common smi handler. The stack is allocated + * at the beginning of smram (aka tseg base, not smbase). The stack + * pointer for each CPU is calculated by using its apic id + * (code is in smm_stub.s) + * Each entry point will now have the same stub code which, sets up the CPU + * stack, enters protected mode and then jumps to the smi handler. It is + * important to enter protected mode before the jump because the "jump to + * address" might be larger than the 20bit address supported by real mode. + * SMI entry right now is in real mode. + * input: smbase - this is the smbase of the first cpu not the smbase + * where tseg starts (aka smram_start). All CPUs code segment + * and stack will be below this point except for the common + * SMI handler which is one segment above + * input: num_cpus - number of cpus that need relocation including + * the first CPU (though its code is already loaded) + * input: top of stack (stacks work downward by default in Intel HW) + * output: return -1, if runtime smi code could not be installed. In + * this case SMM will not work and any SMI's generated will + * cause a CPU shutdown or general protection fault becuause + * the appropriate smi handling code was not installed + */ +static void smm_place_entry_code(unsigned int smbase, unsigned int num_cpus, + unsigned int stack_top, const struct smm_loader_params *params) +{ + unsigned int i; + unsigned int size; + if (smm_create_map(smbase, num_cpus, params)) { + /* + * Ensure there was enough space and the last CPUs smbase + * did not encroach upon the stack. Stack top is smram start + * + size of stack. + */ + if (cpus[num_cpus].active) { + if (cpus[num_cpus - 1].smbase + + params->smm_main_entry_offset < stack_top) { + printk(BIOS_ERR, + "%s : need more stack space, stack encroachment\n", + __func__); + printk(BIOS_ERR, "%s : smbase %x, stack_top %x\n", + __func__, cpus[num_cpus].smbase, stack_top); + return; + } + } + } else { + printk(BIOS_ERR, "%s : unable to place smm entry code\n", __func__); + return; + } + + printk(BIOS_INFO, "%s : smbase %x, stack_top %x\n", + __func__, cpus[num_cpus-1].smbase, stack_top); + + /* start at 1, the first CPU stub code is already there */ + size = cpus[0].code_end - cpus[0].code_start; + for (i = 1; i < num_cpus; i++) { + memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); + printk(BIOS_DEBUG, + "SMM Module: placing smm entry code at 0x%x, cpu # 0x%x\n", + cpus[i].code_start, i); + printk(BIOS_DEBUG, "%s copying from 0x%x to 0x%x 0x%x bytes\n", + __func__, cpus[0].code_start, cpus[i].code_start, size); + } + return; +} + +/* + * Place stacks in base -> base + size region, but ensure the stacks don't + * overlap the staggered entry points. + */ +static void *smm_stub_place_stacks(char *base, size_t size, + struct smm_loader_params *params) +{ + size_t total_stack_size; + char *stacks_top; + + /* If stack space is requested assume the space lives in the lower + * half of SMRAM. */ + total_stack_size = params->per_cpu_stack_size * + params->num_concurrent_stacks; + printk(BIOS_DEBUG, "%s cpus: %x : stack space: needed -> %x\n", + __func__, (int)params->num_concurrent_stacks, + (int)total_stack_size); + printk(BIOS_DEBUG, " available -> %x : per_cpu_stack_size : %x\n", + (int)size, (int)params->per_cpu_stack_size); + + /* There has to be at least one stack user. */ + if (params->num_concurrent_stacks < 1) + return NULL; + + /* Total stack size cannot fit. */ + if (total_stack_size > size) + return NULL; + + /* Stacks extend down to SMBASE */ + stacks_top = &base[total_stack_size]; + printk(BIOS_DEBUG, "%s : exit, stack_top %x\n", __func__, (int)stacks_top); + + return stacks_top; +} + +/* + * Place the staggered entry points for each CPU. The entry points are + * staggered by the per CPU SMM save state size extending down from + * SMM_ENTRY_OFFSET. + */ +static void smm_stub_place_staggered_entry_points(char *base, + const struct smm_loader_params *params, const struct rmodule *smm_stub) +{ + size_t stub_entry_offset; + + stub_entry_offset = rmodule_entry_offset(smm_stub); + /* Each CPU now has its own stub code, which enters protected mode, + * sets up the stack, and then jumps to common SMI handler + */ + if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { + smm_place_entry_code((int)base, params->num_concurrent_save_states, + (int)params->stack_top, params); + } +} + +/* + * The stub setup code assumes it is completely contained within the + * default SMRAM size (0x10000) for the default SMI handler (entry at + * 0x30000), but no assumption should be made for the permanent SMI handler. + * The placement of CPU entry points for permanent handler are determined + * by the number of CPUs in the system and the amount of SMRAM. + * There are potentially 3 regions to place + * within the default SMRAM size: + * 1. Save state areas + * 2. Stub code + * 3. Stack areas + * + * The save state and stack areas are treated as contiguous for the number of + * concurrent areas requested. The save state always lives at the top of the + * the CPUS smbase (and the entry point is at offset 0x8000. This allows only a certain + * number of CPUs with staggered entry points until the save state area comes + * down far enough to overwrite/corrupt the entry code (stub code). Therefore, + * an SMM map is created to avoid this corruption, see smm_create_map above. + * This module setup code works for the default SMM handler setup and the + * permanent SMM handler. + */ +static int smm_module_setup_stub(void *smbase, size_t smm_size, + struct smm_loader_params *params, + void *fxsave_area) +{ + size_t total_save_state_size; + size_t smm_stub_size; + size_t stub_entry_offset; + char *smm_stub_loc; + void *stacks_top; + size_t size; + char *base; + size_t i; + struct smm_stub_params *stub_params; + struct rmodule smm_stub; + unsigned int total_size_all; + base = smbase; + size = smm_size; + + /* The number of concurrent stacks cannot exceed CONFIG_MAX_CPUS. */ + if (params->num_concurrent_stacks > CONFIG_MAX_CPUS) { + printk(BIOS_ERR, "%s : not enough stacks\n", __func__); + return -1; + } + + /* Fail if can't parse the smm stub rmodule. */ + if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { + printk(BIOS_ERR, "%s : unable to parse smm stub\n", __func__); + return -1; + } + + /* Adjust remaining size to account for save state. */ + total_save_state_size = params->per_cpu_save_state_size * + params->num_concurrent_save_states; + if (total_save_state_size > size) { + printk(BIOS_ERR, + "%s:more state save space needed:need -> %x:available->%x\n", + __func__, (int)total_save_state_size, (int)size); + return -1; + } + + size -= total_save_state_size; + + /* The save state size encroached over the first SMM entry point. */ + if (size <= params->smm_main_entry_offset) { + printk(BIOS_ERR, "%s:encroachment over SMM entry point\n", __func__); + printk(BIOS_ERR, "%s:state save size: %x : smm_entry_offset -> %x\n", + __func__, (int)size, params->smm_main_entry_offset); + return -1; + } + + /* Need a minimum stack size and alignment. */ + if (params->per_cpu_stack_size <= SMM_MINIMUM_STACK_SIZE || + (params->per_cpu_stack_size & 3) != 0) { + printk(BIOS_ERR, "%s : need minimum stack size\n", __func__); + return -1; + } + + smm_stub_loc = NULL; + smm_stub_size = rmodule_memory_size(&smm_stub); + stub_entry_offset = rmodule_entry_offset(&smm_stub); + + /* Put the stub at at the main entry point */ + smm_stub_loc = &base[params->smm_main_entry_offset]; + + /* Stub is too big to fit. */ + if (smm_stub_size > (size - params->smm_main_entry_offset)) { + printk(BIOS_ERR, "%s : stub is too big to fit\n", __func__); + return -1; + } + + /* The stacks, if requested, live in the lower half of SMRAM space + * for default handler, but for relocated handler it lives at the beginning + * of SMRAM which is TSEG base + */ + size = params->num_concurrent_stacks*params->per_cpu_stack_size; + stacks_top = smm_stub_place_stacks((char *)params->smram_start, size, params); + if (stacks_top == NULL) { + printk(BIOS_ERR, "%s : not enough space for stacks\n", __func__); + printk(BIOS_ERR, "%s : ....need -> %x : available -> %x\n", __func__, + (int)base, (int)size); + return -1; + } + params->stack_top = stacks_top; + /* Load the stub. */ + if (rmodule_load(smm_stub_loc, &smm_stub)) { + printk(BIOS_ERR, "%s : load module failed\n", __func__); + return -1; + } + + smm_stub_place_staggered_entry_points(base, params, &smm_stub); + + /* Setup the parameters for the stub code. */ + stub_params = rmodule_parameters(&smm_stub); + stub_params->stack_top = (uintptr_t)stacks_top; + stub_params->stack_size = params->per_cpu_stack_size; + stub_params->c_handler = (uintptr_t)params->handler; + stub_params->c_handler_arg = (uintptr_t)params->handler_arg; + stub_params->fxsave_area = (uintptr_t)fxsave_area; + stub_params->fxsave_area_size = FXSAVE_SIZE; + stub_params->runtime.smbase = (uintptr_t)smbase; + stub_params->runtime.smm_size = smm_size; + stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + stub_params->runtime.num_cpus = params->num_concurrent_stacks; + + printk(BIOS_DEBUG, "%s : stack_end = 0x%x\n", + __func__, (int)stub_params->runtime.smbase); + printk(BIOS_DEBUG, + "%s : stack_top = 0x%x\n", __func__, (int)stub_params->stack_top); + printk(BIOS_DEBUG, "%s : stack_size = 0x%x\n", + __func__, (int)stub_params->stack_size); + printk(BIOS_DEBUG, "%s : runtime.smbase = 0x%x\n", + __func__, (int)stub_params->runtime.smbase); + printk(BIOS_DEBUG, "%s : runtime.start32_offset = 0x%x\n", __func__, + (int)stub_params->runtime.start32_offset); + printk(BIOS_DEBUG, "%s : runtime.smm_size = 0x%x\n", + __func__, (int)smm_size); + printk(BIOS_DEBUG, "%s : per_cpu_save_state_size = 0x%x\n", + __func__, (int)stub_params->runtime.save_state_size); + printk(BIOS_DEBUG, "%s : num_cpus = 0x%x\n", __func__, + (int)stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s : total_save_state_size = 0x%x\n", + __func__, (int)(stub_params->runtime.save_state_size* + stub_params->runtime.num_cpus)); + total_size_all = (int)stub_params->stack_size + + (int)(stub_params->runtime.save_state_size* + stub_params->runtime.num_cpus); + printk(BIOS_DEBUG, "%s : total_size_all = 0x%x\n", __func__, + total_size_all); + + /* Initialize the APIC id to CPU number table to be 1:1 */ + for (i = 0; i < params->num_concurrent_stacks; i++) + stub_params->runtime.apic_id_to_cpu[i] = i; + + /* Allow the initiator to manipulate SMM stub parameters. */ + params->runtime = &stub_params->runtime; + + printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", + smm_stub_loc, params->handler, params->handler_arg); + return 0; +} + +/* + * smm_setup_relocation_handler assumes the callback is already loaded in + * memory. i.e. Another SMM module isn't chained to the stub. The other + * assumption is that the stub will be entered from the default SMRAM + * location: 0x30000 -> 0x40000. + */ +int smm_setup_relocation_handler(struct smm_loader_params *params) +{ + void *smram = (void *)(SMM_DEFAULT_BASE); + printk(BIOS_SPEW, "%s: enter\n", __func__); + /* There can't be more than 1 concurrent save state for the relocation + * handler because all CPUs default to 0x30000 as SMBASE. */ + if (params->num_concurrent_save_states > 1) + return -1; + + /* A handler has to be defined to call for relocation. */ + if (params->handler == NULL) + return -1; + + /* Since the relocation handler always uses stack, adjust the number + * of concurrent stack users to be CONFIG_MAX_CPUS. */ + if (params->num_concurrent_stacks == 0) + params->num_concurrent_stacks = CONFIG_MAX_CPUS; + + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + params->smram_start = SMM_DEFAULT_BASE; + params->smram_end = SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE; + return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, + params, fxsave_area_relocation); + printk(BIOS_SPEW, "%s: exit\n", __func__); +} + +/* + *The SMM module is placed within the provided region in the following + * manner: + * +-----------------+ <- smram + size + * | BIOS resource | + * | list (STM) | + * +-----------------+ + * | fxsave area | + * +-----------------+ + * | smi handler | + * | ... | + * +-----------------+ <- cpu0 + * | stub code | <- cpu1 + * | stub code | <- cpu2 + * | stub code | <- cpu3, etc + * | | + * | | + * | | + * | stacks | + * +-----------------+ <- smram start + + * It should be noted that this algorithm will not work for + * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm + * expects a region large enough to encompass the handler and stacks + * as well as the SMM_DEFAULT_SIZE. + */ +int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) +{ + struct rmodule smm_mod; + size_t total_stack_size; + size_t handler_size; + size_t module_alignment; + size_t alignment_size; + size_t fxsave_size; + void *fxsave_area; + size_t total_size = 0; + char *base; + + if (size <= SMM_DEFAULT_SIZE) + return -1; + + /* Load main SMI handler at the top of SMRAM + * everything else will go below + */ + base = smram; + base += size; + params->smram_start = (uintptr_t)smram; + params->smram_end = params->smram_start + size; + params->smm_main_entry_offset = SMM_ENTRY_OFFSET; + + /* Fail if can't parse the smm rmodule. */ + if (rmodule_parse(&_binary_smm_start, &smm_mod)) + return -1; + + /* Clear SMM region */ + if (CONFIG(DEBUG_SMI)) + memset(smram, 0xcd, size); + + total_stack_size = params->per_cpu_stack_size * + params->num_concurrent_stacks; + total_size += total_stack_size; + /* Stacks are the base of SMRAM */ + params->stack_top = smram + total_stack_size; + + /* MSEG starts at the top of SMRAM and works down */ + if (CONFIG(STM)) { + base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + } + + /* FXSAVE goes below MSEG */ + if (CONFIG(SSE)) { + fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks; + fxsave_area = base - fxsave_size; + base -= fxsave_size; + total_size += fxsave_size; + } else { + fxsave_size = 0; + fxsave_area = NULL; + } + + + handler_size = rmodule_memory_size(&smm_mod); + base -= handler_size; + total_size += handler_size; + module_alignment = rmodule_load_alignment(&smm_mod); + alignment_size = module_alignment - + ((uintptr_t)base % module_alignment); + if (alignment_size != module_alignment) { + handler_size += alignment_size; + base += alignment_size; + } + + printk(BIOS_DEBUG, + "%s : total_smm_space_needed 0x%x, available -> 0x%x\n", + __func__, (int)total_size, (int)size); + + /* Does the required amount of memory exceed the SMRAM region size? */ + if (total_size > size) { + printk(BIOS_ERR, + "%s : need more SMRAM\n", __func__); + return -1; + } + if (handler_size > SMM_CODE_SEGMENT_SIZE) { + printk(BIOS_ERR, "%s : increase SMM_CODE_SEGMENT_SIZE: handler_size = 0x%0x\n", + __func__, (int)handler_size); + return -1; + } + + if (rmodule_load(base, &smm_mod)) + return -1; + + params->handler = rmodule_entry(&smm_mod); + params->handler_arg = rmodule_parameters(&smm_mod); + + printk(BIOS_DEBUG, "%s : smram_start: 0x%x\n", + __func__, (int)smram); + printk(BIOS_DEBUG, "%s : smram_end: 0x%x\n", + __func__, (int)smram + (int)size); + printk(BIOS_DEBUG, "%s : stack_top: 0x%x\n", + __func__, (int)params->stack_top); + printk(BIOS_DEBUG, "%s : handler start 0x%x\n", + __func__, (int)params->handler); + printk(BIOS_DEBUG, "%s : handler_size 0x%x\n", + __func__, (int)handler_size); + printk(BIOS_DEBUG, "%s : handler_arg 0x%x\n", + __func__, (int)params->handler_arg); + printk(BIOS_DEBUG, "%s : fxsave_area 0x%x\n", + __func__, (int)fxsave_area); + printk(BIOS_DEBUG, "%s : fxsave_size 0x%x\n", + __func__, (int)fxsave_size); + printk(BIOS_DEBUG, "%s : CONFIG_MSEG_SIZE 0x%x\n", + __func__, (int)CONFIG_MSEG_SIZE); + printk(BIOS_DEBUG, "%s : CONFIG_BIOS_RESOURCE_LIST_SIZE 0x%x\n", + __func__, (int)CONFIG_BIOS_RESOURCE_LIST_SIZE); + + /* CPU 0 smbase goes first, all other CPUs + * will be staggered below + */ + base -= SMM_CODE_SEGMENT_SIZE; + printk(BIOS_DEBUG, "%s : cpu0 entry: 0x%x\n", + __func__, (int)base); + params->smm_entry = (uintptr_t)base + params->smm_main_entry_offset; + return smm_module_setup_stub(base, size, params, fxsave_area); +} diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index a3101e5..7838223 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -128,6 +128,12 @@ * into this field so the code doing the loading can manipulate the * runtime's assumptions. e.g. updating the APIC id to CPU map to * handle sparse APIC id space. + * The following parameters are only used when X86_SMM_LOADER_VERSION2 is enabled. + * - smm_entry - entry address of first CPU thread, all others will be tiled + * below this address. + * - smm_main_entry_offset - default entry offset (e.g 0x8000) + * - smram_start - smaram starting address + * - smram_end - smram ending address */ struct smm_loader_params { void *stack_top; @@ -141,12 +147,24 @@ void *handler_arg; struct smm_runtime *runtime; + + /* The following are only used by X86_SMM_LOADER_VERSION2 */ + #if CONFIG(X86_SMM_LOADER_VERSION2) + unsigned int smm_entry; + unsigned int smm_main_entry_offset; + unsigned int smram_start; + unsigned int smram_end; + #endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); +#if CONFIG(X86_SMM_LOADER_VERSION2) +int smm_get_cpu_smbase(unsigned int cpu_num); +#endif + /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); void restore_default_smm_area(void *smm_save_area); -- To view, visit https://review.coreboot.org/c/coreboot/+/43684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00a23a5f2a46110536c344254868390dbb71854c Gerrit-Change-Number: 43684 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Phagura Gerrit-MessageType: newchange

8 50

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020