junaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30798
Change subject: for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
......................................................................
for review d945gclf/Kconig and devicetree.cb . these files are modified according to the superIO chip Winbond w83627DHG
Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5
Signed-off-by: junaid <junaidimpex(a)gmail.com>
---
M src/mainboard/intel/d945gclf/Kconfig
M src/mainboard/intel/d945gclf/devicetree.cb
2 files changed, 37 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/30798/1
diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
index 70fa848..906dd01 100644
--- a/src/mainboard/intel/d945gclf/Kconfig
+++ b/src/mainboard/intel/d945gclf/Kconfig
@@ -20,7 +20,8 @@
select NORTHBRIDGE_INTEL_I945
select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
select SOUTHBRIDGE_INTEL_I82801GX
- select SUPERIO_SMSC_LPC47M15X
+## changed as per Advantech SOM 4461
+ select SUPERIO_WINBOND_W83627DHG
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 90c517f..864775a 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -65,44 +65,42 @@
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 off end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
- device pci 1e.2 off end # AC'97 Audio
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
+ device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47m15x
- device pnp 2e.0 off # Floppy
- end
- device pnp 2e.3 off # Parport
- end
- device pnp 2e.4 on
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 on
- io 0x60 = 0x2f8
- irq 0x70 = 3
- irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
- end
- device pnp 2e.7 on # Keyboard+Mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- irq 0xf0 = 0x82 # HW accel A20.
- end
- device pnp 2e.8 on # GAME
- # all default
- end
- device pnp 2e.a on # PME
- end
- device pnp 2e.b on # MPU
- end
- end
- end
+ chip superio/winbond/w83627dhg
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 off end # Parallel Port
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard,Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ #device pnp 2e.6 off end # SPI
+ device pnp 2e.307 off end # GPIO6
+ device pnp 2e.8 off end # WDTO, PLED
+ device pnp 2e.009 off end # GPIO2
+ device pnp 2e.109 off end # GPIO3
+ device pnp 2e.209 off end # GPIO4
+ device pnp 2e.309 off end # GPIO5
+ device pnp 2e.A off end # ACPI
+ device pnp 2e.B off end # HW Monitor
+ end # w83627dhg
+ end
device pci 1f.1 off end # IDE
- device pci 1f.2 on end # SATA
- device pci 1f.3 on end # SMBus
- end
- end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ end
+ end
end
--
To view, visit https://review.coreboot.org/c/coreboot/+/30798
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1449d9351bd1b76ecad16e6d81c501c1d4dd80f5
Gerrit-Change-Number: 30798
Gerrit-PatchSet: 1
Gerrit-Owner: junaid <junaidimpex(a)gmail.com>
Gerrit-MessageType: newchange
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40962 )
Change subject: superio/*: Standardise config state entry/exit prototype in pnp_ops.h
......................................................................
superio/*: Standardise config state entry/exit prototype in pnp_ops.h
pnp_{entry,exit}_conf_state() is declared and implemented under each
super I/O with not that much variation. Place them to a central
location along with other pre-RAM pnp functions.
This provides a standard pre-RAM PNP API, with the eventual goal of
consolidating all implementations, with only one implementation
per actual known config state entry/exit sequence.
Remove the prototype from winbond/common. All code that use pre-RAM
pnp include pnp_ops.h and all basic functions will be brought in. The
correct implementation is selected at compile time via Makefile.inc.
Change-Id: If4e742edb17ca73c01ff7b552e00e18acc6779dd
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/include/device/pnp_ops.h
M src/superio/fintek/common/fintek.h
M src/superio/winbond/common/winbond.h
3 files changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/40962/1
diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h
index 93a5dc8..f43cb33 100644
--- a/src/include/device/pnp_ops.h
+++ b/src/include/device/pnp_ops.h
@@ -10,6 +10,9 @@
#if ENV_PNP_SIMPLE_DEVICE
+void pnp_enter_conf_state(pnp_devfn_t dev);
+void pnp_exit_conf_state(pnp_devfn_t dev);
+
static __always_inline void pnp_write_config(
pnp_devfn_t dev, uint8_t reg, uint8_t value)
{
diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h
index 81e8e67..915c148 100644
--- a/src/superio/fintek/common/fintek.h
+++ b/src/superio/fintek/common/fintek.h
@@ -9,7 +9,4 @@
void fintek_enable_serial(pnp_devfn_t dev, u16 iobase);
-void pnp_enter_conf_state(pnp_devfn_t dev);
-void pnp_exit_conf_state(pnp_devfn_t dev);
-
#endif /* SUPERIO_FINTEK_COMMON_PRE_RAM_H */
diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h
index 58297e5..9816db0 100644
--- a/src/superio/winbond/common/winbond.h
+++ b/src/superio/winbond/common/winbond.h
@@ -11,7 +11,4 @@
void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state);
void winbond_set_clksel_48(pnp_devfn_t dev);
-void pnp_enter_conf_state(pnp_devfn_t dev);
-void pnp_exit_conf_state(pnp_devfn_t dev);
-
#endif /* SUPERIO_WINBOND_COMMON_PRE_RAM_H */
--
To view, visit https://review.coreboot.org/c/coreboot/+/40962
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If4e742edb17ca73c01ff7b552e00e18acc6779dd
Gerrit-Change-Number: 40962
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43395 )
Change subject: cpu/x86/16bit/entry16.inc: Stop PBET timer on Boot Guard platforms
......................................................................
cpu/x86/16bit/entry16.inc: Stop PBET timer on Boot Guard platforms
PBET timer has to be stopped before APs are launched and initialized.
Otherwise the platform will reset. The PBET expiration time may be very
low so stop timer as quickly as possible. The expiration time is defined
in Boot Guard manifests.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I545a36d60597fe37a30b8207336ae7fa7831674d
---
M src/cpu/x86/16bit/entry16.inc
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/43395/1
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index babed02..c555c5c 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,6 +29,7 @@
#include <cpu/x86/post_code.h>
#define BOOTGUARD_SACM_INFO 0x13a
+#define BOOTGUARD_PBEC 0x139
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
@@ -118,6 +119,14 @@
andl $0x7FFAFFD1, %ebx /* PG,AM,WP,NE,TS,EM,MP = 0 */
orl $0x60000001, %ebx /* CD, NW, PE = 1 */
#if CONFIG(INTEL_BOOTGUARD)
+ /*
+ * Stop PBET timer. It is recommended to stop the PBET timer
+ * regardless of Boot Guard status.
+ */
+ movl $BOOTGUARD_PBEC, %ecx
+ movl $0, %edx
+ movl $1, %eax
+ wrmsr
/* DO NOT disable cache if Intel BootGuard is supported */
movl $BOOTGUARD_SACM_INFO, %ecx
--
To view, visit https://review.coreboot.org/c/coreboot/+/43395
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I545a36d60597fe37a30b8207336ae7fa7831674d
Gerrit-Change-Number: 43395
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43401 )
Change subject: program layout: align to 64 bytes when Boot Guard is enabled
......................................................................
program layout: align to 64 bytes when Boot Guard is enabled
FIT entries for IBB segmnets have 64 byte granularity. Enforce the
64 bytes alignment on all programs and FIT table to ensure the
entires for IBB will be added correctly.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I3ce09e24d716fe9845104205bc934bd2a0efc9cb
---
M src/arch/x86/memlayout.ld
M src/cpu/intel/fit/fit.S
M src/lib/program.ld
3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/43401/1
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 3659cc9..605ed24 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -47,3 +47,8 @@
#include <cpu/intel/fit/fit.ld>
#endif
#endif /* ENV_BOOTBLOCK */
+
+/* Each program stage needs to be 64 bytes aligned to be added as FIT entry */
+#if CONFIG_INTEL_BOOTGUARD
+. = ALIGN(64);
+#endif
diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S
index 3b7396c..037918a 100644
--- a/src/cpu/intel/fit/fit.S
+++ b/src/cpu/intel/fit/fit.S
@@ -9,7 +9,15 @@
.previous
.section .text
+#if CONFIG(INTEL_BOOTGUARD)
+/*
+ * FIT must be excluded from IBB with BootGuard. As the IBB segments have 64
+ * byte granularity, align the FIT to 64 bytes.
+ */
+.align 64
+#else
.align 16
+#endif
.global fit_table
.global fit_table_end
fit_table:
@@ -28,5 +36,12 @@
/* Checksum byte - must add to zero. */
.byte 0x7d
.fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16
+#if CONFIG(INTEL_BOOTGUARD)
+/*
+ * Just in case the FIT does not end on 64 byte aligned address, maintain the
+ * 64 byte boundaries of IBB segments.
+ */
+.align 64
+#endif
fit_table_end:
.previous
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 88a3126..ee105e3 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -48,6 +48,10 @@
*(.rodata);
*(.rodata.*);
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+#if CONFIG_INTEL_BOOTGUARD
+/* Each program stage needs to be 64 bytes aligned to be added as FIT entry */
+ . = ALIGN(64);
+#endif
_etext = .;
} : to_load
--
To view, visit https://review.coreboot.org/c/coreboot/+/43401
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3ce09e24d716fe9845104205bc934bd2a0efc9cb
Gerrit-Change-Number: 43401
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44262 )
Change subject: soc/intel/tigerlake: move mainboard_silicon_init_params
......................................................................
soc/intel/tigerlake: move mainboard_silicon_init_params
This patch arranges mainboard_silicon_init_params before fetching
any config variables from devicetree. This would allow the variant
specific devicetree overrides to get consumed so that FSP UPD
parameters are initialized properly before SiliconInit.
BUG=b:158573805
TEST=Test that UPD values are set properly with variant specific
overrides of config's .
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Change-Id: Idfce528efa7806e292071e092fb129b53a94a145
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44262/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index a61a025..5178d91 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -107,6 +107,8 @@
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ mainboard_silicon_init_params(params);
+
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable;
cpu_id = cpu_get_cpuid();
@@ -311,7 +313,6 @@
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
params->EnableMultiPhaseSiliconInit = 1;
- mainboard_silicon_init_params(params);
}
/*
--
To view, visit https://review.coreboot.org/c/coreboot/+/44262
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idfce528efa7806e292071e092fb129b53a94a145
Gerrit-Change-Number: 44262
Gerrit-PatchSet: 1
Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-MessageType: newchange