Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39761 )
Change subject: Doc/mb/lenovo/montevina_series: Describe GbE generating
......................................................................
Doc/mb/lenovo/montevina_series: Describe GbE generating
Instead of using the gbe region extracted from stock dump, one may want
to generate the new one. util/bincfg can do that, but it's not
documented anywhere yet.
This patch describes how to do that along with changing the MAC
address.
Change-Id: I9318514b125b53f8ad76ad99755690ec6f681441
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M Documentation/mainboard/lenovo/montevina_series.md
1 file changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39761/1
diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md
index 62e8796..39dee2f 100644
--- a/Documentation/mainboard/lenovo/montevina_series.md
+++ b/Documentation/mainboard/lenovo/montevina_series.md
@@ -33,6 +33,9 @@
$ ifdtool -x backup.rom
```
+Note that you can also [generate new GbE region](#generating-gbe-region) and use
+it instead.
+
Now you need to patch the flash descriptor. You can either [modify the one from
your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
[generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg).
@@ -122,6 +125,7 @@
(/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file
[*] Add gigabit ethernet configuration
+ # Note: if you used bincfg, specify path to generated util/bincfg/flashregion_3_gbe.bin
(/path/to/flashregion_3_gbe.bin) Path to gigabit ethernet configuration
```
@@ -136,6 +140,32 @@
# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
```
+## Generating GbE region
+
+GbE region contains configuration data for Intel integrated Gigabit Ethernet.
+You can generate new GbE Region by using **bincfg**. To do that, go to
+`util/bincfg`.
+
+It's good idea to set MAC address first, so open then `gbe-ich9m.set` file and
+change values of `macaddress0` .. `macaddress5` fields. For example, if you want
+to set MAC address to `00:01:02:03:04:05`:
+
+```
+ "macaddress0" = 0x0,
+ "macaddress1" = 0x1,
+ "macaddress2" = 0x2,
+ "macaddress3" = 0x3,
+ "macaddress4" = 0x4,
+ "macaddress5" = 0x5
+```
+
+Then run:
+```console
+$ make gen-gbe-ich9m
+```
+
+The new GbE region will be saved to `flashregion_3_gbe.bin`.
+
## Flash layout
The flash layouts of the OEM firmware are as follows:
--
To view, visit https://review.coreboot.org/c/coreboot/+/39761
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9318514b125b53f8ad76ad99755690ec6f681441
Gerrit-Change-Number: 39761
Gerrit-PatchSet: 1
Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io>
Gerrit-MessageType: newchange
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41877 )
Change subject: Add Kconfig option for ACPI S3 support
......................................................................
Add Kconfig option for ACPI S3 support
Being able to disable ACPI S3 saves 150 ms on the ASRock E350M1.
Change-Id: Ie25c6ab5cd927287f0e2ff00cce042a95f7d377c
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/Kconfig
M src/lib/hardwaremain.c
2 files changed, 20 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41877/1
diff --git a/src/Kconfig b/src/Kconfig
index 2a2a144..0e89eb6 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -135,6 +135,22 @@
every boot. Use this if you want the NVRAM configuration to
never be modified from its default values.
+config DO_ACPI_RESUME
+ bool "Enable ACPI S3 resume"
+ default y
+ depends on HAVE_ACPI_RESUME
+ help
+ Adds S3 to the available sleepstates
+
+ Enabling ACPI S3 resume support delays the boot-up on certain boards.
+ For example, the delay it 200 ms on the AMD AGESA board ASRock E350M1.
+
+ If you do not need ACPI S3 resume support, select this option.
+
+ (And why should you, with coreboot, an SSD and an optimized OS, you
+ boot as fast as with resuming from ACPI S3, and have less code paths
+ to maintain and test.)
+
config COMPRESS_RAMSTAGE
bool "Compress ramstage with LZMA"
depends on HAVE_RAMSTAGE
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 935393e..20b7c25 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -19,7 +19,7 @@
#include <stdlib.h>
#include <boot/tables.h>
#include <program_loading.h>
-#if CONFIG(HAVE_ACPI_RESUME)
+#if CONFIG(DO_ACPI_RESUME)
#include <acpi/acpi.h>
#endif
#include <timer.h>
@@ -151,7 +151,7 @@
static boot_state_t bs_os_resume_check(void *arg)
{
-#if CONFIG(HAVE_ACPI_RESUME)
+#if CONFIG(DO_ACPI_RESUME)
void *wake_vector;
wake_vector = acpi_find_wakeup_vector();
@@ -168,7 +168,7 @@
static boot_state_t bs_os_resume(void *wake_vector)
{
-#if CONFIG(HAVE_ACPI_RESUME)
+#if CONFIG(DO_ACPI_RESUME)
arch_bootstate_coreboot_exit();
acpi_resume(wake_vector);
#endif
@@ -445,7 +445,7 @@
post_code(POST_ENTRY_RAMSTAGE);
/* Handoff sleep type from romstage. */
-#if CONFIG(HAVE_ACPI_RESUME)
+#if CONFIG(DO_ACPI_RESUME)
acpi_is_wakeup();
#endif
threads_initialize();
--
To view, visit https://review.coreboot.org/c/coreboot/+/41877
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie25c6ab5cd927287f0e2ff00cce042a95f7d377c
Gerrit-Change-Number: 41877
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
Łukasz Siudut has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32905
Change subject: RFC: smbios: allow setting BIOS-version string from VPD variable
......................................................................
RFC: smbios: allow setting BIOS-version string from VPD variable
As in the title. Such approach allows for convenient setting of the
firmware version and keep it in partition that is easily readable
from both - coreboot binary and already running operating system.
vpd_find is used directly as it returns pointer to vpd value which,
by spec, is terminated by 0x00 (VPD_TYPE_TERMINATOR) anyway. This
way we avoid copying string around and coming up with temporary
buffer.
Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458
Signed-off-by: Lukasz Siudut <lsiudut(a)gmail.com>
---
M src/arch/x86/smbios.c
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32905/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 589f4f0..2ffd2dd 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -30,6 +30,9 @@
#include <memory_info.h>
#include <spd.h>
#include <cbmem.h>
+#if CONFIG(VPD)
+#include <drivers/vpd/vpd.h>
+#endif
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -347,6 +350,15 @@
const char *__weak smbios_mainboard_bios_version(void)
{
+#if CONFIG(VPD)
+ /* size is unused for now */
+ int size;
+ const char *coreboot_vpd_version = vpd_find("version", &size, VPD_RO);
+
+ /* if found, vpd value will be terminated by 0x00 (VPD_TYPE_TERMINATOR) */
+ if(coreboot_vpd_version)
+ return coreboot_vpd_version;
+#endif
if (strlen(CONFIG_LOCALVERSION))
return CONFIG_LOCALVERSION;
else
--
To view, visit https://review.coreboot.org/c/coreboot/+/32905
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If0e9d90ed0941c4e76e3e48cdcccf830ef789458
Gerrit-Change-Number: 32905
Gerrit-PatchSet: 1
Gerrit-Owner: Łukasz Siudut
Gerrit-MessageType: newchange
Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42241 )
Change subject: mb/google/hatch: Consolidate mainboard.c for Puff
......................................................................
mb/google/hatch: Consolidate mainboard.c for Puff
Puff and it's variants share a rather common mainboard.c
implementation. Avoid further divergence by sharing a
common implementation when the Puff baseboard is selected
by the variants.
BUG=b:154071868
BRANCH=none
TEST=equiv images.
Change-Id: I9cb11cf0e3ef13a1517a91f93a4b4c53a3e01a44
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M src/mainboard/google/hatch/Makefile.inc
R src/mainboard/google/hatch/mainboard.c
M src/mainboard/google/hatch/variants/duffy/Makefile.inc
D src/mainboard/google/hatch/variants/duffy/mainboard.c
M src/mainboard/google/hatch/variants/kaisa/Makefile.inc
D src/mainboard/google/hatch/variants/kaisa/mainboard.c
M src/mainboard/google/hatch/variants/noibat/Makefile.inc
D src/mainboard/google/hatch/variants/noibat/mainboard.c
M src/mainboard/google/hatch/variants/puff/Makefile.inc
9 files changed, 2 insertions(+), 433 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42241/1
diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc
index f82325f..ca7f318 100644
--- a/src/mainboard/google/hatch/Makefile.inc
+++ b/src/mainboard/google/hatch/Makefile.inc
@@ -7,6 +7,8 @@
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c
+
romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/mainboard.c
similarity index 100%
rename from src/mainboard/google/hatch/variants/puff/mainboard.c
rename to src/mainboard/google/hatch/mainboard.c
diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/hatch/variants/duffy/Makefile.inc
index 2afd494..3b5b7d0 100644
--- a/src/mainboard/google/hatch/variants/duffy/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/duffy/Makefile.inc
@@ -1,5 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
ramstage-y += gpio.c
-ramstage-y += mainboard.c
bootblock-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c
deleted file mode 100644
index ecc0937..0000000
--- a/src/mainboard/google/hatch/variants/duffy/mainboard.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/variants.h>
-#include <chip.h>
-#include <delay.h>
-#include <device/device.h>
-#include <ec/google/chromeec/ec.h>
-#include <gpio.h>
-#include <intelblocks/power_limit.h>
-#include <timer.h>
-
-#define GPIO_HDMI_HPD GPP_E13
-#define GPIO_DP_HPD GPP_E14
-
-/* TODO: This can be moved to common directory */
-static void wait_for_hpd(gpio_t gpio, long timeout)
-{
- struct stopwatch sw;
-
- printk(BIOS_INFO, "Waiting for HPD\n");
- stopwatch_init_msecs_expire(&sw, timeout);
- while (!gpio_get(gpio)) {
- if (stopwatch_expired(&sw)) {
- printk(BIOS_WARNING,
- "HPD not ready after %ldms. Abort.\n", timeout);
- return;
- }
- mdelay(200);
- }
- printk(BIOS_INFO, "HPD ready after %lu ms\n",
- stopwatch_duration_msecs(&sw));
-}
-
-/*
- * For type-C chargers, set PL2 to 90% of max power to account for
- * cable loss and FET Rdson loss in the path from the source.
- */
-#define SET_PSYSPL2(w) (9 * (w) / 10)
-
-#define PUFF_PL2 (35)
-
-#define PUFF_PSYSPL2 (58)
-
-#define PUFF_MAX_TIME_WINDOW 6
-#define PUFF_MIN_DUTYCYCLE 4
-
-/*
- * mainboard_set_power_limits
- *
- * Set Pl2 and SysPl2 values based on detected charger.
- * Values are defined below but we use U22 value for all SKUs for now.
- * definitions:
- * x = no value entered. Use default value in parenthesis.
- * will set 0 to anything that shouldn't be set.
- * n = max value of power adapter.
- * +-------------+-----+---------+-----------+-------+
- * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
- * +-------------+-----+---------+-----------+-------+
- * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
- * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
- * +-------------+-----+---------+-----------+-------+
- * For USB C charger:
- * +-------------+-----+---------+---------+-------+
- * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
- * +-------------+-----+---------+---------+-------+
- * | 60 (U42) | 44 | 54 | 54 | 54 |
- * | 60 (U22) | 29 | 54 | 54 | x(43) |
- * | n (U42) | 44 | .9n | .9n | .9n |
- * | n (U22) | 29 | .9n | .9n | x(43) |
- * +-------------+-----+---------+---------+-------+
- */
-
-/*
- * Psys_pmax considerations
- *
- * Given the hardware design in puff, the serial shunt resistor is 0.01ohm.
- * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A
- * instead of real system power. The equation is shown below:
- * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k)
- * Hence, Iinput (Amps) = 9.6A
- * Since there is no voltage information from PSYS, different voltage input
- * would map to different Psys_pmax settings:
- * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W
- * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W
- * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W
- */
-#define PSYS_IMAX 9600
-#define BJ_VOLTS_MV 19000
-
-static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
-{
- enum usb_chg_type type;
- u32 watts;
- u16 volts_mv, current_ma;
- u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
- int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
-
- /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
- conf->tdp_psyspl3 = 0;
- conf->tdp_pl4 = 0;
-
- if (rv == 0 && type == USB_CHG_TYPE_PD) {
- /* Detected USB-PD. Base on max value of adapter */
- watts = ((u32)current_ma * volts_mv) / 1000000;
- psyspl2 = watts;
- conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
- /* set max possible time window */
- conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
- /* set minimum duty cycle */
- conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
- conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
- } else {
- /* Input type is barrel jack */
- volts_mv = BJ_VOLTS_MV;
- }
- /* voltage unit is milliVolts and current is in milliAmps */
- conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
-
- conf->tdp_pl2_override = PUFF_PL2;
- /* set psyspl2 to 90% of max adapter power */
- conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
-}
-
-void variant_ramstage_init(void)
-{
- static const long display_timeout_ms = 3000;
- struct soc_power_limits_config *soc_config;
- config_t *confg = config_of_soc();
-
- /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
- gpio_input(GPIO_HDMI_HPD);
- gpio_input(GPIO_DP_HPD);
- if (display_init_required()
- && !gpio_get(GPIO_HDMI_HPD)
- && !gpio_get(GPIO_DP_HPD)) {
- /* This has to be done before FSP-S runs. */
- if (google_chromeec_wait_for_displayport(display_timeout_ms))
- wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
- }
- /* Psys_pmax needs to be setup before FSP-S */
- soc_config = &confg->power_limits_config;
- mainboard_set_power_limits(soc_config);
-}
diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc
index 2afd494..3b5b7d0 100644
--- a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/kaisa/Makefile.inc
@@ -1,5 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
ramstage-y += gpio.c
-ramstage-y += mainboard.c
bootblock-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c
deleted file mode 100644
index ecc0937..0000000
--- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/variants.h>
-#include <chip.h>
-#include <delay.h>
-#include <device/device.h>
-#include <ec/google/chromeec/ec.h>
-#include <gpio.h>
-#include <intelblocks/power_limit.h>
-#include <timer.h>
-
-#define GPIO_HDMI_HPD GPP_E13
-#define GPIO_DP_HPD GPP_E14
-
-/* TODO: This can be moved to common directory */
-static void wait_for_hpd(gpio_t gpio, long timeout)
-{
- struct stopwatch sw;
-
- printk(BIOS_INFO, "Waiting for HPD\n");
- stopwatch_init_msecs_expire(&sw, timeout);
- while (!gpio_get(gpio)) {
- if (stopwatch_expired(&sw)) {
- printk(BIOS_WARNING,
- "HPD not ready after %ldms. Abort.\n", timeout);
- return;
- }
- mdelay(200);
- }
- printk(BIOS_INFO, "HPD ready after %lu ms\n",
- stopwatch_duration_msecs(&sw));
-}
-
-/*
- * For type-C chargers, set PL2 to 90% of max power to account for
- * cable loss and FET Rdson loss in the path from the source.
- */
-#define SET_PSYSPL2(w) (9 * (w) / 10)
-
-#define PUFF_PL2 (35)
-
-#define PUFF_PSYSPL2 (58)
-
-#define PUFF_MAX_TIME_WINDOW 6
-#define PUFF_MIN_DUTYCYCLE 4
-
-/*
- * mainboard_set_power_limits
- *
- * Set Pl2 and SysPl2 values based on detected charger.
- * Values are defined below but we use U22 value for all SKUs for now.
- * definitions:
- * x = no value entered. Use default value in parenthesis.
- * will set 0 to anything that shouldn't be set.
- * n = max value of power adapter.
- * +-------------+-----+---------+-----------+-------+
- * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
- * +-------------+-----+---------+-----------+-------+
- * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
- * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
- * +-------------+-----+---------+-----------+-------+
- * For USB C charger:
- * +-------------+-----+---------+---------+-------+
- * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
- * +-------------+-----+---------+---------+-------+
- * | 60 (U42) | 44 | 54 | 54 | 54 |
- * | 60 (U22) | 29 | 54 | 54 | x(43) |
- * | n (U42) | 44 | .9n | .9n | .9n |
- * | n (U22) | 29 | .9n | .9n | x(43) |
- * +-------------+-----+---------+---------+-------+
- */
-
-/*
- * Psys_pmax considerations
- *
- * Given the hardware design in puff, the serial shunt resistor is 0.01ohm.
- * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A
- * instead of real system power. The equation is shown below:
- * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k)
- * Hence, Iinput (Amps) = 9.6A
- * Since there is no voltage information from PSYS, different voltage input
- * would map to different Psys_pmax settings:
- * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W
- * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W
- * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W
- */
-#define PSYS_IMAX 9600
-#define BJ_VOLTS_MV 19000
-
-static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
-{
- enum usb_chg_type type;
- u32 watts;
- u16 volts_mv, current_ma;
- u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
- int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
-
- /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
- conf->tdp_psyspl3 = 0;
- conf->tdp_pl4 = 0;
-
- if (rv == 0 && type == USB_CHG_TYPE_PD) {
- /* Detected USB-PD. Base on max value of adapter */
- watts = ((u32)current_ma * volts_mv) / 1000000;
- psyspl2 = watts;
- conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
- /* set max possible time window */
- conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
- /* set minimum duty cycle */
- conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
- conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
- } else {
- /* Input type is barrel jack */
- volts_mv = BJ_VOLTS_MV;
- }
- /* voltage unit is milliVolts and current is in milliAmps */
- conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
-
- conf->tdp_pl2_override = PUFF_PL2;
- /* set psyspl2 to 90% of max adapter power */
- conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
-}
-
-void variant_ramstage_init(void)
-{
- static const long display_timeout_ms = 3000;
- struct soc_power_limits_config *soc_config;
- config_t *confg = config_of_soc();
-
- /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
- gpio_input(GPIO_HDMI_HPD);
- gpio_input(GPIO_DP_HPD);
- if (display_init_required()
- && !gpio_get(GPIO_HDMI_HPD)
- && !gpio_get(GPIO_DP_HPD)) {
- /* This has to be done before FSP-S runs. */
- if (google_chromeec_wait_for_displayport(display_timeout_ms))
- wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
- }
- /* Psys_pmax needs to be setup before FSP-S */
- soc_config = &confg->power_limits_config;
- mainboard_set_power_limits(soc_config);
-}
diff --git a/src/mainboard/google/hatch/variants/noibat/Makefile.inc b/src/mainboard/google/hatch/variants/noibat/Makefile.inc
index 2afd494..3b5b7d0 100644
--- a/src/mainboard/google/hatch/variants/noibat/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/noibat/Makefile.inc
@@ -1,5 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
ramstage-y += gpio.c
-ramstage-y += mainboard.c
bootblock-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/noibat/mainboard.c b/src/mainboard/google/hatch/variants/noibat/mainboard.c
deleted file mode 100644
index b5bc699..0000000
--- a/src/mainboard/google/hatch/variants/noibat/mainboard.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/variants.h>
-#include <chip.h>
-#include <delay.h>
-#include <device/device.h>
-#include <ec/google/chromeec/ec.h>
-#include <gpio.h>
-#include <intelblocks/power_limit.h>
-#include <timer.h>
-
-#define GPIO_HDMI_HPD GPP_E13
-#define GPIO_DP_HPD GPP_E14
-
-/* TODO: This can be moved to common directory */
-static void wait_for_hpd(gpio_t gpio, long timeout)
-{
- struct stopwatch sw;
-
- printk(BIOS_INFO, "Waiting for HPD\n");
- stopwatch_init_msecs_expire(&sw, timeout);
- while (!gpio_get(gpio)) {
- if (stopwatch_expired(&sw)) {
- printk(BIOS_WARNING,
- "HPD not ready after %ldms. Abort.\n", timeout);
- return;
- }
- mdelay(200);
- }
- printk(BIOS_INFO, "HPD ready after %lu ms\n",
- stopwatch_duration_msecs(&sw));
-}
-
-/*
- * For type-C chargers, set PL2 to 90% of max power to account for
- * cable loss and FET Rdson loss in the path from the source.
- */
-#define SET_PSYSPL2(w) (9 * (w) / 10)
-
-#define PUFF_PL2 (35)
-
-#define PUFF_PSYSPL2 (58)
-
-#define PUFF_MAX_TIME_WINDOW 6
-#define PUFF_MIN_DUTYCYCLE 4
-
-/*
- * mainboard_set_power_limits
- *
- * Set Pl2 and SysPl2 values based on detected charger.
- * Values are defined below but we use U22 value for all SKUs for now.
- * definitions:
- * x = no value entered. Use default value in parenthesis.
- * will set 0 to anything that shouldn't be set.
- * n = max value of power adapter.
- * +-------------+-----+---------+-----------+-------+
- * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
- * +-------------+-----+---------+-----------+-------+
- * | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
- * | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
- * +-------------+-----+---------+-----------+-------+
- * For USB C charger:
- * +-------------+-----+---------+---------+-------+
- * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
- * +-------------+-----+---------+---------+-------+
- * | 60 (U42) | 44 | 54 | 54 | 54 |
- * | 60 (U22) | 29 | 54 | 54 | x(43) |
- * | n (U42) | 44 | .9n | .9n | .9n |
- * | n (U22) | 29 | .9n | .9n | x(43) |
- * +-------------+-----+---------+---------+-------+
- */
-
-/*
- * Psys_pmax considerations
- *
- * Given the hardware design in puff, the serial shunt resistor is 0.01ohm.
- * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A
- * instead of real system power. The equation is shown below:
- * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k)
- * Hence, Iinput (Amps) = 9.6A
- * Since there is no voltage information from PSYS, different voltage input
- * would map to different Psys_pmax settings:
- * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W
- * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W
- * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W
- */
-#define PSYS_IMAX 9600
-#define BJ_VOLTS_MV 19000
-
-static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
-{
- enum usb_chg_type type;
- u32 watts;
- u16 volts_mv, current_ma;
- u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
- int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
-
- /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
- conf->tdp_psyspl3 = 0;
- conf->tdp_pl4 = 0;
-
- if (rv == 0 && type == USB_CHG_TYPE_PD) {
- /* Detected USB-PD. Base on max value of adapter */
- watts = ((u32)current_ma * volts_mv) / 1000000;
- psyspl2 = watts;
- conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
- /* set max possible time window */
- conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
- /* set minimum duty cycle */
- conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
- conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
- } else {
- /* Input type is barrel jack */
- volts_mv = BJ_VOLTS_MV;
- }
- /* voltage unit is milliVolts and current is in milliAmps */
- conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
-
- conf->tdp_pl2_override = PUFF_PL2;
- /* set psyspl2 to 90% of max adapter power */
- conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
-}
-
-void variant_ramstage_init(void)
-{
- static const long display_timeout_ms = 3000;
- struct soc_power_limits_config *soc_config;
- config_t *conf = config_of_soc();
-
- /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
- gpio_input(GPIO_HDMI_HPD);
- gpio_input(GPIO_DP_HPD);
- if (display_init_required()
- && !gpio_get(GPIO_HDMI_HPD)
- && !gpio_get(GPIO_DP_HPD)) {
- /* This has to be done before FSP-S runs. */
- if (google_chromeec_wait_for_displayport(display_timeout_ms))
- wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
- }
- /* Psys_pmax needs to be setup before FSP-S */
- soc_config = &conf->power_limits_config;
- mainboard_set_power_limits(soc_config);
-}
diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/hatch/variants/puff/Makefile.inc
index 2afd494..3b5b7d0 100644
--- a/src/mainboard/google/hatch/variants/puff/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/puff/Makefile.inc
@@ -1,5 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
ramstage-y += gpio.c
-ramstage-y += mainboard.c
bootblock-y += gpio.c
--
To view, visit https://review.coreboot.org/c/coreboot/+/42241
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9cb11cf0e3ef13a1517a91f93a4b4c53a3e01a44
Gerrit-Change-Number: 42241
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newchange