coreboot-gerrit September 2020

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Change in coreboot[master]: nb/intel/sandybridge/gma.c: Fix lock bits setting
by Evgeny Zinoviev (Code Review) 07 Aug '23

07 Aug '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42447 ) Change subject: nb/intel/sandybridge/gma.c: Fix lock bits setting ...................................................................... nb/intel/sandybridge/gma.c: Fix lock bits setting PM lock bits are set too early at the moment. Set them after enabling PM interrupts. Change-Id: I3a16e1ce1236597faad42f3812b2b8d2b5417efd Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/northbridge/intel/sandybridge/gma.c 1 file changed, 23 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42447/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index fee7513..8fe2de8 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -42,7 +42,7 @@ { 0xa23c, 0x0817fe19 }, { 0xa240, 0x00000000 }, { 0xa244, 0x00000000 }, - { 0xa248, 0x8000421e }, + { 0xa248, 0x0000421e }, { 0 }, }; @@ -65,7 +65,7 @@ { 0xa23c, 0x002a002b }, { 0xa240, 0x00000000 }, { 0xa244, 0x00000000 }, - { 0xa248, 0x8000421e }, + { 0xa248, 0x0000421e }, { 0 }, }; @@ -373,23 +373,20 @@ } /* 3: Gear ratio map */ - gtt_write(0xa004, 0x00000010); + gtt_write(0xa004, 0x00000000); /* 4: GFXPAUSE */ gtt_write(0xa000, 0x00070020); - /* 5: Dynamic EU trip control */ - gtt_write(0xa080, 0x00000004); - - /* 6: ECO bits */ + /* 5: ECO bits */ reg32 = gtt_read(0xa180); - reg32 |= (1 << 26) | (1 << 31); + reg32 |= (1 << 26); /* (bit 20=1 for SNB step D1+ / IVB A0+) */ if (bridge_silicon_revision() >= SNB_STEP_D1) reg32 |= (1 << 20); gtt_write(0xa180, reg32); - /* 6a: for SnB step D2+ only */ + /* 5a: for SnB step D2+ only */ if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && (bridge_silicon_revision() >= SNB_STEP_D2)) { reg32 = gtt_read(0x9400); @@ -408,14 +405,14 @@ reg32 |= (1 << 16); gtt_write(0x907c, reg32); - /* 6b: Clocking reset controls */ + /* 5b: Clocking reset controls */ gtt_write(0x9424, 0x00000001); } else { - /* 6b: Clocking reset controls */ + /* 5b: Clocking reset controls */ gtt_write(0x9424, 0x00000000); } - /* 7 */ + /* 6 */ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { gtt_write(0x138128, 0x00000029); /* Mailbox Data */ gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ @@ -424,7 +421,7 @@ gtt_poll(0x138124, (1 << 31), (0 << 31)); } - /* 8 */ + /* 7 */ gtt_write(0xa090, 0x00000000); /* RC Control */ gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ @@ -432,19 +429,19 @@ gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ - /* 9 */ + /* 8 */ gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ - /* 10 */ + /* 9 */ gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ - /* 11 */ + /* 10 */ gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ @@ -454,7 +451,7 @@ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ /* - * 11a: Enable Render Standby (RC6) + * 10a: Enable Render Standby (RC6) * * IvyBridge should also support DeepRenderStandby. * @@ -463,7 +460,7 @@ */ gtt_write(0xa090, 0x88040000); /* HW RC Control */ - /* 12: Normal Frequency Request */ + /* 11: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ /* only the lower 7 bits are used and shifted left by 25 */ reg32 = MCHBAR32(0x5998); @@ -472,12 +469,18 @@ reg32 <<= 25; gtt_write(0xa008, reg32); - /* 13: RP Control */ + /* 12: RP Control */ gtt_write(0xa024, 0x00000592); - /* 14: Enable PM Interrupts */ + /* 13: Enable PM Interrupts */ gtt_write(0x4402c, 0x03000076); + /* 14: PM Lock Settings */ + gtt_write(0xa248, gtt_read(0xa248) | (1 << 31)); + gtt_write(0xa004, gtt_read(0xa004) | (1 << 4)); + gtt_write(0xa080, gtt_read(0xa080) | (1 << 2)); + gtt_write(0xa180, gtt_read(0xa180) | (1 << 31)); + /* Clear 0x6c024 [8:6] */ reg32 = gtt_read(0x6c024); reg32 &= ~0x000001c0; -- To view, visit https://review.coreboot.org/c/coreboot/+/42447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a16e1ce1236597faad42f3812b2b8d2b5417efd Gerrit-Change-Number: 42447 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: cpu/x86/lapic_def.h: Drop unused macros
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42454 ) Change subject: cpu/x86/lapic_def.h: Drop unused macros ...................................................................... cpu/x86/lapic_def.h: Drop unused macros These macros are unused and rather confusing to use. Get rid of them. Change-Id: I435411e46361dc62a40965b7fb77421a4212724a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/cpu/x86/lapic_def.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42454/1 diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index 9da89ee..934c86c 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -52,14 +52,11 @@ #define LAPIC_DM_EXTINT 0x00700 #define LAPIC_VECTOR_MASK 0x000FF #define LAPIC_ICR2 0x310 -#define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF) #define SET_LAPIC_DEST_FIELD(x) ((x)<<24) #define LAPIC_LVTT 0x320 #define LAPIC_LVTPC 0x340 #define LAPIC_LVT0 0x350 #define LAPIC_LVT_TIMER_BASE_MASK (0x3<<18) -#define GET_LAPIC_TIMER_BASE(x) (((x)>>18)&0x3) -#define SET_LAPIC_TIMER_BASE(x) (((x)<<18)) #define LAPIC_TIMER_BASE_CLKIN 0x0 #define LAPIC_TIMER_BASE_TMBASE 0x1 #define LAPIC_TIMER_BASE_DIV 0x2 @@ -74,8 +71,6 @@ #define LAPIC_DELIVERY_MODE_FIXED (0<<8) #define LAPIC_DELIVERY_MODE_NMI (4<<8) #define LAPIC_DELIVERY_MODE_EXTINT (7<<8) -#define GET_LAPIC_DELIVERY_MODE(x) (((x)>>8)&0x7) -#define SET_LAPIC_DELIVERY_MODE(x, y) (((x)&~0x700)|((y)<<8)) #define LAPIC_MODE_FIXED 0x0 #define LAPIC_MODE_NMI 0x4 #define LAPIC_MODE_EXINT 0x7 -- To view, visit https://review.coreboot.org/c/coreboot/+/42454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435411e46361dc62a40965b7fb77421a4212724a Gerrit-Change-Number: 42454 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: nb/intel/sandybridge/gma.c: Correct deasserting force wake on IVB
by Evgeny Zinoviev (Code Review) 07 Aug '23

07 Aug '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42455 ) Change subject: nb/intel/sandybridge/gma.c: Correct deasserting force wake on IVB ...................................................................... nb/intel/sandybridge/gma.c: Correct deasserting force wake on IVB Change-Id: I31f8cddb9408d0c23c558b51f5d1f8787f0b700f Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/northbridge/intel/sandybridge/gma.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/42455/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f9f318c..3e8d0de 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -510,7 +510,8 @@ gtt_write(0xa18c, gtt_read(0xa18c) & ~1); gtt_poll(0x130090, (1 << 0), (0 << 0)); } else { - gtt_write(0xa188, 0x1fffe); + gtt_write(0xa188, gtt_read(0xa188) & 0x1ffff); + gtt_write(0xa188, gtt_read(0xa188) & ~1); if (gtt_poll(0x130040, (1 << 0), (0 << 0))) gtt_write(0xa188, gtt_read(0xa188) | 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f8cddb9408d0c23c558b51f5d1f8787f0b700f Gerrit-Change-Number: 42455 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mainboard/volteer: Enable TcssD3Cold for FW CM
by Shreesh Chhabbi (Code Review) 07 Aug '23

07 Aug '23

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42767 ) Change subject: mainboard/volteer: Enable TcssD3Cold for FW CM ...................................................................... mainboard/volteer: Enable TcssD3Cold for FW CM Enable TcssD3Cold for TCSS Firmware Connection Manager build. This is not tp be merged. It is only for cherrypicking. Change-Id: I6be7c286043020df58057343d622525357139a83 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42767/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 705da1d..4d3b68a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -167,7 +167,7 @@ # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "0" + register "TcssD3ColdEnable" = "1" # DP port register "DdiPortAConfig" = "1" # eDP -- To view, visit https://review.coreboot.org/c/coreboot/+/42767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6be7c286043020df58057343d622525357139a83 Gerrit-Change-Number: 42767 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/intel: Fix bad uses of `find_resource`
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42802 ) Change subject: sb/intel: Fix bad uses of `find_resource` ...................................................................... sb/intel: Fix bad uses of `find_resource` The returned value of `find_resource` can never be null, as the function calls `probe_resource` and dies if it returned null. So, if southbridge code checks if the returned value of `find_resource` is null, replace it with `probe_resource` instead. Change-Id: I22e2e2ce046cc7ac6f2f2a814d694ff50a8dc89b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c 20 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42802/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 4f5d8ca..4bb45e5 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -218,7 +218,7 @@ u32 reg32; /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 03b954f..4d62b80 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -556,7 +556,7 @@ struct mei_csr host; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index ff94a88..da2ef6a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -541,7 +541,7 @@ struct mei_csr host; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 63801a2..2b03140 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -40,28 +40,28 @@ if (sata_mode != 2) return; - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { res->base = 0x1f0; res->size = 8; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } - res = find_resource(dev, PCI_BASE_ADDRESS_1); + res = probe_resource(dev, PCI_BASE_ADDRESS_1); if (res) { res->base = 0x3f4; res->size = 4; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } - res = find_resource(dev, PCI_BASE_ADDRESS_2); + res = probe_resource(dev, PCI_BASE_ADDRESS_2); if (res) { res->base = 0x170; res->size = 8; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } - res = find_resource(dev, PCI_BASE_ADDRESS_3); + res = probe_resource(dev, PCI_BASE_ADDRESS_3); if (res) { res->base = 0x374; res->size = 4; @@ -77,7 +77,7 @@ if (sata_mode == 2) { unsigned int i; for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) { - struct resource *const res = find_resource(dev, i); + struct resource *const res = probe_resource(dev, i); if (res) res->flags &= ~IORESOURCE_FIXED; } diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index dcd2724..e5255d3 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -21,7 +21,7 @@ pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); + res = probe_resource(dev, PCI_BASE_ADDRESS_4); if (res) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 8bc45f6..2764861 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -43,7 +43,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ reg32 = read32((void *)(uintptr_t)(res->base + 4)); diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 91f5857..5f8e89c 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -264,7 +264,7 @@ // pm_iowrite(0x59, 0xB); #endif - res = find_resource(dev, 0x10); + res = probe_resource(dev, 0x10); if (!res) return; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 6efdef7..7fb1433 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -132,7 +132,7 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); + struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5); if (ahci_res != NULL) /* write AHCI GHC_PI register */ write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented); diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index c954f9c..3158000 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -228,7 +228,7 @@ /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, 0x10); + res = probe_resource(dev, 0x10); if (!res) return; diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index cac0375..8ac9bee 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -23,7 +23,7 @@ struct resource *res; /* Initialize AHCI memory-mapped space */ - res = find_resource(dev, PCI_BASE_ADDRESS_5); + res = probe_resource(dev, PCI_BASE_ADDRESS_5); if (!res) return; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index ba20a6a..cb54243 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -228,7 +228,7 @@ /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, 0x10); + res = probe_resource(dev, 0x10); if (!res) return; diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 59a384a..6bc9a4f 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -216,7 +216,7 @@ u32 reg32; /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 2c9c87c..7e35d40 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -478,7 +478,7 @@ u16 reg16; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 7e9aa57..e5c43e5 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -20,7 +20,7 @@ pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); + res = probe_resource(dev, PCI_BASE_ADDRESS_4); if (res) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 0b496da..3ff31e1 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -13,7 +13,7 @@ u8 *base; printk(BIOS_DEBUG, "Thermal init start.\n"); - res = find_resource(dev, 0x10); + res = probe_resource(dev, 0x10); if (!res) return; diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 7ad9929..a597a56 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -36,7 +36,7 @@ /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ reg32 = read32((u32 *)(uintptr_t)(res->base + 4)); diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index f415170..cc29efa 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -117,7 +117,7 @@ u32 codec_mask; /* Find base address */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index cdae271..658a4f4 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -727,7 +727,7 @@ struct mei_csr host; /* Find the MMIO base for the ME interface */ - res = find_resource(dev, PCI_BASE_ADDRESS_0); + res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res || res->base == 0 || res->size == 0) { printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 3973a8d..00bc691 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -140,10 +140,10 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ - bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + bar0 = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!bar0) return; - bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); + bar1 = probe_resource(dev, PCI_BASE_ADDRESS_1); if (!bar1) return; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 39003f6..f88bd2b 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -20,7 +20,7 @@ pci_write_config32(dev, 0x80, reg16); /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); + res = probe_resource(dev, PCI_BASE_ADDRESS_4); if (res) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22e2e2ce046cc7ac6f2f2a814d694ff50a8dc89b Gerrit-Change-Number: 42802 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/amd/picasso: Enable paging on S3 resume
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Hello Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42888 to review the following change. Change subject: soc/amd/picasso: Enable paging on S3 resume ...................................................................... soc/amd/picasso: Enable paging on S3 resume This way we can prevent the BSP from accidentally stomping on OS memory. BUG=b:159081993 TEST=S3 suspend and resume to OS. See paging enabled message. Ran suspend_stress_test for 20+ cycles. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Signed-off-by: Raul E Rangel <rrangel(a)google.com> Change-Id: I58fed6f297831b3cdc2758a5e7610388171d84d3 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/page_map_s3.txt 6 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42888/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9860546..f9c653a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -174,6 +174,12 @@ Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. +config PAGE_TABLE_ADDR + hex + default 0x2B0000 + help + Sets the address in DRAM where page tables should be loaded. + config RAMBASE hex default 0x10000000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 39269e9..9d3bbd8 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -445,4 +445,15 @@ cpu_microcode_bins += $(wildcard 3rdparty/amd_blobs/picasso/PSP/UcodePatch_*.bin) +$(obj)/pt_s3.c $(obj)/pdpt_s3.c: src/soc/amd/picasso/page_map_s3.txt $(DOTCONFIG) util/x86/x86_page_tables.go + go run util/x86/x86_page_tables.go --iomap_file=$< --metadata_base_address=$(CONFIG_PAGE_TABLE_ADDR) --pdpt_output_c_file=$(obj)/pdpt_s3.c --pt_output_c_file=$(obj)/pt_s3.c + +cbfs-files-y += pt_s3 +pt_s3-file := $(obj)/pt_s3.c:struct +pt_s3-type := raw + +cbfs-files-y += pdpt_s3 +pdpt_s3-file := $(obj)/pdpt_s3.c:struct +pdpt_s3-type := raw + endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index a3935cc..ec30c19 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -4,6 +4,7 @@ #include <symbols.h> #include <bootblock_common.h> #include <console/console.h> +#include <cpu/x86/pae.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> @@ -104,6 +105,17 @@ wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } +static void enable_paging(void) +{ + paging_set_nxe(1); + paging_set_default_pat(); + if (acpi_is_wakeup_s3()) { + printk(BIOS_DEBUG, "Enabling S3 page tables\n"); + paging_enable_for_car("pdpt_s3", "pt_s3"); + } +} + + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); @@ -123,5 +135,7 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + enable_paging(); + fch_early_init(); } diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 2e5fae5..2abe54e 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootstate.h> #include <console/console.h> +#include <cpu/x86/pae.h> #include <device/device.h> #include <device/pci.h> #include <drivers/i2c/designware/dw_i2c.h> @@ -173,9 +175,30 @@ southbridge_final(chip_info); } +static void picasso_disable_paging(void *unused) +{ + printk(BIOS_INFO, "%s: Disable Paging\n", __func__); + paging_disable_pae(); +} + +static void picasso_os_entry(void *unused) +{ + picasso_disable_paging(NULL); +} + struct chip_operations soc_amd_picasso_ops = { CHIP_NAME("AMD Picasso SOC") .enable_dev = enable_dev, .init = soc_init, .final = soc_final }; + +BOOT_STATE_INIT_ENTRY( + BS_PAYLOAD_BOOT, + BS_ON_ENTRY, + picasso_disable_paging, NULL); + +BOOT_STATE_INIT_ENTRY( + BS_OS_RESUME, + BS_ON_ENTRY, + picasso_os_entry, NULL); diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 6f43ba1..27c72a2 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -89,6 +89,9 @@ VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif + REGION(pagetables, CONFIG_PAGE_TABLE_ADDR, 4096 * 12, 8) + REGION(pdpt, ., 32, 32) + EARLY_RESERVED_DRAM_END(.) RAMSTAGE(CONFIG_RAMBASE, 8M) diff --git a/src/soc/amd/picasso/page_map_s3.txt b/src/soc/amd/picasso/page_map_s3.txt new file mode 100644 index 0000000..a03796f --- /dev/null +++ b/src/soc/amd/picasso/page_map_s3.txt @@ -0,0 +1,7 @@ +0xd0000000, 0x100000000, UC, NX # All of MMIO +0xff000000, 0x100000000, WP, # memory-mapped SPI +0xcbd0b000, 0xd0000000, WB, # RAM for CBMEM and FSP +0x100000, 0x3BD000, WB, # RAM for lower memory usage +0xFF000, 0x100000, WB, # RAM for FSP AP Reset Vectors [0xFF000 - 0xFF1A4] +0xE0000, 0x100000, WB, # ACPI Reset Vector search area +0x30000, 0x40000, WB, # RAM for SIPI -- To view, visit https://review.coreboot.org/c/coreboot/+/42888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fed6f297831b3cdc2758a5e7610388171d84d3 Gerrit-Change-Number: 42888 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: RFC: soc/amd/picasso: Enable paging for boot
by Raul Rangel (Code Review) 07 Aug '23

07 Aug '23

Hello Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42889 to review the following change. Change subject: RFC: soc/amd/picasso: Enable paging for boot ...................................................................... RFC: soc/amd/picasso: Enable paging for boot This is WIP because I think we should dynamically map the 0-4KiB page when we need to write to that range. Otherwise dereferencing a null pointer is valid. BUG=b:159081993 TEST=Boot trembyle to the OS. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5d027a71cd32f6240fa004d813513b84a1ecfd26 --- M src/arch/x86/ebda.c M src/arch/x86/tables.c M src/device/oprom/realmode/x86.c M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/bootblock/bootblock.c A src/soc/amd/picasso/page_map.txt 6 files changed, 65 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42889/1 diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index ea2d9d3..9c54359 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -5,6 +5,7 @@ #include <arch/ebda.h> #include <commonlib/endian.h> #include <console/console.h> +#include <cpu/x86/pae.h> static void *get_ebda_start(void) { @@ -29,7 +30,13 @@ ebda_kb = ebda_size >> 10; ebda = get_ebda_start(); - /* clear BIOS DATA AREA */ + /* + * We disable paging because the BDA is located between 0 - 4KiB. + * We don't want to map a page in this region because otherwise + * 0 will become a valid memory address + */ + paging_disable_pae(); + zero_n(X86_BDA_BASE, X86_BDA_SIZE); /* Avoid unaligned write16() since it's undefined behavior */ @@ -39,6 +46,8 @@ /* Set up EBDA */ zero_n(ebda, ebda_size); write_le16(ebda, ebda_kb); + + paging_enable_pae(); } void setup_default_ebda(void) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 492674c..3e2f19a 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -11,6 +11,7 @@ #include <string.h> #include <cbmem.h> #include <smbios.h> +#include <cpu/x86/pae.h> static unsigned long write_pirq_table(unsigned long rom_table_end) { @@ -200,8 +201,17 @@ if (CONFIG(GENERATE_SMBIOS_TABLES)) rom_table_end = write_smbios_table(rom_table_end); + /* + * We disable paging because the forwarding table is located + * between 0 - 4KiB. We don't want to map a page in this region because + * otherwise 0 will become a valid memory address + */ + paging_disable_pae(); + sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); + paging_enable_pae(); + forwarding_table += sz; /* Align up to page boundary for historical consistency. */ forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5215934..27bdf27 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -12,6 +12,7 @@ #include <pc80/i8254.h> #include <string.h> #include <vbe.h> +#include <cpu/x86/pae.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> @@ -303,6 +304,8 @@ { printk(BIOS_DEBUG, "VBE: Getting information about VESA mode %04x\n", mi->video_mode); + + paging_disable_pae(); char *buffer = PTR_TO_REAL_MODE(__realmode_buffer); u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00; u16 buffer_adr = ((unsigned long)buffer) & 0xffff; @@ -312,6 +315,9 @@ die("\nError: In %s function\n", __func__); memcpy(mi->mode_info_block, buffer, sizeof(mi->mode_info_block)); mode_info_valid = 1; + + paging_enable_pae(); + return 0; } @@ -322,10 +328,12 @@ mi->video_mode |= (1 << 14); // request clearing of framebuffer mi->video_mode &= ~(1 << 15); + paging_disable_pae(); X86_EAX = realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, 0x0000, 0x0000, 0x0000, 0x0000); if (vbe_check_for_failure(X86_AH)) die("\nError: In %s function\n", __func__); + paging_enable_pae(); return 0; } @@ -356,10 +364,13 @@ void vbe_textmode_console(void) { delay(2); + + paging_disable_pae(); X86_EAX = realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000); if (vbe_check_for_failure(X86_AH)) die("\nError: In %s function\n", __func__); + paging_enable_pae(); } int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) @@ -409,6 +420,13 @@ /* Set up C interrupt handlers */ setup_interrupt_handlers(); + /* + * We disable paging because the IDT and Option ROM are located between + * 0 - 4KiB. We don't want to map a page in this region because + * otherwise 0 will become a valid memory address. + */ + paging_disable_pae(); + /* Set up real-mode IDT */ setup_realmode_idt(); @@ -419,6 +437,9 @@ /* TODO ES:DI Pointer to System BIOS PnP Installation Check Structure */ /* Option ROM entry point is at OPROM start + 3 */ realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); + + paging_enable_pae(); + printk(BIOS_DEBUG, "... Option ROM returned.\n"); #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9d3bbd8..5b0be65 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -445,6 +445,17 @@ cpu_microcode_bins += $(wildcard 3rdparty/amd_blobs/picasso/PSP/UcodePatch_*.bin) +$(obj)/pt.c $(obj)/pdpt.c: src/soc/amd/picasso/page_map.txt $(DOTCONFIG) util/x86/x86_page_tables.go + go run util/x86/x86_page_tables.go --iomap_file=$< --metadata_base_address=$(CONFIG_PAGE_TABLE_ADDR) --pdpt_output_c_file=$(obj)/pdpt.c --pt_output_c_file=$(obj)/pt.c + +cbfs-files-y += pt +pt-file := $(obj)/pt.c:struct +pt-type := raw + +cbfs-files-y += pdpt +pdpt-file := $(obj)/pdpt.c:struct +pdpt-type := raw + $(obj)/pt_s3.c $(obj)/pdpt_s3.c: src/soc/amd/picasso/page_map_s3.txt $(DOTCONFIG) util/x86/x86_page_tables.go go run util/x86/x86_page_tables.go --iomap_file=$< --metadata_base_address=$(CONFIG_PAGE_TABLE_ADDR) --pdpt_output_c_file=$(obj)/pdpt_s3.c --pt_output_c_file=$(obj)/pt_s3.c diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index ec30c19..b82f99f 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -112,6 +112,9 @@ if (acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Enabling S3 page tables\n"); paging_enable_for_car("pdpt_s3", "pt_s3"); + } else { + printk(BIOS_DEBUG, "Enabling page tables\n"); + paging_enable_for_car("pdpt", "pt"); } } diff --git a/src/soc/amd/picasso/page_map.txt b/src/soc/amd/picasso/page_map.txt new file mode 100644 index 0000000..0fd224b --- /dev/null +++ b/src/soc/amd/picasso/page_map.txt @@ -0,0 +1,10 @@ +0xd0000000, 0x100000000, UC, NX # All of MMIO +0xff000000, 0x100000000, WP, # memory-mapped SPI +0xcbd0b000, 0xd0000000, WB, # RAM for CBMEM and FSP +0x30000000, 0x3023f000, WB, # RAM for payload +0x100000, 0x3BD000, WB, # RAM for lower memory usage +0xc0000, 0x100000, WB, # RAM for option ROM + EBDA [0xf6000 - 0xf6400] + IDT [0x0xff065 + 0xff84d + 0xff841 + 0xfec59 + 0xfe739 + 0xff859 + 0xfe82e + 0xfefd2 + 0xffe6e] +0xa0000, 0xc0000, UC, NX # VGA +0x30000, 0x40000, WB, # RAM for SIPI +0x1000, 0x2000, WB, # RAM for IDT stub code [0x1000 - 0x1900] +# 0x0, 0x1000, WB, # RAM for BDA [0x400 - 0x600] + CB forwarding table [0x500 - 0x1000] -- To view, visit https://review.coreboot.org/c/coreboot/+/42889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d027a71cd32f6240fa004d813513b84a1ecfd26 Gerrit-Change-Number: 42889 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: post_code: add missing postcode calls
by Sindhoor Tilak (Code Review) 07 Aug '23

07 Aug '23

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43000 ) Change subject: post_code: add missing postcode calls ...................................................................... post_code: add missing postcode calls The change adds postcode calls wherever necessary on top of the updated set of postcode defines Change-Id: Ia75cd863bf6ffac2c91ff78aefabc5327b1c138b Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> --- M src/arch/x86/postcar_loader.c M src/console/init.c M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/haswell/romstage.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/northbridge/intel/sandybridge/raminit_mrc.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/xeon_sp/romstage.c 10 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/43000/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index f79c90c..7b3088f 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -104,6 +104,7 @@ postcar_frame_common_mtrrs(pcf); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(pcf); /* We do not return here. */ } diff --git a/src/console/init.c b/src/console/init.c index 1dba9ad..cfe2e2e 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -62,6 +62,7 @@ asmlinkage void console_init(void) { + post_code(POST_CONSOLE_READY); init_log_level(); if (CONFIG(DEBUG_CONSOLE_INIT)) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 7a96441..e0cebc1 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -20,6 +20,7 @@ xor %edx, %edx clear_fixed_mtrr: + post_code(POST_CAR_FIXED_MTRR) add $-2, %ebx movzwl fixed_mtrr_list(%ebx), %ecx wrmsr diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 6481404..6ddcf19 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,6 +23,7 @@ andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax jz ap_init + post_code(POST_CAR_FIXED_MTRR) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 35566c4..f3090e7 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -18,6 +18,7 @@ int boot_mode; int wake_from_s3; + post_code(POST_ENTRY_ROMSTAGE); enable_lapic(); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 617416a..4a65cab 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -84,6 +84,7 @@ postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE); recover_postcar_frame(&pcf, cb->s3resume); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); /* We do not return. */ } diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 2a7678e..8ffcbcc 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -51,12 +51,14 @@ movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + post_code(POST_CAR_INIT_CACHE) /* Enable cache */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 + post_code(POST_CAR_MTRR_ENABLE) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index aa7d677..aaa7f81 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -363,6 +363,7 @@ pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); + post_code(POST_ROM_SDRAM_INIT); sdram_initialize(&pei_data); /* Sanity check mrc_var location by verifying a known field */ diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 5932fe6..69633ae 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -87,6 +87,7 @@ movd %mm1, %eax push %eax + post_code(POST_ENTRY_C_BOOTBLOCK) /* We can call into C functions now */ call bootblock_c_entry diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 02ed7eb..86e121e 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -41,6 +41,7 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + post_code(POST_ENTRY_POST_CAR); run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia75cd863bf6ffac2c91ff78aefabc5327b1c138b Gerrit-Change-Number: 43000 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 17

Change in coreboot[master]: post_code: delete unneeded postcode calls
by Sindhoor Tilak (Code Review) 07 Aug '23

07 Aug '23

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43132 ) Change subject: post_code: delete unneeded postcode calls ...................................................................... post_code: delete unneeded postcode calls This change removes postcode calls that are either duplicated or not needed anymore Change-Id: I44e94e64585cdaf9f3d6506fc92e1845c39254f1 Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/bootblock.c M src/drivers/intel/fsp1_1/romstage.c M src/mainboard/amd/thatcher/bootblock.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 12 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43132/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index c3f81fa..c59cfb4 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -87,7 +87,6 @@ xorl %edx, %edx wrmsr - post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 6095126..5f6e9f5 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -92,7 +92,6 @@ xorl %edx, %edx wrmsr - post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 4cfe75c..b137e77 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -34,7 +34,6 @@ andl $~1, %eax wrmsr - post_code(0x32) /* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 1cb0cc7..56bb5f3 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -49,7 +49,6 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 5489bb4..d0e3ee0 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -25,7 +25,6 @@ andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x32) /* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index f3090e7..7a666b0 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -46,7 +46,6 @@ if (wake_from_s3) enable_usb_bar(); - post_code(0x3a); params->pei_data->boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 1b46403e..99b9939 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -6,7 +6,6 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - post_code(0x05); /* Halt if there was a built in self test failure */ if (bist) { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index cf11179..58206b2 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -100,7 +100,6 @@ .chipset_context = fih, }; - post_code(0x30); timestamp_add_now(TS_START_ROMSTAGE); diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index ae76b72..cf23654 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -10,7 +10,6 @@ void bootblock_mainboard_early_init(void) { - post_code(0x30); post_code(POST_ROM_SOC_EARLY_INIT); gpio_100_write8(0x1, 0x98); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d2833d7..6278cac 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -78,5 +78,4 @@ northbridge_romstage_finalize(s3resume); - post_code(0x3f); } diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index f8cff23..ea2c920 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -83,7 +83,6 @@ mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); - post_code(0x42); u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2493b41..2ab502c 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -34,7 +34,6 @@ { struct romstage_params rp = { 0 }; - post_code(0x30); /* System Agent Early Initialization */ systemagent_early_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/43132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44e94e64585cdaf9f3d6506fc92e1845c39254f1 Gerrit-Change-Number: 43132 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [TESTME] nb/intel/i945/early_init.c: Detect DMI link width
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43226 ) Change subject: [TESTME] nb/intel/i945/early_init.c: Detect DMI link width ...................................................................... [TESTME] nb/intel/i945/early_init.c: Detect DMI link width UNTESTED. Change-Id: I79829fa8fc9b26abca9983b1e3dc3a137a0ba49b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43226/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f388330..cb5b520 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -399,11 +399,12 @@ reg32 = DMIBAR32(0x204); reg32 &= ~0x3ff; -#if 1 - reg32 |= 0x13f; /* for x4 DMI only */ -#else - reg32 |= 0x1e4; /* for x2 DMI only */ -#endif + + if (((DMIBAR16(DMILSTS) >> 4) & 0xf) == 2) + reg32 |= 0x1e4; /* for x2 DMI only */ + else + reg32 |= 0x13f; /* for x4 DMI only */ + DMIBAR32(0x204) = reg32; if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/43226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79829fa8fc9b26abca9983b1e3dc3a137a0ba49b Gerrit-Change-Number: 43226 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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