coreboot-gerrit July 2020

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Change in coreboot[master]: soc/intel/gpio: convert PAD_CFG0_RX_POL_* to PAD_RX_POL()
by Maxim Polyakov (Code Review) 12 Jul '20

12 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41033 ) Change subject: soc/intel/gpio: convert PAD_CFG0_RX_POL_* to PAD_RX_POL() ...................................................................... soc/intel/gpio: convert PAD_CFG0_RX_POL_* to PAD_RX_POL() Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code cleaner and reduce the length of the macro. Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/41033/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 90e669d..ecc9489 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -137,6 +137,7 @@ #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value +#define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value #define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value @@ -160,14 +161,14 @@ #define PAD_IRQ_CFG(route, trig, inv) \ (PAD_CFG0_ROUTE_##route | \ PAD_TRIG(trig) | \ - PAD_CFG0_RX_POL_##inv) + PAD_RX_POL(inv)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ (PAD_CFG0_ROUTE_##route1 | \ PAD_CFG0_ROUTE_##route2 | \ PAD_TRIG(trig) | \ - PAD_CFG0_RX_POL_##inv) + PAD_RX_POL(inv)) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ @@ -292,7 +293,7 @@ #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_TRIG(trig) | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ @@ -305,7 +306,7 @@ #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE), \ + PAD_RX_POL(NONE) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) -- To view, visit https://review.coreboot.org/c/coreboot/+/41033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546 Gerrit-Change-Number: 41033 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: intel/gpio: convert PAD_CFG0_TRIG_* to PAD_TRIG()
by Maxim Polyakov (Code Review) 12 Jul '20

12 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41032 ) Change subject: intel/gpio: convert PAD_CFG0_TRIG_* to PAD_TRIG() ...................................................................... intel/gpio: convert PAD_CFG0_TRIG_* to PAD_TRIG() Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner and reduce the length of the macro, which is often used. Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 18 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41032/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index d6c0287..90e669d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -137,6 +137,7 @@ #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value +#define PAD_TRIG(value) PAD_CFG0_TRIG_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value /* Disable the input/output buffer of the pad */ @@ -158,14 +159,14 @@ #define PAD_IRQ_CFG(route, trig, inv) \ (PAD_CFG0_ROUTE_##route | \ - PAD_CFG0_TRIG_##trig | \ + PAD_TRIG(trig) | \ PAD_CFG0_RX_POL_##inv) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ (PAD_CFG0_ROUTE_##route1 | \ PAD_CFG0_ROUTE_##route2 | \ - PAD_CFG0_TRIG_##trig | \ + PAD_TRIG(trig) | \ PAD_CFG0_RX_POL_##inv) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */ @@ -192,7 +193,7 @@ /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* @@ -200,7 +201,7 @@ * input/output buffer if necessary */ #define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_##trig | \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_TRIG(trig) | \ PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) @@ -210,62 +211,62 @@ */ #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) #endif /* Native function configuration for standby state */ #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) /* Native function configuration for standby state, also configuring iostandby as masked */ #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(IGNORE)) /* Native function configuration for standby state, also configuring iosstate and iosterm */ #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* Configure native function, iosstate, iosterm and disable input/output buffer */ #define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_BUF(bufdis) | PAD_FUNC(func), \ + PAD_RESET(rst) | PAD_TRIG(OFF) | PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG_OWN_GPIO(DRIVER)) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ @@ -291,13 +292,13 @@ #define PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(trig) | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(own)) #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(TX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | \ PAD_IOSSTATE(TxDRxE)) @@ -311,7 +312,7 @@ #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* GPIO Interrupt */ @@ -326,7 +327,7 @@ #define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ - PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) -- To view, visit https://review.coreboot.org/c/coreboot/+/41032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9 Gerrit-Change-Number: 41032 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/intel/tglrvp: Add SMI handler for tglrvp
by John Zhao (Code Review) 12 Jul '20

12 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42957 ) Change subject: mb/intel/tglrvp: Add SMI handler for tglrvp ...................................................................... mb/intel/tglrvp: Add SMI handler for tglrvp This change adds SMI handler for SCI, S3/S5 wake up and LID closed events on tglrvp platform. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f --- M src/mainboard/intel/tglrvp/Makefile.inc A src/mainboard/intel/tglrvp/smihandler.c 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/42957/1 diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index fbdac4d..065bd4c 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -11,6 +11,8 @@ romstage-y += romstage_fsp_params.c romstage-y += board_id.c +smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c new file mode 100644 index 0000000..8c9444c --- /dev/null +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -0,0 +1,28 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f Gerrit-Change-Number: 42957 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/tglrvp: Add EC_HOST_EVENT_USB_MUX for tglrvp
by John Zhao (Code Review) 12 Jul '20

12 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42955 ) Change subject: mb/intel/tglrvp: Add EC_HOST_EVENT_USB_MUX for tglrvp ...................................................................... mb/intel/tglrvp: Add EC_HOST_EVENT_USB_MUX for tglrvp This change allows EC to change state of host-controlled USB MUX. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ia7c331157b1b4039e42c373f5b130a66f7594458 --- M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/42955/1 diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index f05cb77..cbdb423 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -21,7 +21,8 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) -- To view, visit https://review.coreboot.org/c/coreboot/+/42955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7c331157b1b4039e42c373f5b130a66f7594458 Gerrit-Change-Number: 42955 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton: Avoid NULL pointer dereference
by John Zhao (Code Review) 12 Jul '20

12 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42839 ) Change subject: superio/nuvoton: Avoid NULL pointer dereference ...................................................................... superio/nuvoton: Avoid NULL pointer dereference Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. Found-by: Coverity CID 1420207 Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Icc253c63aadef1c0ecb116a38b608f64f80abc79 --- M src/superio/nuvoton/npcd378/superio.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42839/1 diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index 628bd4e..46923e0 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -325,7 +325,8 @@ acpigen_pop_len(); /* Pop Scope */ /* Inject into parent: */ - acpigen_write_scope(acpi_device_scope(dev)); + if (scope) + acpigen_write_scope(scope); acpigen_write_name_integer("MSFG", 1); acpigen_write_name_integer("KBFG", 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/42839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc253c63aadef1c0ecb116a38b608f64f80abc79 Gerrit-Change-Number: 42839 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Deselect PCIEXP_CLK_PM and L1_SUB_STATE
by Christian Walter (Code Review) 12 Jul '20

12 Jul '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43179 ) Change subject: mb/prodrive/hermes: Deselect PCIEXP_CLK_PM and L1_SUB_STATE ...................................................................... mb/prodrive/hermes: Deselect PCIEXP_CLK_PM and L1_SUB_STATE Set default of PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE to n as this breaks booting Windows with a PCIE NVIDIA. Change-Id: Ie8768b91c27c4159f9b3c7f94699134a82decea0 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/prodrive/hermes/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/43179/1 diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index 3a74ce5..6a79f5b 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -33,6 +33,14 @@ string default "prodrive/hermes" +config PCIEXP_L1_SUB_STATE + bool + default n + +config PCIEXP_CLK_PM + bool + default n + config VARIANT_DIR string default "baseboard" if BOARD_PRODRIVE_HERMES_BASEBOARD -- To view, visit https://review.coreboot.org/c/coreboot/+/43179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8768b91c27c4159f9b3c7f94699134a82decea0 Gerrit-Change-Number: 43179 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/common/block/pcie: Remove auto-select ASPM and L1_SUB_STATE
by Christian Walter (Code Review) 12 Jul '20

12 Jul '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41696 ) Change subject: soc/intel/common/block/pcie: Remove auto-select ASPM and L1_SUB_STATE ...................................................................... soc/intel/common/block/pcie: Remove auto-select ASPM and L1_SUB_STATE Current the common soc code automatically selects PCIEXP_ASPM and PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA graphics card attached. Tested on CFL with Windows 10 Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/common/block/pcie/Kconfig 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/41696/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index aa32324..308f197 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -1,9 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_PCIE bool - select PCIEXP_ASPM - select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE help Intel Processor common PCIE support -- To view, visit https://review.coreboot.org/c/coreboot/+/41696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7 Gerrit-Change-Number: 41696 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Convert static ASL files to new DPTF implementation
by Tim Wawrzynczak (Code Review) 12 Jul '20

12 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41895 ) Change subject: mb/google/volteer: Convert static ASL files to new DPTF implementation ...................................................................... mb/google/volteer: Convert static ASL files to new DPTF implementation This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/baseboard/devicetree.cb D src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl D src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl 8 files changed, 93 insertions(+), 151 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/41895/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 63e70c5..7bb6d64 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -5,6 +5,7 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index c6a2e8b..a02d30f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -224,7 +224,98 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + register "policies.enabled.passive" = "1" + register "policies.enabled.critical" = "1" + register "policies.enabled.active" = "1" + + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, .thresholds={ + {.temp=85, .fan_pct=90}, + {.temp=80, .fan_pct=69}, + {.temp=75, .fan_pct=56}, + {.temp=70, .fan_pct=46}, + {.temp=65, .fan_pct=36}}}" + register "policies.active[1]" = "{.target=DPTF_TSR0, .thresholds={ + {.temp=50, .fan_pct=90}, + {.temp=47, .fan_pct=69}, + {.temp=45, .fan_pct=56}, + {.temp=42, .fan_pct=46}, + {.temp=39, .fan_pct=36}}}" + register "policies.active[2]" = "{.target=DPTF_TSR1, .thresholds={ + {.temp=50, .fan_pct=90}, + {.temp=47, .fan_pct=69}, + {.temp=45, .fan_pct=56}, + {.temp=42, .fan_pct=46}, + {.temp=39, .fan_pct=36}}}" + register "policies.active[3]" = "{.target=DPTF_TSR2, .thresholds={ + {.temp=50, .fan_pct=90}, + {.temp=47, .fan_pct=69}, + {.temp=45, .fan_pct=56}, + {.temp=42, .fan_pct=46}, + {.temp=39, .fan_pct=36}}}" + + ## Passive Policy + register "policies.passive[0]" = "{.source=DPTF_CPU, .target=DPTF_CPU, .temp=95, .period=5000}" + register "policies.passive[1]" = "{.source=DPTF_CPU, .target=DPTF_TSR0, .temp=65, .period=6000}" + register "policies.passive[2]" = "{.source=DPTF_CHARGER, .target=DPTF_TSR1, .temp=65, .period=6000}" + register "policies.passive[3]" = "{.source=DPTF_CPU, .target=DPTF_TSR2, .temp=65, .period=6000}" + + ## Critical Policy + register "policies.critical[0]" = "{.source=DPTF_CPU, .temp=105, .type=DPTF_CRITICAL_SUSPEND}" + register "policies.critical[1]" = "{.source=DPTF_TSR0, .temp=75, .type=DPTF_CRITICAL_SUSPEND}" + register "policies.critical[2]" = "{.source=DPTF_TSR1, .temp=75, .type=DPTF_CRITICAL_SUSPEND}" + register "policies.critical[3]" = "{.source=DPTF_TSR2, .temp=75, .type=DPTF_CRITICAL_SUSPEND}" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28s interval + # PL2 is fixed at 64W, avg over 28s interval + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28000, + .time_window_max = 32000, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28000, + .time_window_max = 32000, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + # TSR hysteresis + register "options.tsr[0].hysteresis" = "2" + register "options.tsr[1].hysteresis" = "2" + register "options.tsr[2].hysteresis" = "2" + register "options.tsr[3].hysteresis" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device pci 05.0 off end # IPU 0x9A19 device pci 06.0 off end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl deleted file mode 100644 index cef895b..0000000 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 105 -#define DPTF_CPU_ACTIVE_AC0 85 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 75 -#define DPTF_CPU_ACTIVE_AC3 70 -#define DPTF_CPU_ACTIVE_AC4 65 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 39 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 - -#define DPTF_TSR2_SENSOR_ID 1 -#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor 3" -#define DPTF_TSR2_PASSIVE 65 -#define DPTF_TSR2_CRITICAL 75 -#define DPTF_TSR2_ACTIVE_AC0 50 -#define DPTF_TSR2_ACTIVE_AC1 47 -#define DPTF_TSR2_ACTIVE_AC2 45 -#define DPTF_TSR2_ACTIVE_AC3 42 -#define DPTF_TSR2_ACTIVE_AC4 39 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - } -}) - - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on TSR0 sensor */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on TSR2 sensor */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ - 60000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl deleted file mode 100644 index 726e381..0000000 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include <baseboard/acpi/dptf.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/41895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Gerrit-Change-Number: 41895 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: mb/google/dedede: Add ability to provide override GPIO table
by Karthik Ramasubramanian (Code Review) 12 Jul '20

12 Jul '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43279 ) Change subject: mb/google/dedede: Add ability to provide override GPIO table ...................................................................... mb/google/dedede: Add ability to provide override GPIO table For variants with slightly different GPIO configuration, add support to pass an override GPIO configuration table. BUG=None TEST=Build and boot the waddledee mainboard. Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h 3 files changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/43279/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index fe89527..cb84e1f 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -22,11 +22,15 @@ static void mainboard_init(void *chip_info) { - const struct pad_config *pads; - size_t num; + const struct pad_config *base_pads; + const struct pad_config *override_pads; + size_t base_num, override_num; - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); + base_pads = variant_base_gpio_table(&base_num); + override_pads = variant_override_gpio_table(&override_num); + + gpio_configure_pads_with_override(base_pads, base_num, + override_pads, override_num); } static void mainboard_dev_init(struct device *dev) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 71c0c14..1284bc5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -420,12 +420,18 @@ PAD_CFG_GPI(GPP_S0, NONE, DEEP), }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *__weak variant_base_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + const struct pad_config *__weak variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index 5d8355b..1f40443 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -13,10 +13,11 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ -const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_base_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +const struct pad_config *variant_override_gpio_table(size_t *num); /** * Get board's Hardware features as defined in FW_CONFIG -- To view, visit https://review.coreboot.org/c/coreboot/+/43279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a Gerrit-Change-Number: 43279 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/ocp/deltalake: Pull POST complete pin low before booting payload
by Johnny Lin (Code Review) 12 Jul '20

12 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43162 ) Change subject: mb/ocp/deltalake: Pull POST complete pin low before booting payload ...................................................................... mb/ocp/deltalake: Pull POST complete pin low before booting payload Delta Lake uses GPIO pin GPP_B20 for POST complete event, BIOS needs to pull this pin low for BIC (Bridge IC) to start reading sensors. Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm the pin is low. Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/43162/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 9380304..88f89b5 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <gpio.h> +#include <soc/lewisburg_pch_gpio_defs.h> #include <soc/ramstage.h> #include <stdio.h> @@ -92,3 +95,11 @@ .enable_dev = mainboard_enable, .final = mainboard_final, }; + +static void pull_post_complete_pin(void *unused) +{ + /* Pull Low post complete pin */ + gpio_output(GPP_B20, 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/43162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd Gerrit-Change-Number: 43162 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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