coreboot-gerrit June 2020

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Change in coreboot[master]: drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1
by Jonathan Zhang (Code Review) 25 Jun '20

25 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42487 ) Change subject: drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1 ...................................................................... drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1 Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/42487/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index c7c44cd..f6395c5 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -11,12 +11,10 @@ default n select PLATFORM_USES_FSP2_0 select FSP_USES_CB_STACK - select FSP_PEIM_TO_PEIM_INTERFACE help Include FSP 2.1 wrappers and functionality. - Features added into FSP 2.1 specification that impacts coreboot are: + Feature added into FSP 2.1 specification that impacts coreboot is: 1. Remove FSP stack switch and use the same stack with boot firmware - 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE config PLATFORM_USES_FSP2_2 bool diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..3c29b24 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -61,7 +61,7 @@ config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 + default y if FSP_PEIM_TO_PEIM_INTERFACE default n help This option allows FSP to make use of MP services PPI published by diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 83a62ca..f58aa33 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,6 +31,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 4e514c4..2a8391e 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -32,6 +32,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index a61cbfc..a00b33d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -32,6 +32,7 @@ select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/42487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Gerrit-Change-Number: 42487 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/xeon_sp: use edk2-stable202005
by Jonathan Zhang (Code Review) 25 Jun '20

25 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42240 ) Change subject: soc/intel/xeon_sp: use edk2-stable202005 ...................................................................... soc/intel/xeon_sp: use edk2-stable202005 Use edk2-stable202005 header files instead of UDK2017 header files, since FSP uses latest EDK2 code base. TESTED=Booted OCP Delta Lake server to OS. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I3c845bceb201d4ffdf5adbf2af9aad6d6794a19d --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42240/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 8e39b77..ea48ff9 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -68,7 +68,7 @@ def_bool y depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 - select UDK_2017_BINDING + select UDK_202005_BINDING select POSTCAR_CONSOLE select POSTCAR_STAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/42240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c845bceb201d4ffdf5adbf2af9aad6d6794a19d Gerrit-Change-Number: 42240 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: vendorcode/intel: Add edk2-stable202005 support
by Jonathan Zhang (Code Review) 25 Jun '20

25 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42239 ) Change subject: vendorcode/intel: Add edk2-stable202005 support ...................................................................... vendorcode/intel: Add edk2-stable202005 support This patch includes (edk2/edk2-stable202005) all required headers for edk2-stable202005 quaterly EDK2 tag from EDK2 github project using below command: >> git clone https://github.com/tianocore/edk2.git vedk2-stable202005 Only included necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safe guarding definitions for MIX, MAX, NULL, ABS, ARRAY_SIZE. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I3172505d9b829647ee1208c87623172f10b39310 --- M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.inc A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspEas/FspApi.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspGlobalData.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspMeasurePointId.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/FspStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/CacheLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/FspCommonLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/FspPlatformLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h A src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/AArch64/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Arm/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Base.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ebc/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/Acpi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/Apriori.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/AprioriFileName.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/Btt.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/CapsuleReport.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/Cper.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/DebugImageInfoTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/DxeServices.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/EventGroup.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/EventLegacyBios.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FileInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FileSystemInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FirmwareContentsSigned.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FirmwareFileSystem2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FirmwareFileSystem3.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/FmpCapsule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/GlobalVariable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/Gpt.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/GraphicsInfoHob.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/HardwareErrorVariable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/HiiFormMapMethodGuid.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/HiiKeyBoardLayout.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/HiiPlatformSetupFormset.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/HobList.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/ImageAuthentication.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/JsonCapsule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/MdePkgTokenSpace.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/MemoryAllocationHob.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/MemoryAttributesTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/MemoryOverwriteControl.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/Mps.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/PcAnsi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/RtPropertiesTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/SmBios.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/SmramMemoryReserve.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/StatusCodeDataTypeId.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/SystemResourceTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/VectorHandoffTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Guid/WinCertificate.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32/Nasm.inc A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ia32/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi10.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi20.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi30.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi40.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi50.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi51.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi60.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi61.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi62.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Acpi63.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/AcpiAml.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Atapi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Bluetooth.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Bmp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/DebugPort2Table.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/DebugPortTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Dhcp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/ElTorito.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Emmc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Hsti.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Http11.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IoRemappingTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Ipmi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Mbr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Nvme.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci23.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci30.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PciCodeId.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PciExpress21.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PciExpress30.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PciExpress31.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PciExpress40.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PciExpress50.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/PeImage.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Scsi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Sd.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpd.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SmBios.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SmBus.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Spdm.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/TcgStorageCore.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/TcgStorageOpal.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/TcpaAcpi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tls1.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm12.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm20.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Tpm2Acpi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/TpmPtp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/TpmTis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Udf.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Usb.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/WatchdogActionTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/BaseLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/BaseMemoryLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/CacheMaintenanceLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/CpuLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/DebugLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/DebugPrintErrorLevelLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/DevicePathLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/DxeCoreEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/DxeServicesLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/DxeServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/ExtractGuidedSectionLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/FileHandleLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/HobLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/HstiLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/IoLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/MemoryAllocationLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/MmServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/OrderedCollectionLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PcdLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PciCf8Lib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PciExpressLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PciLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PciSegmentInfoLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PciSegmentLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeCoffExtraActionLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeCoffGetEntryPointLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeCoffLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeiCoreEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeiServicesLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeiServicesTablePointerLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PeimEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PerformanceLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PostCodeLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/PrintLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/ReportStatusCodeLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/ResourcePublicationLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/RngLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/S3BootScriptLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/S3IoLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/S3PciLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/S3PciSegmentLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/S3SmbusLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/S3StallLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SafeIntLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SerialPortLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmbusLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmiHandlerProfileLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmmIoLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmmLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmmMemLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmmPeriodicSmiLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SmmServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/SynchronizationLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/TimerLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiApplicationEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiBootServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiDecompressLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiDriverEntryPoint.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiRuntimeLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiScsiLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UefiUsbLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Library/UnitTestLib.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiBootMode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiDependency.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiDxeCis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiFirmwareFile.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiFirmwareVolume.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiHob.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiI2c.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiMmCis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiMultiPhase.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiPeiCis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiS3BootScript.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiSmmCis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Pi/PiStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/PiDxe.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/PiMm.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/PiPei.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/PiSmm.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/BlockIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/BlockIo2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/BootInRecoveryMode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Capsule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/CpuIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Decompress.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/DelayedDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/DeviceRecoveryModule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/DxeIpl.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/EndOfPeiPhase.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/FirmwareVolume.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/FirmwareVolumeInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Graphics.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/GuidedSectionExtraction.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/I2cMaster.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/IsaHc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/LoadFile.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/LoadImage.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MasterBootMode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MemoryDiscovered.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MmAccess.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MmControl.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Pcd.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/PcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/PciCfg2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/PeiCoreFvLocation.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/PiPcd.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/PiPcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/ReadOnlyVariable2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/RecoveryModule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/ReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Reset.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Reset2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/S3Resume2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/SecHobData.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/SecPlatformInformation.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/SecPlatformInformation2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Security2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Smbus2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/Stall.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/StatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/SuperIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/TemporaryRamDone.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/TemporaryRamSupport.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/VectorHandoffInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/AbsolutePointer.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/AcpiTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/AdapterInformation.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Arp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/AtaPassThru.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/AuthenticationInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Bds.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Bis.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BlockIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BlockIo2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BlockIoCrypto.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BluetoothAttribute.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BluetoothConfig.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BluetoothHc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BluetoothIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BluetoothLeConfig.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BootManagerPolicy.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/BusSpecificDriverOverride.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Capsule.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ComponentName.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ComponentName2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Cpu.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/CpuIo2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DebugPort.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DebugSupport.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Decompress.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DeferredImageLoad.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DeviceIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DevicePath.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DevicePathFromText.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DevicePathToText.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DevicePathUtilities.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Dhcp4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Dhcp6.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DiskInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DiskIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DiskIo2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Dns4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Dns6.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverBinding.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverConfiguration2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverDiagnostics.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverDiagnostics2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverFamilyOverride.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverHealth.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DxeMmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/DxeSmmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Eap.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EapConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EapManagement.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EapManagement2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ebc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EdidActive.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EdidDiscovered.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EdidOverride.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/EraseBlock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/FirmwareManagement.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/FirmwareVolume2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/FirmwareVolumeBlock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/FormBrowser2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ftp4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/GraphicsOutput.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/GuidedSectionExtraction.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Hash.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Hash2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiConfigAccess.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiConfigKeyword.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiConfigRouting.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiDatabase.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiFont.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiImage.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiImageDecoder.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiImageEx.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiPackageList.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiPopup.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HiiString.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Http.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HttpBootCallback.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/HttpUtilities.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/I2cEnumerate.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/I2cHost.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/I2cIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/I2cMaster.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/IScsiInitiatorName.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/IdeControllerInit.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ip4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ip4Config.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ip4Config2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ip6.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Ip6Config.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/IpSec.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/IpSecConfig.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/IsaHc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Kms.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LegacyRegion2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LegacySpiController.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LegacySpiFlash.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LegacySpiSmmController.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LegacySpiSmmFlash.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LoadFile.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LoadFile2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/LoadedImage.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ManagedNetwork.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Metronome.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmAccess.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmBase.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmCommunication.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmCommunication2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmControl.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmCpu.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmCpuIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmEndOfDxe.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmGpiDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmIoTrapDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmMp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmPciRootBridgeIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmPowerButtonDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmSwDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmSxDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MmUsbDispatch.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MonotonicCounter.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/MpService.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Mtftp4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Mtftp6.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/NvdimmLabel.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/NvmExpressPassthru.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PartitionInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Pcd.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciEnumerationComplete.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciHotPlugInit.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciHotPlugRequest.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciOverride.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciPlatform.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PciRootBridgeIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PiPcd.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PiPcdInfo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Pkcs7Verify.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PlatformDriverOverride.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PxeBaseCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/RamDisk.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/RealTimeClock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/RegularExpressionProtocol.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Reset.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ResetNotification.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Rest.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Rng.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Runtime.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/S3SaveState.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/S3SmmSaveState.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ScsiIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ScsiPassThru.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ScsiPassThruExt.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SdMmcPassThru.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Security.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Security2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SecurityPolicy.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SerialIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ServiceBinding.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Shell.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ShellDynamicCommand.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/ShellParameters.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SimpleFileSystem.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SimpleNetwork.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SimplePointer.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SimpleTextIn.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SimpleTextInEx.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SimpleTextOut.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmartCardEdge.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmartCardReader.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Smbios.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmbusHc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmAccess2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmBase2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmCommunication.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmControl2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmCpu.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmCpuIo2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmEndOfDxe.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmGpiDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmReadyToLock.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmSwDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmSxDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SmmUsbDispatch2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiHc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiNorFlash.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiSmmConfiguration.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiSmmHc.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SpiSmmNorFlash.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/StatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/StorageSecurityCommand.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SuperIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/SuperIoControl.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Supplicant.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/TapeIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Tcg2Protocol.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/TcgService.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Tcp4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Tcp6.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Timer.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Timestamp.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Tls.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/TlsConfig.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/TrEEProtocol.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Udp4.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Udp6.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UfsDeviceConfig.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UgaDraw.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UgaIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UnicodeCollation.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Usb2HostController.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UsbFunctionIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UsbHostController.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UsbIo.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UserCredential.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UserCredential2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/UserManager.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/Variable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/VariableWrite.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/VlanConfig.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/WatchdogTimer.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/WiFi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Protocol/WiFi2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Amd/Cpuid.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Amd/Fam17Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Amd/Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/ArchitecturalMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Cpuid.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/LocalApic.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Microcode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/AtomMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/Core2Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/CoreMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/P6Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/SmramSaveStateMap.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/StmApi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/StmResourceDescriptor.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Register/Intel/StmStatusCode.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/RiscV64/ProcessorBind.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiAcpiDataTable.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiBaseType.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiGpt.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiMultiPhase.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiPxe.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Uefi/UefiSpec.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64/Nasm.inc A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/X64/ProcessorBind.h 569 files changed, 232,126 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42239/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3172505d9b829647ee1208c87623172f10b39310 Gerrit-Change-Number: 42239 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: vendorcode/google/chromeos: Add GOOG0016 _HID for Chrome OS ACPI
by Duncan Laurie (Code Review) 25 Jun '20

25 Jun '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42735 ) Change subject: vendorcode/google/chromeos: Add GOOG0016 _HID for Chrome OS ACPI ...................................................................... vendorcode/google/chromeos: Add GOOG0016 _HID for Chrome OS ACPI The Chrome OS ACPI code has always used a legacy PNP ID "GGL0001" for the ID. This is technically valid but we have an official ACPI ID now so I allocated "GOOG0016" for an ID and we can eventually retire the legacy PNP ID. This is being discussed on LKML as part of an effort to upstream the Chrome OS ACPI kernel driver: https://lkml.org/lkml/2020/4/13/315 Change-Id: I2e41fe419113b327618f8f98058ef7af657f2532 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/vendorcode/google/chromeos/acpi/chromeos.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/42735/1 diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 5c8af4e..7642676 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -9,7 +9,8 @@ Device (CRHW) { - Name(_HID, EISAID("GGL0001")) + Name(_HID, "GOOG0016") + Name(_CID, EISAID("GGL0001")) Method(_STA, 0, Serialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e41fe419113b327618f8f98058ef7af657f2532 Gerrit-Change-Number: 42735 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: arch/x86/smbios: Add more fields to be overriden for type 3 and 4
by Patrick Georgi (Code Review) 25 Jun '20

25 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40309 ) Change subject: arch/x86/smbios: Add more fields to be overriden for type 3 and 4 ...................................................................... arch/x86/smbios: Add more fields to be overriden for type 3 and 4 For type 3, override chassis asset_tag_number with smbios_mainboard_asset_tag() and add two functions that can override chassis version and serial_number. For type 4 add smbios_processor_serial_number() to override serial_number. Tested on OCP Tioga Pass. Change-Id: I80c6244580a4428fab781d760071c51c7933abee Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40309 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index ee69408..a8723aa 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -539,6 +539,21 @@ return ""; } +const char * __weak smbios_chassis_version(void) +{ + return ""; +} + +const char * __weak smbios_chassis_serial_number(void) +{ + return ""; +} + +const char * __weak smbios_processor_serial_number(void) +{ + return ""; +} + static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) @@ -621,6 +636,9 @@ t->thermal_state = SMBIOS_STATE_SAFE; t->_type = smbios_mainboard_enclosure_type(); t->security_status = SMBIOS_STATE_SAFE; + t->asset_tag_number = smbios_add_string(t->eos, smbios_mainboard_asset_tag()); + t->version = smbios_add_string(t->eos, smbios_chassis_version()); + t->serial_number = smbios_add_string(t->eos, smbios_chassis_serial_number()); len = t->length + smbios_string_table_len(t->eos); *current += len; return len; @@ -674,6 +692,7 @@ t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; + t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number()); t->processor_upgrade = get_socket_type(); len = t->length + smbios_string_table_len(t->eos); if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { diff --git a/src/include/smbios.h b/src/include/smbios.h index d281bf0..9edf284 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -50,6 +50,9 @@ const char *smbios_mainboard_asset_tag(void); u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); +const char *smbios_chassis_version(void); +const char *smbios_chassis_serial_number(void); +const char *smbios_processor_serial_number(void); #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) -- To view, visit https://review.coreboot.org/c/coreboot/+/40309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c6244580a4428fab781d760071c51c7933abee Gerrit-Change-Number: 40309 Gerrit-PatchSet: 28 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/ipmi: Add IPMI read FRU chassis info area
by Patrick Georgi (Code Review) 25 Jun '20

25 Jun '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40306 ) Change subject: drivers/ipmi: Add IPMI read FRU chassis info area ...................................................................... drivers/ipmi: Add IPMI read FRU chassis info area Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Chassis Info Area. Tested on OCP Tioga Pass. Change-Id: Ieb53c20f8eb4b7720bf1fe349e6aaebaa4c37247 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40306 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_ops.h 2 files changed, 110 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 506e207..9cfe893 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -11,6 +11,7 @@ #define READ_FRU_DATA_RETRY_INTERVAL_MS 30 /* From IPMI spec v2.0 rev 1.1 */ #define OFFSET_LENGTH_MULTIPLIER 8 /* offsets/lengths are multiples of 8 */ #define NUM_DATA_BYTES(t) (t & 0x3f) /* Encoded in type/length byte */ +#define FRU_END_OF_FIELDS 0xc1 /* type/length byte encoded to indicate no more info fields */ static enum cb_err ipmi_read_fru(const int port, struct ipmi_read_fru_data_req *req, uint8_t *fru_data) @@ -120,6 +121,98 @@ return length; } + +static enum cb_err read_fru_chassis_info_area(const int port, const uint8_t id, + uint8_t offset, struct fru_chassis_info *info) +{ + uint8_t length; + struct ipmi_read_fru_data_req req; + uint8_t *data_ptr, *end, *custom_data_ptr; + int ret = CB_SUCCESS; + + if (!offset) + return CB_ERR; + + offset = offset * OFFSET_LENGTH_MULTIPLIER; + req.fru_device_id = id; + /* Read Chassis Info Area length first. */ + req.fru_offset = offset + 1; + req.count = sizeof(length); + if (ipmi_read_fru(port, &req, &length) != CB_SUCCESS || !length) { + printk(BIOS_ERR, "%s failed, length: %d\n", __func__, length); + return CB_ERR; + } + length = length * OFFSET_LENGTH_MULTIPLIER; + data_ptr = (uint8_t *)malloc(length); + if (!data_ptr) { + printk(BIOS_ERR, "malloc %d bytes for chassis info failed\n", length); + return CB_ERR; + } + end = data_ptr + length; + /* Read Chassis Info Area data. */ + req.fru_offset = offset; + req.count = length; + if (ipmi_read_fru(port, &req, data_ptr) != CB_SUCCESS) { + printk(BIOS_ERR, "%s failed to read fru\n", __func__); + ret = CB_ERR; + goto out; + } + if (checksum(data_ptr, length)) { + printk(BIOS_ERR, "Bad FRU chassis info checksum.\n"); + ret = CB_ERR; + goto out; + } + /* Read chassis type. */ + info->chassis_type = data_ptr[CHASSIS_TYPE_OFFSET]; + + printk(BIOS_DEBUG, "Read chassis part number string.\n"); + length = read_data_string(data_ptr + CHASSIS_TYPE_OFFSET + 1, + &info->chassis_partnumber); + + printk(BIOS_DEBUG, "Read chassis serial number string.\n"); + data_ptr += CHASSIS_TYPE_OFFSET + 1 + length + 1; + length = read_data_string(data_ptr, &info->serial_number); + + printk(BIOS_DEBUG, "Read custom chassis info fields.\n"); + data_ptr += length + 1; + /* Check how many valid custom fields first. */ + info->custom_count = 0; + custom_data_ptr = data_ptr; + while ((data_ptr < end) && ((data_ptr[0] != FRU_END_OF_FIELDS))) { + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) + info->custom_count++; + data_ptr += length + 1; + } + if (!info->custom_count) + goto out; + + info->chassis_custom = malloc(info->custom_count * sizeof(char *)); + if (!info->chassis_custom) { + printk(BIOS_ERR, "%s failed to malloc %ld bytes for " + "chassis custom data array.\n", __func__, + info->custom_count * sizeof(char *)); + ret = CB_ERR; + goto out; + } + + /* Start reading custom chassis data. */ + data_ptr = custom_data_ptr; + int count = 0; + while ((data_ptr < end) && ((data_ptr[0] != FRU_END_OF_FIELDS))) { + length = NUM_DATA_BYTES(data_ptr[0]); + if (length > 0) { + length = read_data_string(data_ptr, info->chassis_custom + count); + count++; + } + data_ptr += length + 1; + } + +out: + free(data_ptr); + return ret; +} + static void read_fru_board_info_area(const int port, const uint8_t id, uint8_t offset, struct fru_board_info *info) { @@ -277,7 +370,8 @@ &fru_info_str->prod_info); read_fru_board_info_area(port, id, fru_common_hdr.board_area_offset, &fru_info_str->board_info); - /* ToDo: Add read_fru_chassis_info_area(). */ + read_fru_chassis_info_area(port, id, fru_common_hdr.chassis_area_offset, + &fru_info_str->chassis_info); } void read_fru_one_area(const int port, const uint8_t id, uint16_t offset, @@ -318,7 +412,11 @@ read_fru_board_info_area(port, id, fru_common_hdr.board_area_offset, &fru_info_str->board_info); break; - /* ToDo: Add case for CHASSIS_INFO_AREA. */ + case CHASSIS_INFO_AREA: + memset(&fru_info_str->chassis_info, 0, sizeof(fru_info_str->chassis_info)); + read_fru_chassis_info_area(port, id, fru_common_hdr.chassis_area_offset, + &fru_info_str->chassis_info); + break; default: printk(BIOS_ERR, "Invalid fru_area: %d\n", fru_area); break; diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index d5d2945..82296a9 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -88,6 +88,7 @@ /* Platform Management FRU Information Storage Definition Spec. */ #define PRODUCT_MAN_TYPE_LEN_OFFSET 3 #define BOARD_MAN_TYPE_LEN_OFFSET 6 +#define CHASSIS_TYPE_OFFSET 2 struct ipmi_fru_common_hdr { uint8_t format_version; @@ -117,9 +118,18 @@ char *part_number; }; +struct fru_chassis_info { + uint8_t chassis_type; + char *chassis_partnumber; + char *serial_number; + char **chassis_custom; + int custom_count; /* Number of custom fields */ +}; + struct fru_info_str { struct fru_product_info prod_info; struct fru_board_info board_info; + struct fru_chassis_info chassis_info; }; enum typecode { -- To view, visit https://review.coreboot.org/c/coreboot/+/40306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb53c20f8eb4b7720bf1fe349e6aaebaa4c37247 Gerrit-Change-Number: 40306 Gerrit-PatchSet: 27 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/ipmi: Added function read_data_string() to make code cleaner
by Johnny Lin (Code Review) 25 Jun '20

25 Jun '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40621 ) Change subject: drivers/ipmi: Added function read_data_string() to make code cleaner ...................................................................... drivers/ipmi: Added function read_data_string() to make code cleaner Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I1da8abaa682af802e5cda65e5021069daf4ee717 --- M src/drivers/ipmi/ipmi_fru.c 1 file changed, 50 insertions(+), 124 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40621/1 diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c index 7fd3d30..a6fb02a 100644 --- a/src/drivers/ipmi/ipmi_fru.c +++ b/src/drivers/ipmi/ipmi_fru.c @@ -92,6 +92,32 @@ return length; } +/* Read data string from data_ptr and store it to string, return the + length of the string or 0 when it's failed. */ +static int read_data_string(uint8_t *data_ptr, char **string) +{ + uint8_t length; + + length = NUM_DATA_BYTES(data_ptr[0]); + if (length == 0) { + printk(BIOS_ERR, "%s:%d - failed due to length is zero\n", __func__, __LINE__); + return 0; + } + + *string = malloc(length + 1); + if (!*string) { + printk(BIOS_ERR, "%s failed to malloc %d bytes for string data.\n", __func__, + length + 1); + return 0; + } + if (!data2str((const uint8_t *)data_ptr, *string, length)) { + printk(BIOS_ERR, "%s:%d - data2str failed\n", __func__, __LINE__); + free(*string); + return 0; + } + + return length; +} static void read_fru_board_info_area(const int port, const uint8_t id, uint8_t offset, struct fru_board_info *info) { @@ -128,61 +154,21 @@ printk(BIOS_ERR, "Bad FRU board info checksum.\n"); goto out; } - /* Read manufacturer string, bit[5:0] is the string length. */ - length = NUM_DATA_BYTES(data_ptr[BOARD_MAN_TYPE_LEN_OFFSET]); - data_ptr += BOARD_MAN_TYPE_LEN_OFFSET; - if (length > 0) { - info->manufacturer = malloc(length + 1); - if (!info->manufacturer) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "manufacturer.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->manufacturer, length)) - free(info->manufacturer); - } + printk(BIOS_DEBUG, "Read board manufacturer string\n"); + length = read_data_string(data_ptr + BOARD_MAN_TYPE_LEN_OFFSET, + &info->manufacturer); - /* Read product name string. */ - data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->product_name = malloc(length+1); - if (!info->product_name) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "product_name.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->product_name, length)) - free(info->product_name); - } + printk(BIOS_DEBUG, "Read board product name string.\n"); + data_ptr += BOARD_MAN_TYPE_LEN_OFFSET + length + 1; + length = read_data_string(data_ptr, &info->product_name); - /* Read serial number string. */ + printk(BIOS_DEBUG, "Read board serial number string.\n"); data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->serial_number = malloc(length + 1); - if (!info->serial_number) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "serial_number.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->serial_number, length)) - free(info->serial_number); - } + length = read_data_string(data_ptr, &info->serial_number); - /* Read part number string. */ + printk(BIOS_DEBUG, "Read board part number string.\n"); data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->part_number = malloc(length + 1); - if (!info->part_number) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "part_number.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->part_number, length)) - free(info->part_number); - } + length = read_data_string(data_ptr, &info->part_number); out: free(data_ptr); @@ -225,89 +211,29 @@ printk(BIOS_ERR, "Bad FRU product info checksum.\n"); goto out; } - /* Read manufacturer string, bit[5:0] is the string length. */ - length = NUM_DATA_BYTES(data_ptr[PRODUCT_MAN_TYPE_LEN_OFFSET]); - data_ptr += PRODUCT_MAN_TYPE_LEN_OFFSET; - if (length > 0) { - info->manufacturer = malloc(length + 1); - if (!info->manufacturer) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "manufacturer.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->manufacturer, length)) - free(info->manufacturer); - } + printk(BIOS_DEBUG, "Read product manufacturer string.\n"); + length = read_data_string(data_ptr + PRODUCT_MAN_TYPE_LEN_OFFSET, + &info->manufacturer); - /* Read product_name string. */ - data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->product_name = malloc(length + 1); - if (!info->product_name) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "product_name.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->product_name, length)) - free(info->product_name); - } + data_ptr += PRODUCT_MAN_TYPE_LEN_OFFSET + length + 1; + printk(BIOS_DEBUG, "Read product_name string.\n"); + length = read_data_string(data_ptr, &info->product_name); - /* Read product part/model number. */ data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->product_partnumber = malloc(length + 1); - if (!info->product_partnumber) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "product_partnumber.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->product_partnumber, length)) - free(info->product_partnumber); - } + printk(BIOS_DEBUG, "Read product part/model number.\n"); + length = read_data_string(data_ptr, &info->product_partnumber); - /* Read product version string. */ data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->product_version = malloc(length + 1); - if (!info->product_version) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "product_version.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->product_version, length)) - free(info->product_version); - } + printk(BIOS_DEBUG, "Read product version string.\n"); + length = read_data_string(data_ptr, &info->product_version); - /* Read serial number string. */ data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->serial_number = malloc(length + 1); - if (!info->serial_number) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "serial_number.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->serial_number, length)) - free(info->serial_number); - } + printk(BIOS_DEBUG, "Read serial number string.\n"); + length = read_data_string(data_ptr, &info->serial_number); - /* Read asset tag string. */ data_ptr += length + 1; - length = NUM_DATA_BYTES(data_ptr[0]); - if (length > 0) { - info->asset_tag = malloc(length + 1); - if (!info->asset_tag) { - printk(BIOS_ERR, "%s failed to malloc %d bytes for " - "asset_tag.\n", __func__, length + 1); - goto out; - } - if (!data2str((const uint8_t *)data_ptr, info->asset_tag, length)) - free(info->asset_tag); - } + printk(BIOS_DEBUG, "Read asset tag string.\n"); + length = read_data_string(data_ptr, &info->asset_tag); out: free(data_ptr); -- To view, visit https://review.coreboot.org/c/coreboot/+/40621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1da8abaa682af802e5cda65e5021069daf4ee717 Gerrit-Change-Number: 40621 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: mb/ocp/deltalake: Enable IPMI KCS
by Morgan Jang (Code Review) 25 Jun '20

25 Jun '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41023 ) Change subject: mb/ocp/deltalake: Enable IPMI KCS ...................................................................... mb/ocp/deltalake: Enable IPMI KCS Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result. TEST=Check if the BMC IPMI reponse data is correct or not. Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/devicetree.cb 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/41023/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index f927174..1a578c5 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -8,6 +8,11 @@ select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 + select IPMI_KCS + +config IPMI_KCS_REGISTER_SPACING + int + default 4 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 27c72af..2044474 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -54,6 +54,8 @@ register "coherency_support" = "0" register "ats_support" = "0" + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + device cpu_cluster 0 on device lapic 0 on end end @@ -86,7 +88,13 @@ device pci 1c.4 on end # PCI bridge: Intel Corporation Device a214 device pci 1c.5 on end # PCI bridge: Intel Corporation Device a215 device pci 1d.0 on end # PCI bridge: Intel Corporation Device a218 - device pci 1f.0 on end # ISA bridge: Intel Corporation Device a245 + device pci 1f.0 on + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + end # ISA bridge: Intel Corporation Device a245 device pci 1f.2 on end # Memory controller: Intel Corporation Device a221 device pci 1f.3 on end # Audio device: Intel Corporation Device a270 device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus -- To view, visit https://review.coreboot.org/c/coreboot/+/41023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Gerrit-Change-Number: 41023 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/xeon_sp/cpx: display platform specific HOBs
by Jonathan Zhang (Code Review) 25 Jun '20

25 Jun '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41348 ) Change subject: soc/intel/xeon_sp/cpx: display platform specific HOBs ...................................................................... soc/intel/xeon_sp/cpx: display platform specific HOBs Add code to support display of platform specific HOBs, and display of UPD. Call the hob display functions at chip_start(), instead of using CONFIG_DISPLAY_HOBS. Otherwise the platform specific HOBs get displayed hundreds of times; in other words, there is a bug in CONFIG_DISPLAY_HOBS support code to be solved. Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c A src/soc/intel/xeon_sp/cpx/hob_display.c A src/soc/intel/xeon_sp/cpx/upd_display.c 4 files changed, 285 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41348/1 diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 8e300e8..87aad3b 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -13,7 +13,11 @@ subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c + ramstage-y += chip.c acpi.c cpu.c soc_util.c +ramstage-y += hob_display.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 8597a2d..f0eb7b1 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -590,6 +590,9 @@ printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); + soc_display_memmap_hob(); + soc_display_iio_universal_data_hob(); + pch_enable_ioapic(NULL); setup_lapic(); p2sb_unhide(); diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c new file mode 100644 index 0000000..424f460 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> +#include <assert.h> +#include <hob_iiouds.h> +#include <hob_memmap.h> +#include <soc/soc_util.h> + +static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; +static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + +struct guid_name_map { + const void *guid; + const char *name; +}; + +static const struct guid_name_map guid_names[] = { + { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" }, + { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" }, +}; + +const char *soc_get_guid_name(const uint8_t *guid) +{ + size_t index; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_guid_compare(guid, guid_names[index].guid)) + return guid_names[index].name; + + return NULL; +} + +void soc_display_hob(const struct hob_header *hob) +{ + const struct hob_resource *res; + + res = fsp_hob_header_to_resource(hob); + assert(res != NULL); + printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n", + res->type, res->attribute_type, res->addr, res->length); + printk(BIOS_DEBUG, "\tOwner GUID: "); + fsp_print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid)); + + if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0) + soc_display_iio_universal_data_hob(); + else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid) == 0) + soc_display_memmap_hob(); + else + hexdump(hob, hob->length); +} + +void soc_display_memmap_hob(void) +{ + size_t hob_size; + const struct SystemMemoryMapHob *hob; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + + hob = (const struct SystemMemoryMapHob *)fsp_find_extension_hob_by_guid( + mem_hob_guid, &hob_size); + assert(hob != NULL); + + printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n"); + printk(BIOS_DEBUG, "hob: %p\n", hob); + printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, " + "highMemSize: 0x%x\n", + hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); + printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x\n", + hob->memSize, hob->memFreq); + + printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries); + for (int e = 0; e < hob->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &hob->Element[e]; + printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n", + e, mem_element->BaseAddress, + mem_element->ElementSize, mem_element->Type); + } +} + +void soc_display_iio_universal_data_hob(void) +{ + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + + hob = (const IIO_UDS *)fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL); + + printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n"); + + printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n"); + printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus); + printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit); + printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit); + + printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n"); + printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase); + printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit); + printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", + hob->PlatformData.PlatGlobalMmiolBase); + printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", + hob->PlatformData.PlatGlobalMmiolLimit); + printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", + hob->PlatformData.PlatGlobalMmiohBase); + printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", + hob->PlatformData.PlatGlobalMmiohLimit); + printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize); + printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize); + printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase); + printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize); + printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm); + printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO); + printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber); + printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity); + printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity); + printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n", + hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo); + printk(BIOS_DEBUG, "\tPci64BitResourceAllocation: 0x%d\n", + hob->PlatformData.Pci64BitResourceAllocation); + + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s); + printk(BIOS_DEBUG, "\tValid: 0x%x\n", + hob->PlatformData.IIO_resource[s].Valid); + printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", + hob->PlatformData.IIO_resource[s].SocketID); + printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].BusBase); + printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].BusLimit); + printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceIoBase); + printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceIoLimit); + printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].IoApicBase); + printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].IoApicLimit); + printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceMem32Base); + printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); + printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", + hob->PlatformData.IIO_resource[s].PciResourceMem64Base); + printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", + hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); + + printk(BIOS_DEBUG, "\t============ Stack Info ================\n"); + for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x); + printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality); + printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); + printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); + printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", + ri->PciResourceIoBase); + printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", + ri->PciResourceIoLimit); + printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); + printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); + printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", + ri->PciResourceMem32Base); + printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", + ri->PciResourceMem32Limit); + printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n", + ri->PciResourceMem64Base); + printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n", + ri->PciResourceMem64Limit); + printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress); + } + + printk(BIOS_DEBUG, "\t============ PcieInfo ================\n"); + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[s]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", + p, iio_resource.PcieInfo.PortInfo[p].Device, + iio_resource.PcieInfo.PortInfo[p].Function); + } + } +} diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c new file mode 100644 index 0000000..f3f78fc --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/upd_display.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> + +#define DUMP_UPD(old, new, field) \ + fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field) + +/* Display the UPD parameters for MemoryInit */ +void soc_display_fspm_upd_params( + const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) +{ + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + printk(BIOS_DEBUG, "UPD values for MemoryInit:\n"); + + DUMP_UPD(old, new, DebugPrintLevel); + + hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); +} + +/* Display the UPD parameters for SiliconInit */ +void soc_display_fsps_upd_params( + const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd) +{ + const FSPS_CONFIG *new; + const FSPS_CONFIG *old; + + old = &fsps_old_upd->FspsConfig; + new = &fsps_new_upd->FspsConfig; + + printk(BIOS_DEBUG, "UPD values for SiliconInit:\n"); + + DUMP_UPD(old, new, BifurcationPcie0); + DUMP_UPD(old, new, BifurcationPcie1); + DUMP_UPD(old, new, ActiveCoreCount); + DUMP_UPD(old, new, CpuMicrocodePatchBase); + DUMP_UPD(old, new, CpuMicrocodePatchSize); + DUMP_UPD(old, new, EnablePcie0); + DUMP_UPD(old, new, EnablePcie1); + DUMP_UPD(old, new, EnableEmmc); + DUMP_UPD(old, new, EnableGbE); + DUMP_UPD(old, new, FiaMuxConfigRequestPtr); + DUMP_UPD(old, new, PcieRootPort0DeEmphasis); + DUMP_UPD(old, new, PcieRootPort1DeEmphasis); + DUMP_UPD(old, new, PcieRootPort2DeEmphasis); + DUMP_UPD(old, new, PcieRootPort3DeEmphasis); + DUMP_UPD(old, new, PcieRootPort4DeEmphasis); + DUMP_UPD(old, new, PcieRootPort5DeEmphasis); + DUMP_UPD(old, new, PcieRootPort6DeEmphasis); + DUMP_UPD(old, new, PcieRootPort7DeEmphasis); + DUMP_UPD(old, new, EMMCDLLConfigPtr); + + hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 Gerrit-Change-Number: 41348 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

7 18

Change in coreboot[master]: mb/google/octopus/variants/bobba: fix disable_xhci_lfps_pm by sku
by Sheng-Liang Pan (Code Review) 25 Jun '20

25 Jun '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42564 ) Change subject: mb/google/octopus/variants/bobba: fix disable_xhci_lfps_pm by sku ...................................................................... mb/google/octopus/variants/bobba: fix disable_xhci_lfps_pm by sku due to overridetree.cb set disable_xhci_lfps_pm = 0, need correct condition expression to let fuction work. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I53621d7674a531adfa40e8703cb2cd01c50376b8 --- M src/mainboard/google/octopus/variants/bobba/variant.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/42564/1 diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index f011b65..97c77a9 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -82,7 +82,7 @@ cfg = (struct soc_intel_apollolake_config *)dev->chip_info; - if (cfg != NULL && cfg->disable_xhci_lfps_pm) { + if (cfg != NULL && (cfg->disable_xhci_lfps_pm != 1)) { switch (google_chromeec_get_board_sku()) { case 37: case 38: -- To view, visit https://review.coreboot.org/c/coreboot/+/42564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53621d7674a531adfa40e8703cb2cd01c50376b8 Gerrit-Change-Number: 42564 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2020