coreboot-gerrit May 2020

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Change in coreboot[master]: abuild: Fix board variant handling
by Keith Hui (Code Review) 17 Aug '23

17 Aug '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41918 ) Change subject: abuild: Fix board variant handling ...................................................................... abuild: Fix board variant handling Problem: Me: $ util/abuild/abuild -t asus/p2b -b p2b-ls abuild: No such target: asus/p2b, variant: p2b-ls Cause: We identify boards and variants using path names in tree, so I type in the test command above. abuild identifies all board variants the Kconfig way, in all caps and all underscores. Result: Expectation gap and abuild can't find anything where we expect it to. All variants with a hyphen in their names are affected. Fix: Add a substitution to replace hyphens with underscores. Test: I get my abuild with the command above, even a variant-specific test config works. Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41918/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index b6a6bfe..ca8a0cf 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -165,7 +165,7 @@ local targets local VARIANT_UC - VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]') + VARIANT_UC=$(echo "${variant}" | tr '[:lower:]' '[:upper:]' | tr '-' '_') targets=$(get_mainboards "$1") if [ -n "$targets" ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/41918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a Gerrit-Change-Number: 41918 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/asus/p2b: Add ACPI support for p3b-f
by Keith Hui (Code Review) 14 Aug '23

14 Aug '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41098 ) Change subject: mb/asus/p2b: Add ACPI support for p3b-f ...................................................................... mb/asus/p2b: Add ACPI support for p3b-f Finally! Power button works to turn board on and off. ACPI hooks to manipulate power and message LEDs work. Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/dsdt.asl A src/mainboard/asus/p2b/suspend.asl A src/mainboard/asus/p2b/variants/p3b-f/suspend.asl 4 files changed, 393 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41098/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 1ad25e1..45018d6 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -29,7 +29,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F - select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS config MAX_CPUS diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 88be9ba..623b575 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -53,6 +53,7 @@ { Offset (0x03), TO12, 1, /* Device trap 12 */ +#if !CONFIG(BOARD_ASUS_P3B_F) Offset (0x08), FANM, 1, /* GPO0, meant for fan */ Offset (0x09), @@ -61,33 +62,25 @@ , 2, , 16, MSG0, 1 /* GPO30, message LED */ +#endif } - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) + OperationRegion (ECOS, SystemIO, 0x72, 0x02) + Field (ECOS, ByteAcc, NoLock, Preserve) { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) + CIDX, 8, + CDAT, 8 } - Method (\_WAK, 1, NotSerialized) + IndexField (CIDX, CDAT, ByteAcc, NoLock, Preserve) { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) + Offset (0x58), + RTCS, 8, + Offset (0x5F), + SUS3, 1, + , 3, + SLST, 4 } - /* Root of the bus hierarchy */ Scope (\_SB) { @@ -169,19 +162,9 @@ } } - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } +#if CONFIG(BOARD_ASUS_P3B_F) +#include "variants/p3b-f/suspend.asl" +#else +#include "suspend.asl" +#endif } diff --git a/src/mainboard/asus/p2b/suspend.asl b/src/mainboard/asus/p2b/suspend.asl new file mode 100644 index 0000000..5d2b540 --- /dev/null +++ b/src/mainboard/asus/p2b/suspend.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* ASUS P2B family board DSDT declarations (at top level) that does not apply to P3B-F */ + +/** + * ACPI message indicator. + * + * @param Arg0 Number of waiting messages + */ +Scope (\_SI) +{ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (One, MSG0) + } + Else + { + Store (Zero, MSG0) + } + } +} + +/** + * Prepare To Sleep. + * + * @param Arg0 Target ACPI S-state + */ +Method (\_PTS, 1, NotSerialized) +{ + /*SLST = Arg0*/ + /* Disable fan, blink power LED. S5 will turn them off too */ + If (Arg0 != 5) + { + FANM = 0 + PLED = 0 + } + + /* Arms SMI for device 12 */ + Store (One, TO12) + /* Put out a POST code */ + P80 = 0xF0 | Arg0 +} + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ +Method (\_WAK, 1, NotSerialized) +{ + /* Re-enable fan, stop power led blinking */ + FANM = 1 + PLED = 1 + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) +} + diff --git a/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl new file mode 100644 index 0000000..a84c700 --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/suspend.asl @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include "southbridge/intel/i82371eb/i82371eb.h" + +/* ASUS P3B-F board specific (top level) DSDT declarations */ + +Name (PRW1, Package (0x04) +{ + Package (0x02) {0x09, 0x01}, + Package (0x02) {0x08, 0x01}, + Package (0x02) {0x0A, 0x01}, + Package (0x02) {0x0B, 0x01} +}) + +Name (PRW3, Package (0x04) +{ + Package (0x02) { 0x09, 0x03 }, + Package (0x02) { 0x08, 0x03 }, + Package (0x02) { 0x0A, 0x03 }, + Package (0x02) { 0x0B, 0x04 } +}) + +Name (PRWT, Package (0x04) +{ + 0x09, + 0x08, + 0x0A, + 0x0B +}) + +/* SPRW(n) = (SUS3==0) ? PRW1[n] : PRW3[n] */ +Method (SPRW, 1, NotSerialized) +{ + Store (Match (PRWT, MEQ, Arg0, MTR, 0x00, 0x00), Local0) + If (LEqual (SUS3, Zero)) + { + Return (DerefOf (Index (PRW1, Local0))) + } + Else + { + Return (DerefOf (Index (PRW3, Local0))) + } +} + +/* + * SMBus driver functions + * + * These functions communicate with the AS99127F ASIC on the P3B-F to handle hardware + * sequencing required around S3 suspend and resume. This chip is undocumented except it has + * W83781D-compatible hardware monitoring features, and seems to be responsible for hiding the + * flashchip from internal programming via flashrom. + * + * Note: The SMBus host controller interface is located in the southbridge. + */ + /* The SMBus controller hardware interface. Only byte accesses covered. */ + OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7) + Field (SM00, ByteAcc, NoLock, Preserve) + { + HSTS, 8, + Offset (0x02), + CTLR, 8, + CMDR, 8, + ADDR, 8, + DAT0, 8, + DAT1, 8 + } + /* Wait for SMBus activity to complete, error or not */ + Method (SWFS, 0, NotSerialized) + { + And (HSTS, 0x06, Local0) + While (Local0 == 0) + { + Stall (1) + And (HSTS, 0x06, Local0) + } + } + + /** + * Writes a byte to a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @param Arg2 Data + */ + Method (WBYT, 3, NotSerialized) + { + Store (Arg0, ADDR) + Store (Arg1, CMDR) + Store (Arg2, DAT0) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + SWFS () + } + + /** + * Reads a byte from a SMBus device. + * + * @param Arg0 SMBus device ID << 1 + * @param Arg1 Command (register index in our case) + * @return Data read + */ + Method (RBYT, 2, NotSerialized) + { + Or (Arg0, 0x01, ADDR) /* Set bit 0, this will be a read */ + Store (Arg1, CMDR) + Store (0xFF, HSTS) + Store (0x48, CTLR) /* Start a byte data R/W access */ + + /* If interrupted without success, restart and try again */ + And (HSTS, 0x02, Local0) + While (LEqual (Local0, Zero)) + { + Store (0xFF, HSTS) + Store (0x48, CTLR) + SWFS () + And (HSTS, 0x02, Local0) + } + + Return (DAT0) /* \DAT0 */ + } + + Method (SGOH, 2, NotSerialized) + { + /* SMBus address 0x48 */ + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Or (Local1, Arg1, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (SGOL, 2, NotSerialized) + { + Store (0x90, Local0) + Store (RBYT (Local0, Arg0), Local1) + Not (Arg1, Local2) + And (Local1, Local2, Local1) + WBYT (Local0, Arg0, Local1) + } + + Method (FANC, 1, NotSerialized) + { + /* SMBus address 0x2d */ + WBYT (0x5A, 0x59, Arg0) + } + + Method (FANP, 1, NotSerialized) + { + WBYT (0x5A, 0x5A, Arg0) + } + + Method (EN18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + And (Local1, 0xDF, Local1) + WBYT (Local0, 0x5F, Local1) + } + + Method (DS18, 0, NotSerialized) + { + Store (0x5A, Local0) + Store (RBYT (Local0, 0x5F), Local1) + Or (Local1, 0x20, Local1) + WBYT (Local0, 0x5F, Local1) + } + +/** + * Prepare To Sleep, + * + * @param Arg0 Target ACPI S-state + */ + Method (\_PTS, 1, NotSerialized) + { + SLST = Arg0 + If (Arg0 == 0x01) + { + /* Disable BX.PMCR[CRst_En] */ + Store (\_SB.PCI0.NB.PMCR, Local0) + And (Local0, 0xFE, \_SB.PCI0.NB.PMCR) + + /* Isolate CPU_STP# and SUS_STAT1# signals at GENCFG register */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + Or (Local0, 0x24, Local1) + Store (Local1, \_SB.PCI0.PX40.FXS1) + + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + /* In SIO Dev A CR E4 = xxxx01xx (these bits are reserved per datasheet?) */ + And (\_SB.PCI0.KBWK, 0xF7, Local0) + Or (Local0, 0x04, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + } + + If (Arg0 == 0x03) + { + SGOH (0x83, 0x04) + SGOL (0x80, 0x04) + SGOH (0x80, 0x04) + SGOH (0x83, 0x01) + EN18 () + } + + /* Arms SMI for device 12 */ + TO12 = 1 + /* Put out a POST code */ + P80 = 0xF0 | Arg0 + } + +/** + * System wake. + * + * Returns a 2-DWORD package of: + * Status: Wake status (0 = success, 1 = failure (power), 2 = failure (thermal)) + * PSS: Actual S-state power supply entered if not 0 + * + * @param Arg0 Target ACPI S-state + * @return See description + */ + Method (\_WAK, 1, NotSerialized) // _WAK: Wake + { + DS18 () + Store (Zero, TO12) + /* Restore CPU_STP# and SUS_STAT1# signals */ + Store (\_SB.PCI0.PX40.FXS1, Local0) + And (Local0, 0xDB, \_SB.PCI0.PX40.FXS1) + SGOL (0x83, 0x01) + \_SB.PCI0.ENTER_CONFIG_MODE (0x0A) + And (\_SB.PCI0.MSWK, 0xFD, Local1) + Store (Local1, \_SB.PCI0.MSWK) + /* In SIO Dev A CR E4 = xxxx00xx */ + And (\_SB.PCI0.KBWK, 0xF3, Local0) + Store (Local0, \_SB.PCI0.KBWK) + \_SB.PCI0.EXIT_CONFIG_MODE () + /* Put out a POST code */ + P80 = 0xFF + Return(Package(0x02){0x00, 0x00}) + } + + Scope (\_GPE) + { + Method (_L0A, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0.SER2, 0x02) // Device Wake + Notify (\_SB.PCI0.SER3, 0x02) // Device Wake + } + + Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE + { + Notify (\_SB.PCI0, 0x02) // Device Wake + } + } + +Scope (\_SI) +{ + /** + * ACPI message indicator + * + * @param Arg0 Number of waiting messages + */ + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + SGOL (0x81, 0x02) + SGOH (0x81, 0x01) + SGOL (0x81, 0x01) + } + Else + { + SGOH (0x81, 0x02) + SGOL (0x81, 0x02) + } + } + + + /** + * System Status. OS calls to set system status indicator. + * Arg0: + * 0 = Indicator off + * 1 = Working + * 2 = Waking + * 3 = Sleeping: States S1, S2, S3 + * 4 = Sleeping with context saved to non-volatile storage. + * + * @param Arg0 System status indicator + */ + Method (_SST, 1, NotSerialized) // _SST: System Status + { + If (LEqual (Arg0, 0x00)) + { + SGOH (0x80, 0x40) + } + ElseIf (LEqual (Arg0, 0x03)) + { + SGOL (0x80, 0x40) + SGOL (0x80, 0x80) + FANC (0x81) + FANP (0x81) + } + Else + { + SGOL (0x80, 0x40) + SGOH (0x80, 0x80) + FANC (0x8F) + FANP (0x8F) + } + } +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/41098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3736532df0efde4399fb36eb19df8db511fac6ea Gerrit-Change-Number: 41098 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 23

Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T
by Gaggery Tsai (Code Review) 07 Aug '23

07 Aug '23

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38252 ) Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T ...................................................................... soc/intel/common/block/cpu/car: Enable caching before FSP-T This patch is required for Boot Guard enabled platform. Enable caching before entering FSP-T. TEST=Stitch boot guard ACM with signed KM and BPM && Enable FSP-T and boot all the way to the OS && Read MSR 0x13a and esnure boot guard verified boot and measured boot are enabled. Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38252/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 091fc4a..fd22903 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -35,6 +35,12 @@ cache_as_ram: post_code(0x21) + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + /* find fsp in cbfs */ lea fsp_name, %esi mov $1f, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/38252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24 Gerrit-Change-Number: 38252 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

12 29

Change in ...coreboot[master]: mb/*/romstage: Drop defines already set by raminit code
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32070 Change subject: mb/*/romstage: Drop defines already set by raminit code ...................................................................... mb/*/romstage: Drop defines already set by raminit code Drop defines that are set by raminit code. Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/roda/rv11/variants/rw11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c 19 files changed, 0 insertions(+), 265 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32070/1 diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a917722..68ed658 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -74,20 +74,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */ diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..6417f0d 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -71,20 +71,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, // 0 = leave channel enabled diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index d34b1e4..cbd9f3d 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -132,20 +132,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66a503d0..6617dc4 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -127,20 +127,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .ddr3lv_support = 1, diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 76a4b4b..d76d814 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -101,20 +101,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 25f8d27..2244119 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -109,20 +109,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index b95c6e1..35345d0 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -106,20 +106,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index e47edc7..a5de6c0 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -124,20 +124,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 3125efe..5a8c972 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -111,20 +111,7 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 7539dd7..6e32145 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -137,20 +137,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 24ec912..2043cf6 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -29,20 +29,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9a9fc24..8cd7ec2 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -94,20 +94,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index f778f96..e0f8954 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -80,20 +80,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index a5b0c81..d398d81 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -50,20 +50,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c index 685e942..df679f1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c @@ -37,20 +37,6 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c index 97d9d2b..56ac32c 100644 --- a/src/mainboard/roda/rv11/variants/rw11/romstage.c +++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c @@ -66,20 +66,6 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1080689..29fe08b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -156,20 +156,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, .ec_present = 1, diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a8e28d6..510efbe 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -144,20 +144,6 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 84ad047..702e8bb 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -66,20 +66,6 @@ { struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 1, /* desktop/server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, .ec_present = 0, .ddr_refresh_2x = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/32070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica844a70b50486b4db3744cb123b3e4b8d5bedb0 Gerrit-Change-Number: 32070 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36779 ) Change subject: [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support ...................................................................... [TESTME]x4x/i82801jx/socket_LGA775: Add x86_64 support Use correct datasize to compile on x86_64. Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/walkcbfs.S M src/cpu/intel/model_1067x/Kconfig M src/cpu/intel/model_6fx/Kconfig M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_handler.c M src/drivers/net/atl1e.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/x4x.h M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/sata.c 18 files changed, 63 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36779/1 diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded6558..01382e4 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -33,6 +33,7 @@ .section .text .global walkcbfs_asm +.code32 /* * input %esi: filename diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 564a428..93604d6 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 + select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index cfd3e7c..8c86226 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 9a5e2a1..ae67337 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,9 +1,14 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b5..84c6863 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,8 +1,12 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..8f60d2c 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -3,6 +3,10 @@ if CPU_INTEL_SOCKET_LGA775 +config ARCH_EXP_X86_64 + bool "Enable experimental 64bit support" + default n + config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_MODEL_6FX diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de..ea70453 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -122,7 +122,7 @@ /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -348,16 +348,16 @@ setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on abiility to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index bd4d48c..82ad37d 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -107,7 +107,7 @@ /* This function assumes all save states start at top of default * SMRAM size space and are staggered down by save state size. */ - base = (void *)smm_runtime->smbase; + base = (void *)(uintptr_t)smm_runtime->smbase; base += SMM_DEFAULT_SIZE; base -= (cpu + 1) * smm_runtime->save_state_size; diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c index 51470b0..d68ea0d 100644 --- a/src/drivers/net/atl1e.c +++ b/src/drivers/net/atl1e.c @@ -86,7 +86,7 @@ } } -static void program_mac_address(u32 mem_base) +static void program_mac_address(uintptr_t mem_base) { u8 macstrbuf[MACLEN] = { 0 }; /* Default MAC Address of 90:e6:ba:24:f9:d2 */ @@ -110,7 +110,7 @@ printk(BIOS_DEBUG, "done\n"); } -static int atl1e_eeprom_exist(u32 mem_base) +static int atl1e_eeprom_exist(uintptr_t mem_base) { u32 value = read32((void *)mem_base + REG_SPI_FLASH_CTRL); if (value & SPI_FLASH_CTRL_EN_VPD) { diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ed372b5..080262e 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -178,7 +178,7 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel) { - u32 address; + uintptr_t address; int rank, lane; u8 count, count1; u8 data[8]; @@ -374,7 +374,7 @@ { int i, rank, lane; volatile u8 data[8]; - u32 address; + uintptr_t address; u8 bytelane_error = 0; FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) { @@ -453,7 +453,8 @@ int do_read_training(struct sysinfo *s) { int loop, channel, i, lane, rank; - u32 address, content; + uintptr_t address; + u32 content; u8 dqs_lower[TOTAL_BYTELANES]; u8 dqs_upper[TOTAL_BYTELANES]; struct rt_dqs_setting dqs_setting[TOTAL_BYTELANES]; @@ -643,7 +644,7 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, u8 high_found[8]) { - u32 address = test_address(channel, rank); + uintptr_t address = test_address(channel, rank); int samples, lane; memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 39f24d3..592a2e0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -89,7 +89,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..31e94f4 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1316,7 +1316,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { - u32 addr = test_address(ch, r); + uintptr_t addr = test_address(ch, r); u8 data8 = cmd; u32 data32; @@ -2160,7 +2160,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32((u32 *)((uintptr_t)test_address(ch, r) | 0x800000 | (bank << 12))); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 36a6ebd..c41bb07 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -39,7 +39,7 @@ asm volatile("mfence":::); } -static u8 sampledqs(u32 addr, u8 lane, u8 channel) +static u8 sampledqs(uintptr_t addr, u8 lane, u8 channel) { u32 sample_offset = 0x400 * channel + 0x561 + lane * 4; diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76d94c6..4809ee7 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -84,9 +84,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a84a0df..a9c8863 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -275,7 +275,7 @@ { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ + uintptr_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 0628c43..2273e6c 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -276,10 +276,8 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a395069..412e97f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -669,7 +669,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..70c5e69 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -37,7 +37,7 @@ u32 reg32; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/36779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4851932975e99e06ba5650c2359a835b46d702d Gerrit-Change-Number: 36779 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/common/block: Update microcode for each core
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35739 ) Change subject: soc/intel/common/block: Update microcode for each core ...................................................................... soc/intel/common/block: Update microcode for each core On Hyper-Threading enabled platform update the microcde only once for each core, not for each thread. Follow Intel Software Developer Guidelines as the added comment also states. Change-Id: I72804753e567a137a5648ca6950009fed332531b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35739/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 2c5061f..e7689cf 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -26,6 +26,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <cpu/intel/common/common.h> #include <soc/cpu.h> static const void *microcode_patch; @@ -44,7 +45,24 @@ static void init_one_cpu(struct device *dev) { soc_core_init(dev); - intel_microcode_load_unlocked(microcode_patch); + + /* + * Update just on the first CPU in the core. Other siblings + * get the update automatically according to Document: 253668-060US + * Intel SDM Chapter 9.11.6.3 + * "Update in a System Supporting Intel Hyper-Threading Technology" + * Intel Hyper-Threading Technology has implications on the loading of the + * microcode update. The update must be loaded for each core in a physical + * processor. Thus, for a processor supporting Intel Hyper-Threading + * Technology, only one logical processor per core is required to load the + * microcode update. Each individual logical processor can independently + * load the update. However, MP initialization must provide some mechanism + * (e.g. a software semaphore) to force serialization of microcode update + * loads and to prevent simultaneous load attempts to the same core. + */ + if (!intel_ht_sibling()) { + intel_microcode_load_unlocked(microcode_patch); + } } static struct device_operations cpu_dev_ops = { @@ -141,6 +159,7 @@ if (CONFIG(USE_INTEL_FSP_MP_INIT)) return; + /* Update microcode on BSP */ microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); -- To view, visit https://review.coreboot.org/c/coreboot/+/35739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72804753e567a137a5648ca6950009fed332531b Gerrit-Change-Number: 35739 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

9 52

Change in coreboot[master]: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig
by Christoph Pomaska (Code Review) 07 Aug '23

07 Aug '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34905 ) Change subject: mb/supermicro/x10slm-f: Add new superio support to board's Kconfig ...................................................................... mb/supermicro/x10slm-f: Add new superio support to board's Kconfig Since the superio support code didnt exist when the board was ported, the Kconfig was not modified yet to add support for the BMC-chip. This commit fixes the missing Kconfig entry. Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- M src/mainboard/supermicro/x10slm-f/Kconfig 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34905/1 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm-f/Kconfig index 3945c09..6effff2 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm-f/Kconfig @@ -20,15 +20,16 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select CPU_INTEL_HASWELL - select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select SOUTHBRIDGE_INTEL_LYNXPOINT select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_LYNXPOINT - select SUPERIO_NUVOTON_NCT6776 + select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. + select SUPERIO_ASPEED_AST2400 # The board's BMC + select SUPERIO_NUVOTON_NCT6776 # the board's superio select SUPERIO_NUVOTON_NCT6776_COM_A config CBFS_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/34905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f89c2ddcc00327e01d0a83fc13cfa862e6abd70 Gerrit-Change-Number: 34905 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

9 45

Change in coreboot[master]: soc/intel/common: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 07 Aug '23

07 Aug '23

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 ) Change subject: soc/intel/common: Add romstage common stage file ...................................................................... soc/intel/common: Add romstage common stage file This patch will ensures all intel soc is using common stage files to make coreboot design flow align across all socs. CPU, SA, PCH, MCH programming sequence might be different between socs but the function call should route from same location across all soc. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c --- M src/cpu/intel/car/romstage.c A src/soc/intel/common/basecode/include/intelbasecode/romstage.h A src/soc/intel/common/basecode/romstage/Makefile.inc A src/soc/intel/common/basecode/romstage/romstage.c 4 files changed, 162 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 1f8eb9a..55d3c9d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -52,9 +52,6 @@ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; - if (CONFIG(VBOOT_EARLY_EC_SYNC)) - vboot_sync_ec(); - mainboard_romstage_entry(); /* Check the stack. */ @@ -64,9 +61,6 @@ printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); } - if (CONFIG(SMM_TSEG)) - smm_list_regions(); - prepare_and_run_postcar(&early_mtrrs); /* We do not return here. */ } diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h new file mode 100644 index 0000000..0cebbbf --- /dev/null +++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H +#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +struct romstage_ops { + void (*soc_early_init)(void); + void (*soc_init)(void); + void (*pch_early_init)(void); + void (*pch_init)(void); + void (*cpu_early_init)(void); + void (*cpu_init)(void); + bool (*is_s3wake)(void); + void (*soc_mem_init_params)(FSP_M_CONFIG *mupd); +}; + +/* SoC Override function */ +struct romstage_ops *soc_get_ops(void); + +#endif diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc new file mode 100644 index 0000000..29763fb --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/Makefile.inc @@ -0,0 +1 @@ +romstage-y += romstage.c diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c new file mode 100644 index 0000000..55c4ab5 --- /dev/null +++ b/src/soc/intel/common/basecode/romstage/romstage.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <romstage_common.h> +#include <cpu/x86/pae.h> +#include <intelbasecode/romstage.h> +#include <intelblocks/systemagent.h> +#include <soc/iomap.h> +#include <soc/romstage.h> + +static const struct romstage_ops s_romstage_ops; + +__weak struct romstage_ops *soc_get_ops(void) +{ + return (struct romstage_ops *)&s_romstage_ops; +} + +void romstage_early_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_early_init(); + rs_ops->pch_early_init(); + rs_ops->cpu_early_init(); +} + +void romstage_init(void) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + rs_ops->soc_init(); + rs_ops->pch_init(); + rs_ops->cpu_init(); +} + +void romstage_cmn_soc_early_init(void) +{ + systemagent_early_init(); + heci_init(HECI1_BASE_ADDRESS); +} + +void romstage_cmn_soc_init(void) +{ +} + +void romstage_cmn_pch_early_init(void) +{ +} + +void romstage_cmn_cpu_early_init(void) +{ +} + +void romstage_cmn_pch_init(void) +{ +} + +void romstage_cmn_cpu_init(void) +{ +} + +bool romstage_cmn_is_s3wake(void) +{ + struct chipset_power_state *ps = pmc_get_power_state(); + return pmc_fill_power_state(ps) == ACPI_S3; +} + +void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg) +{ +} + +static const struct romstage_ops s_romstage_ops = { + &romstage_cmn_soc_early_init, + &romstage_cmn_soc_init, + &romstage_cmn_pch_early_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_early_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_mb_mem_init_param, + &romstage_cmn_soc_mem_init_param +}; + +/* + Main romstage function +*/ +asmlinkage void mainboard_romstage_entry(void) +{ + if (CONFIG(VBOOT_EARLY_EC_SYNC)) + vboot_sync_ec(rs_ops->fill_power_state()); + + romstage_early_init(); + romstage_init(); + fsp_memory_init(rs_ops->is_s3wake()); + + if (CONFIG(SMM_TSEG)) + smm_list_regions(); +} + +/* + Callback function for FSP memory initialization +*/ +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + struct romstage_ops *rs_ops = soc_get_ops(); + + FSP_M_CONFIG *m_cfg; + rs_ops->soc_mem_init_params(m_cfg); + mainboard_memory_init_params(m_cfg); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/37628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c Gerrit-Change-Number: 37628 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: [TESTME]lenovo/x220: Attempt to fix broken DRAM init
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39043 ) Change subject: [TESTME]lenovo/x220: Attempt to fix broken DRAM init ...................................................................... [TESTME]lenovo/x220: Attempt to fix broken DRAM init Enable power on WWAN as it has SMBUS connected. Might resolv an issue where DRAM init fails as no EEPROM is found on the bus. Untested. Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/ec/lenovo/h8/Makefile.inc M src/mainboard/lenovo/x220/early_init.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39043/1 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 51c11be..9c8687a 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -18,6 +18,8 @@ ramstage-y += panic.c endif +romstage += wwan.c + ramstage-y += h8.c ramstage-y += bluetooth.c ramstage-y += wwan.c diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 3429c1b..ae16f0c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -24,6 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <ec/lenovo/h8/h8.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -74,6 +75,18 @@ *pei_data = pei_data_template; } +void mainboard_early_init(int s3_resume) +{ + /* + * The WWAN slot has SMBUS connected. Turn on power to make sure + * SMBUS is usable and DRAM init will succeed. + * ramstage will turn it off, in case it's not needed. + * TODO: Does GPIO42 (SMB_3B_EN) help here? + */ + if (h8_has_wwan()) + h8_wwan_enable(true); +} + void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd (&spd[0], 0x50, id_only); -- To view, visit https://review.coreboot.org/c/coreboot/+/39043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Gerrit-Change-Number: 39043 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: sb/intel/lynxpoint: Setup gpio in bootblock
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36712 ) Change subject: sb/intel/lynxpoint: Setup gpio in bootblock ...................................................................... sb/intel/lynxpoint: Setup gpio in bootblock GPIO setup is needed for verstage. verstage can also still happen after romstage so keep the GPIO init there too. Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/h81m-hds/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/mainboard/supermicro/x10slm-f/Makefile.inc M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36712/1 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index de18bc5..3fc7ac7 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 7535350..0ecb31d 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -23,5 +23,7 @@ romstage-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index f80dcab..e35f93e 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -23,6 +23,8 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 91a7963..8f12999 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index 301070b..0b4f367 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -15,4 +15,5 @@ ## romstage-y += gpio.c +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5ca7daf..433a310 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..bacaf74 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -50,6 +50,7 @@ romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +bootblock-y += lp_gpio.c romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e6925..abcb35b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "pch.h" +#include "lp_gpio.h" /* * Enable Prefetching and Caching. @@ -33,14 +34,6 @@ pci_write_config8(dev, 0xdc, reg8); } - -static void map_rcba(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, @@ -72,7 +65,7 @@ void bootblock_early_southbridge_init(void) { - map_rcba(); + pch_enable_bars(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); @@ -83,3 +76,12 @@ pch_enable_lpc(); mainboard_config_superio(); } + +void bootblock_southbridge_init(void) +{ +#if CONFIG(INTEL_LYNXPOINT_LP) + setup_pch_lp_gpios(mainboard_gpio_map); +#else + setup_pch_gpios(mainboard_gpio_map); +#endif +} diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index b49d3cf..9cf021e 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -45,7 +45,7 @@ return id == PCH_TYPE_LPT_LP; } -static void pch_enable_bars(void) +void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8802be1..561c5b7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -184,6 +184,7 @@ int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); +void pch_enable_bars(void); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Gerrit-Change-Number: 36712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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