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Aug. 7, 2023
Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39172 )
Change subject: screen fix
......................................................................
screen fix
Change-Id: Ie68e77af77ccec83c29d3329ee9997b950b351f6
---
A grub.cfg
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Kconfig
A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
A src/mainboard/dell/dell_system_vostro_3360/board_info.txt
A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
A src/mainboard/dell/dell_system_vostro_3360/early_init.c
A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
A src/mainboard/dell/dell_system_vostro_3360/gpio.c
A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
A src/mainboard/dell/dell_system_vostro_3360/mainboard.c
M util/superiotool/ite.c
A util/superiotool/output
20 files changed, 1,275 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/39172/1
diff --git a/grub.cfg b/grub.cfg
new file mode 100644
index 0000000..0e941ec
--- /dev/null
+++ b/grub.cfg
@@ -0,0 +1 @@
+configfile (ahci0,3)/boot/grub/grub.cfg
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100755
index 0000000..298c62b
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_DELL
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/dell/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/dell/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Dell Inc."
+
+endif # VENDOR_DELL
diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name
new file mode 100755
index 0000000..3d2fefd
--- /dev/null
+++ b/src/mainboard/dell/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_DELL
+ bool "Dell Inc."
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig
new file mode 100755
index 0000000..8861897
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig
@@ -0,0 +1,43 @@
+if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select GFX_GMA_INTERNAL_IS_LVDS
+ select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ string
+ default dell/dell_system_vostro_3360
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Dell System Vostro 3360"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0156.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0156"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
new file mode 100755
index 0000000..8925217
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360
+ bool "Dell System Vostro 3360"
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
new file mode 100755
index 0000000..18391d8
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
new file mode 100755
index 0000000..afb8abb
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
@@ -0,0 +1,8 @@
+Method(_WAK, 1)
+{
+ Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
new file mode 100755
index 0000000..cfc2061
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt
new file mode 100755
index 0000000..be6bff8
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt
@@ -0,0 +1,4 @@
+Category: desktop
+ROM protocol: SPI
+Flashrom support: n
+FIXME: check category, , put ROM package, ROM socketed, Release year
diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
new file mode 100755
index 0000000..d234325
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
@@ -0,0 +1,111 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "3000"
+ register "gpu_panel_power_backlight_on_delay" = "1700"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "300"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x00040069"
+ register "gen2_dec" = "0x00040911"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x000c06a1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x1028 0x055c
+ end
+ device pci 16.0 off # Management Engine Interface 1
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.1 off # PCIe Port #2
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1028 0x055c
+ end
+ device pci 01.0 off # PEG
+ end
+ device pci 02.0 on # iGPU
+ subsystemid 0x1028 0x055c
+ end
+ end
+end
diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
new file mode 100755
index 0000000..b00a7ff
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
@@ -0,0 +1,29 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c
new file mode 100755
index 0000000..6dbf226
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 0, 1, 3 },
+ { 0, 1, 3 },
+ { 1, 1, 4 },
+ { 0, 1, 4 },
+ { 1, 1, 5 },
+ { 0, 1, 5 },
+ { 1, 1, 6 },
+ { 0, 1, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+}
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
new file mode 100755
index 0000000..d7afe73
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
@@ -0,0 +1,34 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ Internal);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c
new file mode 100755
index 0000000..d7db210
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_GPIO,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_GPIO,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_INPUT,
+ .gpio62 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
new file mode 100755
index 0000000..c55bf3c
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134213, /* Codec Vendor / Device ID: Cirrus */
+ 0x1028055c, /* Subsystem ID */
+ 6, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x0, 0x1028055c),
+ AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f),
+ AZALIA_PIN_CFG(0x0, 0x05, 0x90170010),
+ AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e),
+ AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0),
+ AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c
new file mode 100755
index 0000000..e5cfebf
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c
@@ -0,0 +1,15 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c
index 81ab024..2f2cb57 100644
--- a/util/superiotool/ite.c
+++ b/util/superiotool/ite.c
@@ -274,6 +274,60 @@
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}},
{EOT}}},
+ {0x8518, "IT8518", {
+ {NOLDN, "Chip ID",
+ {0x20,0x21, EOT},
+ {0x85,0x16, EOT}},
+ {NOLDN, "Chip Version",
+ {0x22,EOT},
+ {0x63,EOT}},
+ {NOLDN, "Super I/O Control Register (SIOCTRL)",
+ {0x23,EOT},
+ {0x01,EOT}},
+ {NOLDN, "Super I/O Configuration Register (SIOIRQ)",
+ {0x25,EOT},
+ {0x00,EOT}},
+ {NOLDN, "Super I/O General Purpose Register (SIOGP)",
+ {0x26,EOT},
+ {0x00,EOT}},
+ {NOLDN, "Super I/O Power Mode Register (SIOPWR)",
+ {0x2d,EOT},
+ {0x00,EOT}},
+ {0x01, "UART1",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x03,0xf8,0x00,0x00,0x04,0x02,EOT}},
+ {0x02, "UART2",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x02,0xf8,0x00,0x00,0x04,0x02,EOT}},
+ {0x04, "System Wakup-Up (SWUC)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}},
+ {0x05, "Mouse",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x0C,0x01,EOT}},
+ {0x06, "Keyboard",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}},
+ {0x0f, "Shared Memory/Flash Interface (SMFI)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,
+ 0xf4,0xf5,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ NANA,NANA,EOT}},
+ {0x10, "BRAM / Real Time Clock (RTC)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,
+ 0xf1,0xf2,0xf3,0xf4,0xf5,EOT},
+ {0x00,0x00,0x70,0x00,0x72,0x08,0x01,
+ NANA,NANA,NANA,NANA,NANA,EOT}},
+ {0x11, "Power Management Interface Channel 1",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}},
+ {0x12, "Power Management Interface Channel 2",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x68,0x00,0x6c,0x01,0x01,EOT}},
+ {0x17, "Power Management Interface Channel 3",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
+ {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}},
+ {EOT}}},
{0x8528, "IT8528", {
{NOLDN, NULL,
{0x24,0x25,0x26,0x27,0x28,0x29,
@@ -1388,6 +1442,73 @@
{NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
{EOT}}},
+ {0x8518, "IT8518", {
+ {NOLDN, NULL,
+ {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
+ 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+ 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,
+ 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,
+ 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,
+ 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,
+ 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,
+ 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,
+ 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,
+ 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,
+ 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,
+ 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,
+ 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {NOLDN, NULL,
+ {0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,
+ 0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,
+ NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {EOT}}},
{0x8987, "IT8987", {
{NOLDN, NULL,
{0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
diff --git a/util/superiotool/output b/util/superiotool/output
new file mode 100644
index 0000000..fdf8a94
--- /dev/null
+++ b/util/superiotool/output
@@ -0,0 +1,500 @@
+superiotool r4.11-1185-g6824173704
+Found Aspeed AST2400 (id=0x00) at 0x4e
+Register dump:
+idx val def
+0x20: 0x85 (0x00)
+0x21: 0x18 (0x00)
+0x22: 0x08 (0x00)
+0x23: 0x01 (0x00)
+0x24: 0x00 (0x00)
+0x25: 0x00 (0x00)
+0x26: 0x00 (0x00)
+0x27: 0x00 (0x00)
+0x28: 0x00 (0x00)
+0x29: 0x00 (0x00)
+0x2a: 0x00 (0x00)
+0x2b: 0x00 (0x00)
+0x2c: 0x01 (0x00)
+0x2d: 0x00 (0x00)
+0x2e: 0x00 (0x00)
+0x2f: 0x00 (0x00)
+
+LDN 0x02 (SUART1)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x02 (0x03)
+0x61: 0xf8 (0xf8)
+0x70: 0x03 (0x04)
+0x71: 0x02 (0x02)
+0xf0: 0x00 (RR)
+
+LDN 0x03 (SUART2)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x02)
+0x61: 0x00 (0xf8)
+0x70: 0x00 (0x03)
+0x71: 0x00 (0x02)
+0xf0: 0x00 (0x00)
+
+LDN 0x04 (SWC)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x08)
+0x61: 0x00 (0xe6)
+0x62: 0x00 (0x08)
+0x63: 0x00 (0xe0)
+0x64: 0x00 (0x08)
+0x65: 0x00 (0xe4)
+0x66: 0x00 (0x08)
+0x67: 0x00 (0xe8)
+0x70: 0x00 (0x09)
+0x71: 0x01 (0x01)
+
+LDN 0x05 (Keyboard config (KBC))
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x60)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x64)
+0x70: 0x0c (0x01)
+0x71: 0x01 (0x02)
+0x72: 0x00 (0x0c)
+0x73: 0x00 (0x02)
+0xf0: 0x00 (0x83)
+
+LDN 0x07 (GPIO)
+idx val def
+0x30: 0x00 (0x00)
+0x38: 0x00 (0x00)
+0x70: 0x00 (0x0b)
+0x71: 0x00 (0x01)
+
+LDN 0x0b (SUART3)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x03)
+0x61: 0x00 (0xe8)
+0x70: 0x00 (0x06)
+0x71: 0x00 (0x02)
+0xf0: 0x00 (0x00)
+
+LDN 0x0c (SUART4)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x02)
+0x61: 0x00 (0xe8)
+0x70: 0x00 (0x05)
+0x71: 0x00 (0x02)
+0xf0: 0x00 (0x00)
+
+LDN 0x0d (iLPC2AHB)
+idx val def
+0x30: 0x00 (0x00)
+0x70: 0x00 (0x09)
+0x71: 0x00 (0x01)
+0xf0: 0x00 (NA)
+0xf1: 0x00 (NA)
+0xf2: 0x00 (NA)
+0xf3: 0x00 (NA)
+0xf4: 0x00 (NA)
+0xf5: 0x00 (NA)
+0xf6: 0x00 (NA)
+0xf7: 0x00 (NA)
+0xf8: 0x00 (0x00)
+0xfe: 0x00 (0x00)
+
+LDN 0x0e (Mailbox)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x08)
+0x61: 0x00 (0xc0)
+0x70: 0x00 (0x09)
+0x71: 0x00 (0x01)
+
+Found ITE IT8516??? (id=0x8518, rev=0x8) at 0x4e
+(Chip ID)
+idx val def
+0x20: 0x85 (0x85)
+0x21: 0x18 (0x16)
+
+(Chip Version)
+idx val def
+0x22: 0x08 (0x63)
+
+(Super I/O Control Register (SIOCTRL))
+idx val def
+0x23: 0x01 (0x01)
+
+(Super I/O Configuration Register (SIOIRQ))
+idx val def
+0x25: 0x00 (0x00)
+
+(Super I/O General Purpose Register (SIOGP))
+idx val def
+0x26: 0x00 (0x00)
+
+(Super I/O Power Mode Register (SIOPWR))
+idx val def
+0x2d: 0x00 (0x00)
+
+LDN 0x01 (UART1)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x03 (0x03)
+0x61: 0xf8 (0xf8)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x04 (0x04)
+0x71: 0x02 (0x02)
+
+LDN 0x02 (UART2)
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x02 (0x02)
+0x61: 0xf8 (0xf8)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x03 (0x04)
+0x71: 0x02 (0x02)
+
+LDN 0x04 (System Wakup-Up (SWUC))
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x00)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x00 (0x00)
+0x71: 0x01 (0x01)
+
+LDN 0x05 (Mouse)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x00)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x0c (0x0c)
+0x71: 0x01 (0x01)
+
+LDN 0x06 (Keyboard)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x60 (0x60)
+0x62: 0x00 (0x00)
+0x63: 0x64 (0x64)
+0x70: 0x01 (0x01)
+0x71: 0x01 (0x01)
+
+LDN 0x0f (Shared Memory/Flash Interface (SMFI))
+idx val def
+0x30: 0x00 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x00 (0x00)
+0x62: 0x00 (0x00)
+0x63: 0x00 (0x00)
+0x70: 0x00 (0x00)
+0x71: 0x00 (0x00)
+0xf4: 0x00 (NA)
+0xf5: 0x00 (NA)
+
+LDN 0x10 (BRAM / Real Time Clock (RTC))
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x70 (0x70)
+0x62: 0x09 (0x00)
+0x63: 0x10 (0x72)
+0x70: 0x08 (0x08)
+0x71: 0x01 (0x01)
+0xf1: 0x00 (NA)
+0xf2: 0x00 (NA)
+0xf3: 0x00 (NA)
+0xf4: 0x3f (NA)
+0xf5: 0x3f (NA)
+
+LDN 0x11 (Power Management Interface Channel 1)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x62 (0x62)
+0x62: 0x00 (0x00)
+0x63: 0x66 (0x66)
+0x70: 0x00 (0x01)
+0x71: 0x01 (0x01)
+
+LDN 0x12 (Power Management Interface Channel 2)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x00 (0x00)
+0x61: 0x68 (0x68)
+0x62: 0x00 (0x00)
+0x63: 0x6c (0x6c)
+0x70: 0x00 (0x01)
+0x71: 0x01 (0x01)
+
+LDN 0x17 (Power Management Interface Channel 3)
+idx val def
+0x30: 0x01 (0x00)
+0x60: 0x06 (0x00)
+0x61: 0xa0 (0x6a)
+0x62: 0x06 (0x00)
+0x63: 0xa4 (0x6e)
+0x70: 0x01 (0x01)
+0x71: 0x01 (0x01)
+
+Environment controller (0x0005)
+BRAM (0x0910)
+Register dump:
+idx val def
+0x00: 0x12 (NA)
+0x01: 0x03 (NA)
+0x02: 0x00 (NA)
+0x03: 0x00 (NA)
+0x04: 0x01 (NA)
+0x05: 0x00 (NA)
+0x06: 0x02 (NA)
+0x07: 0x00 (NA)
+0x08: 0xa3 (NA)
+0x09: 0xff (NA)
+0x0a: 0xff (NA)
+0x0b: 0x00 (NA)
+0x0c: 0x00 (NA)
+0x0d: 0x00 (NA)
+0x0e: 0x00 (NA)
+0x0f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x10: 0x00 (NA)
+0x11: 0x00 (NA)
+0x12: 0x00 (NA)
+0x13: 0x00 (NA)
+0x14: 0x00 (NA)
+0x15: 0x00 (NA)
+0x16: 0x00 (NA)
+0x17: 0x00 (NA)
+0x18: 0x00 (NA)
+0x19: 0x00 (NA)
+0x1a: 0x00 (NA)
+0x1b: 0x00 (NA)
+0x1c: 0x00 (NA)
+0x1d: 0x00 (NA)
+0x1e: 0x02 (NA)
+0x1f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x20: 0x01 (NA)
+0x21: 0x10 (NA)
+0x22: 0x00 (NA)
+0x23: 0x00 (NA)
+0x24: 0x00 (NA)
+0x25: 0x00 (NA)
+0x26: 0x00 (NA)
+0x27: 0x00 (NA)
+0x28: 0x00 (NA)
+0x29: 0x00 (NA)
+0x2a: 0x00 (NA)
+0x2b: 0x00 (NA)
+0x2c: 0x00 (NA)
+0x2d: 0x00 (NA)
+0x2e: 0x00 (NA)
+0x2f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x30: 0x00 (NA)
+0x31: 0x00 (NA)
+0x32: 0x24 (NA)
+0x33: 0x00 (NA)
+0x34: 0x00 (NA)
+0x35: 0x10 (NA)
+0x36: 0x00 (NA)
+0x37: 0x00 (NA)
+0x38: 0x00 (NA)
+0x39: 0x00 (NA)
+0x3a: 0x88 (NA)
+0x3b: 0x27 (NA)
+0x3c: 0x68 (NA)
+0x3d: 0x00 (NA)
+0x3e: 0x00 (NA)
+0x3f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x40: 0x00 (NA)
+0x41: 0x00 (NA)
+0x42: 0x00 (NA)
+0x43: 0x00 (NA)
+0x44: 0x00 (NA)
+0x45: 0x00 (NA)
+0x46: 0x00 (NA)
+0x47: 0x00 (NA)
+0x48: 0x00 (NA)
+0x49: 0x00 (NA)
+0x4a: 0x00 (NA)
+0x4b: 0x00 (NA)
+0x4c: 0x00 (NA)
+0x4d: 0x00 (NA)
+0x4e: 0x00 (NA)
+0x4f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x50: 0x00 (NA)
+0x51: 0x00 (NA)
+0x52: 0x00 (NA)
+0x53: 0x00 (NA)
+0x54: 0x00 (NA)
+0x55: 0x00 (NA)
+0x56: 0x00 (NA)
+0x57: 0x00 (NA)
+0x58: 0x00 (NA)
+0x59: 0x00 (NA)
+0x5a: 0x00 (NA)
+0x5b: 0x00 (NA)
+0x5c: 0x00 (NA)
+0x5d: 0x00 (NA)
+0x5e: 0x00 (NA)
+0x5f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x60: 0x00 (NA)
+0x61: 0x00 (NA)
+0x62: 0x00 (NA)
+0x63: 0x00 (NA)
+0x64: 0x00 (NA)
+0x65: 0x00 (NA)
+0x66: 0x00 (NA)
+0x67: 0x00 (NA)
+0x68: 0x00 (NA)
+0x69: 0x00 (NA)
+0x6a: 0x00 (NA)
+0x6b: 0x00 (NA)
+0x6c: 0x00 (NA)
+0x6d: 0x00 (NA)
+0x6e: 0x00 (NA)
+0x6f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x70: 0x00 (NA)
+0x71: 0x00 (NA)
+0x72: 0x00 (NA)
+0x73: 0x00 (NA)
+0x74: 0x00 (NA)
+0x75: 0x00 (NA)
+0x76: 0x00 (NA)
+0x77: 0x00 (NA)
+0x78: 0x00 (NA)
+0x79: 0x00 (NA)
+0x7a: 0x00 (NA)
+0x7b: 0x00 (NA)
+0x7c: 0x00 (NA)
+0x7d: 0x00 (NA)
+0x7e: 0x00 (NA)
+0x7f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x80: 0x12 (NA)
+0x81: 0x03 (NA)
+0x82: 0x00 (NA)
+0x83: 0x00 (NA)
+0x84: 0x01 (NA)
+0x85: 0x00 (NA)
+0x86: 0x02 (NA)
+0x87: 0x00 (NA)
+0x88: 0xa3 (NA)
+0x89: 0xff (NA)
+0x8a: 0xff (NA)
+0x8b: 0x00 (NA)
+0x8c: 0x00 (NA)
+0x8d: 0x00 (NA)
+0x8e: 0x00 (NA)
+0x8f: 0x00 (NA)
+
+Register dump:
+idx val def
+0x90: 0x00 (NA)
+0x91: 0x00 (NA)
+0x92: 0x00 (NA)
+0x93: 0x00 (NA)
+0x94: 0x00 (NA)
+0x95: 0x00 (NA)
+0x96: 0x00 (NA)
+0x97: 0x00 (NA)
+0x98: 0x00 (NA)
+0x99: 0x00 (NA)
+0x9a: 0x00 (NA)
+0x9b: 0x00 (NA)
+0x9c: 0x00 (NA)
+0x9d: 0x00 (NA)
+0x9e: 0x02 (NA)
+0x9f: 0x00 (NA)
+
+Register dump:
+idx val def
+0xa0: 0x01 (NA)
+0xa1: 0x10 (NA)
+0xa2: 0x00 (NA)
+0xa3: 0x00 (NA)
+0xa4: 0x00 (NA)
+0xa5: 0x00 (NA)
+0xa6: 0x00 (NA)
+0xa7: 0x00 (NA)
+0xa8: 0x00 (NA)
+0xa9: 0x00 (NA)
+0xaa: 0x00 (NA)
+0xab: 0x00 (NA)
+0xac: 0x00 (NA)
+0xad: 0x00 (NA)
+0xae: 0x00 (NA)
+0xaf: 0x00 (NA)
+
+Register dump:
+idx val def
+0xb0: 0x00 (NA)
+0xb1: 0x00 (NA)
+0xb2: 0x24 (NA)
+0xb3: 0x00 (NA)
+0xb4: 0x00 (NA)
+0xb5: 0x10 (NA)
+0xb6: 0x00 (NA)
+0xb7: 0x00 (NA)
+0xb8: 0x00 (NA)
+0xb9: 0x00 (NA)
+0xba: 0x88 (NA)
+0xbb: 0x27 (NA)
+0xbc: 0x68 (NA)
+0xbd: 0x00 (NA)
+0xbe: 0x00 (NA)
+0xbf: 0x00 (NA)
+
+Register dump:
+idx val def
+0xc0: 0x00 (NA)
+0xc1: 0x00 (NA)
+0xc2: 0x00 (NA)
+0xc3: 0x00 (NA)
+0xc4: 0x00 (NA)
+0xc5: 0x00 (NA)
+0xc6: 0x00 (NA)
+0xc7: 0x00 (NA)
+0xc8: 0x00 (NA)
+0xc9: 0x00 (NA)
+0xca: 0x00 (NA)
+0xcb: 0x00 (NA)
+0xcc: 0x00 (NA)
+0xcd: 0x00 (NA)
+0xce: 0x00 (NA)
+0xcf: 0x00 (NA)
+
+Found SMSC SCH5317 (id=0x85, rev=0x18) at 0x4e
+No dump available for this Super I/O
+No extra registers known for this chip.
--
To view, visit https://review.coreboot.org/c/coreboot/+/39172
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie68e77af77ccec83c29d3329ee9997b950b351f6
Gerrit-Change-Number: 39172
Gerrit-PatchSet: 1
Gerrit-Owner: Name of user not set #1002723
Gerrit-MessageType: newchange
7
23

Change in ...coreboot[master]: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
by Patrick Rudolph (Code Review) Aug. 7, 2023
by Patrick Rudolph (Code Review) Aug. 7, 2023
Aug. 7, 2023
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33107
Change subject: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
......................................................................
[RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
BOOT_MEDIA_PARAMS2 exposes the boot media MMIO address if it's
memory mapped in addition to various regions inside the bootmedia.
That information can be used by payloads to:
* Support VBOOT on SeaBIOS, as it otherwise uses the RO CBFS only
* Support Intel Apollolake and platforms that don't map the end of
the BIOS region to the end of the address space
* Support fwupd and flashrom finding the FMAP in memory
Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/commonlib/include/commonlib/coreboot_tables.h
M src/lib/coreboot_table.c
2 files changed, 118 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33107/1
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 198ad27..a854e44 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -392,6 +392,81 @@
struct mac_address mac_addrs[0];
};
+/**
+ * coreboot boot media params2
+ *
+ * The coreboot 'boot media params2' contain information about the
+ * bootmedia layout, allowing a payload to read the boot media
+ * without the need to parse (platform specific) layout files.
+ *
+ * It extends 'boot media params' by MMIO addresses and a second CBFS
+ * pointer.
+ *
+ * If the boot media is memory mapped, as it's usually done on x86 platforms,
+ * the FMAP and CBFS can be easily accessed by any software without the need
+ * for platform specific drivers.
+ *
+ * If the boot media is not memory mapped, the `mmap_mmio_address` is set
+ * to ~0ULL. In that case the software must use platform specific drivers
+ * to access the boot media (like flashrom or Linux's MTD).
+ *
+ * The memory mapped area is `mmap_size` bytes in size, starting `mmap_offset`
+ * bytes from `mmap_mmio_address`.
+ * The memory mapped area might be smaller than `boot_media_size` bytes,
+ * which gives the total size in bytes as seen by an external programmer.
+ *
+ * Software utilizing the coreboot boot media params2 shall check if the
+ * region to be access falls completely within the memory mapped region,
+ * before trying to access them.
+ * In addition it should not assume that the whole boot media is memory mapped.
+ *
+ * Example on Intel Apollolake:
+ *
+ * physical memory boot media
+ * +-----------+
+ * | |
+ * | |
+ * +-----------+ MMAP MMIO address +-----------------+ --------
+ * | ~UNAVAIL~ | | | IFD | | | | |
+ * | | MMAP offset | | | | | |
+ * | | | | | | | | |
+ * +-----------+ --- <<< +-----------------+ | | | |
+ * | BIOS REG | | | BIOS | | | | |
+ * | | | | | | | | |
+ * | | | |+---------------+| --+-+-+-+CBFS offset
+ * | | | || CBFS Active || | | |
+ * | | MMAP size |+---------------+| --+-+-+FMAP offset
+ * | | | || FMAP || | |
+ * | | | |+---------------+| --+-+CBFS legacy offset
+ * | | | || COREBOOT(CBFS)|| |
+ * +-----------+ --- <<< |+---------------+| |
+ * | TXE SRAM | || BIOS UNUSABLE || |
+ * | | |+---------------+| |
+ * +-----------+ +-----------------+ |
+ * |DEVICE EXTENSION | |
+ * | | |
+ * +-----------------+ -+Boot media size
+ */
+
+#define LB_TAG_BOOT_MEDIA_PARAMS2 0x0036
+struct lb_boot_media_params2 {
+ uint32_t tag;
+ uint32_t size;
+ /* offsets are relative to start of boot media */
+ uint64_t fmap_offset;
+ uint64_t cbfs_offset;
+ uint64_t cbfs_legacy_offset;
+ uint64_t mmap_offset;
+ /* Size is in bytes */
+ uint64_t cbfs_size;
+ uint64_t fmap_size;
+ uint64_t boot_media_size;
+ uint64_t cbfs_legacy_size;
+ uint64_t mmap_size;
+ /* MMIO address of MMAPed boot media, ~0ULL if not MMAPed.*/
+ uint64_t mmap_mmio_address;
+};
+
#define LB_TAG_SERIALNO 0x002a
#define MAX_SERIALNO_LENGTH 32
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6e44f5d..c5807fd 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -261,8 +261,10 @@
static void lb_boot_media_params(struct lb_header *header)
{
struct lb_boot_media_params *bmp;
+ struct lb_boot_media_params2 *bmp2;
struct cbfs_props props;
const struct region_device *boot_dev;
+ struct region ar;
struct region_device fmrd;
boot_device_init();
@@ -285,6 +287,47 @@
bmp->fmap_offset = ~(uint64_t)0;
if (find_fmap_directory(&fmrd) == 0)
bmp->fmap_offset = region_device_offset(&fmrd);
+
+ /* LB_TAG_BOOT_MEDIA_PARAMS2 exposes additional parameters:
+ * - MMAPed boot media address
+ * - legacy CBFS position (RO partition in case of VBOOT)
+ */
+ bmp2 = (struct lb_boot_media_params2 *)lb_new_record(header);
+ bmp2->tag = LB_TAG_BOOT_MEDIA_PARAMS2;
+ bmp2->size = sizeof(*bmp2);
+
+ bmp2->cbfs_offset = bmp->cbfs_offset;
+ bmp2->cbfs_size = bmp->cbfs_size;
+ bmp2->boot_media_size = bmp->boot_media_size;
+ bmp2->fmap_offset = bmp->fmap_offset;
+
+ if (find_fmap_directory(&fmrd) == 0)
+ bmp2->fmap_size = region_device_size(&fmrd);
+
+ if (fmap_locate_area("COREBOOT", &ar)) {
+ printk(BIOS_INFO, "Can't find 'COREBOOT' area in FMAP\n");
+ bmp2->cbfs_legacy_offset = ~(uint64_t)0;
+ bmp2->cbfs_legacy_size = 0;
+ } else {
+ bmp2->cbfs_legacy_offset = ar.offset;
+ bmp2->cbfs_legacy_size = ar.size;
+ }
+
+ if (CONFIG(COMMON_CBFS_SPI_WRAPPER)) {
+ /* rdev_mmap will return a pointer to _postram_cbfs_cache */
+ bmp2->mmap_offset = ~(uint64_t)0;
+ bmp2->mmap_size = 0;
+ bmp2->mmap_mmio_address = ~(uint64_t)0;
+ } else {
+ /* FIXME: Introduce API to set correct values here */
+ bmp2->mmap_offset = 0;
+ bmp2->mmap_size = bmp2->boot_media_size;
+ /* Get address to MMAP boot media */
+ uintptr_t off = (uintptr_t)rdev_mmap(boot_dev, 0,
+ bmp2->mmap_size);
+ bmp2->mmap_mmio_address = off;
+ rdev_munmap(boot_dev, (void *)off);
+ }
}
static void lb_ram_code(struct lb_header *header)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570
Gerrit-Change-Number: 33107
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
10
22

Change in coreboot[master]: x86: Prevent Kconfig errors resulting in a brick
by Patrick Rudolph (Code Review) Aug. 7, 2023
by Patrick Rudolph (Code Review) Aug. 7, 2023
Aug. 7, 2023
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34709 )
Change subject: x86: Prevent Kconfig errors resulting in a brick
......................................................................
x86: Prevent Kconfig errors resulting in a brick
Always select USE_LEGACY_8254_TIMER if we know we have to.
Fixes boot failure (Linux kernel/GRUB2 hangs with no console output)
on X11SSH-TF using SeaBIOS as payload.
Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M payloads/external/GRUB2/Kconfig.name
M payloads/external/SeaBIOS/Kconfig.name
M src/device/Kconfig
M src/soc/intel/common/block/timer/Kconfig
4 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34709/1
diff --git a/payloads/external/GRUB2/Kconfig.name b/payloads/external/GRUB2/Kconfig.name
index fe60d76..40629ad 100644
--- a/payloads/external/GRUB2/Kconfig.name
+++ b/payloads/external/GRUB2/Kconfig.name
@@ -1,6 +1,7 @@
config PAYLOAD_GRUB2
bool "GRUB2"
depends on ARCH_X86 || ARCH_ARM
+ select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK
help
Select this option if you want to build a coreboot image
with a GRUB2 payload. If you don't know what this is
diff --git a/payloads/external/SeaBIOS/Kconfig.name b/payloads/external/SeaBIOS/Kconfig.name
index bb1f30c..8f92997 100644
--- a/payloads/external/SeaBIOS/Kconfig.name
+++ b/payloads/external/SeaBIOS/Kconfig.name
@@ -1,6 +1,7 @@
config PAYLOAD_SEABIOS
bool "SeaBIOS"
depends on ARCH_X86
+ select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK
help
Select this option if you want to build a coreboot image
with a SeaBIOS payload. If you don't know what this is
diff --git a/src/device/Kconfig b/src/device/Kconfig
index e605bc2..ebf6bfb 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -86,6 +86,7 @@
bool "Run VGA Option ROMs"
depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER
+ select USE_LEGACY_8254_TIMER if SOC_INTEL_COMMON_BLOCK
help
Execute VGA Option ROMs in coreboot if found. This can be used
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig
index a214ef0..66bf9cf 100644
--- a/src/soc/intel/common/block/timer/Kconfig
+++ b/src/soc/intel/common/block/timer/Kconfig
@@ -5,7 +5,6 @@
config USE_LEGACY_8254_TIMER
bool "Use Legacy 8254 Timer"
- default y if PAYLOAD_SEABIOS || VGA_ROM_RUN
default n
help
This sets the FSP UPD to enable Legacy 8254 clock gating. As per
--
To view, visit https://review.coreboot.org/c/coreboot/+/34709
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ica0c20255f661dd61edc3a7d15646b7447c4658e
Gerrit-Change-Number: 34709
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange
11
29

Change in coreboot[master]: sb/intel/common: Add AHCI code
by Patrick Rudolph (Code Review) Aug. 7, 2023
by Patrick Rudolph (Code Review) Aug. 7, 2023
Aug. 7, 2023
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37137 )
Change subject: sb/intel/common: Add AHCI code
......................................................................
sb/intel/common: Add AHCI code
Implement a clean implementation based on AHCI spec 1.0-1.3 and the
Intel ICH/PCH datasheets.
The common implementation should combine all features of the duplicated
code present in the various southbridge implementations.
It compiles on x86_64, uses less magic values and detects the AHCI version
at runtime.
Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
A src/include/ahci.h
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/Makefile.inc
A src/southbridge/intel/common/ahci.c
A src/southbridge/intel/common/ahci.h
5 files changed, 252 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/37137/1
diff --git a/src/include/ahci.h b/src/include/ahci.h
new file mode 100644
index 0000000..e7818fb
--- /dev/null
+++ b/src/include/ahci.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AHCI_H__
+#define __AHCI_H__
+
+/* Serial ATA AHCI 1.3.1 Specification */
+
+#define AHCI_CAP 0x00
+#define AHCI_CAP_NP 0x1f
+#define AHCI_CAP_PSC (1u << 13)
+#define AHCI_CAP_SSC (1u << 14)
+#define AHCI_CAP_PMD (1u << 15)
+#define AHCI_CAP_SPM (1u << 17)
+#define AHCI_CAP_SAM (1u << 18)
+#define AHCI_CAP_SNZO (1u << 19)
+#define AHCI_CAP_ISS(x) ((x) << 20)
+#define AHCI_CAP_SCLO (1u << 24)
+#define AHCI_CAP_SAL (1u << 25)
+#define AHCI_CAP_SALP (1u << 26)
+#define AHCI_CAP_SSS (1u << 27)
+#define AHCI_CAP_SIS (1u << 28)
+#define AHCI_CAP_SNCQ (1u << 30)
+#define AHCI_CAP_S64A (1u << 31)
+/* Added in AHCI 1.1 */
+#define AHCI_CAP_SXS (1u << 5)
+#define AHCI_CAP_EMS (1u << 6)
+#define AHCI_CAP_CCCS (1u << 7)
+/* Added in AHCI 1.2 */
+#define AHCI_CAP_SSNTF (1u << 29)
+
+#define AHCI_GHC 0x04
+#define AHCI_GHC_AE (1u << 31)
+#define AHCI_PI 0x0c
+#define AHCI_VS 0x10
+#define AHCI_VS_MAJOR(x) ((x >> 16) & 0xf)
+#define AHCI_VS_MINOR(x) ((x >> 8) & 0xf)
+
+/* Added in AHCI 1.1 */
+#define AHCI_CCC_CTL 0x14
+#define AHCI_CCC_PORTS 0x18
+#define AHCI_EM_LOC 0x1c
+#define AHCI_EM_CTL 0x20
+/* Added in AHCI 1.2 */
+#define AHCI_CAP2 0x24
+#define AHCI_CAP2_BOH (1u << 0)
+/* Added in AHCI 1.3 */
+#define AHCI_CAP2_NVMP (1u << 1)
+#define AHCI_CAP2_APST (1u << 2)
+#define AHCI_CAP2_SDS (1u << 3)
+#define AHCI_CAP2_SADM (1u << 4)
+#define AHCI_CAP2_DESO (1u << 5)
+
+#define AHCI_BOHC 0x28
+
+#define AHCI_VENDOR 0xa0
+#define AHCI_PORT 0x100
+#define AHCI_PORT_PxCMD 0x18
+#define AHCI_PORT_LEN 0x80
+
+
+#endif
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 18bcd2e..376f077 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -2,6 +2,10 @@
def_bool n
select HAVE_CF9_RESET
+config SOUTHBRIDGE_INTEL_COMMON_AHCI
+ def_bool n
+ depends on PCI
+
config SOUTHBRIDGE_INTEL_COMMON_RTC
def_bool n
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index c8521e1..e87ae82 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -18,6 +18,8 @@
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_AHCI) += ahci.c
+
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
diff --git a/src/southbridge/intel/common/ahci.c b/src/southbridge/intel/common/ahci.c
new file mode 100644
index 0000000..ca20d30
--- /dev/null
+++ b/src/southbridge/intel/common/ahci.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ahci.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+
+#include "ahci.h"
+
+/**
+ * Initialize the AHCI config space.
+ * @param port_map The ports to enable
+ * @param sam Set SAM bit (no legacy device support)
+ * @param cccs Set CCCS bit
+ * @param iss Limit the controller to sata gen x
+ * @param devslp Enable DEVSLP feature if supported
+ * @param clear_vnd Clear bits in vendor config space
+ */
+void sb_ahci_init(struct device *const dev,
+ const u32 port_map,
+ const bool sam,
+ const bool cccs,
+ const u8 iss,
+ const bool devslp,
+ const u32 clear_vnd)
+{
+ u32 reg32;
+ u8 major, minor;
+ struct resource *res;
+ u8 *abar;
+ unsigned int ports;
+
+ /* Initialize AHCI memory-mapped space */
+ res = find_resource(dev, PCI_BASE_ADDRESS_5);
+ if (!res)
+ return;
+
+ abar = res2mmio(res, 0, 0);
+ /*
+ * Set AHCI access mode.
+ * Spec: "No other ABAR registers should be accessed before this."
+ */
+ reg32 = read32(abar + AHCI_GHC);
+ if (!(reg32 & AHCI_GHC_AE)) {
+ reg32 |= AHCI_GHC_AE;
+ write32(abar + AHCI_GHC, reg32);
+ }
+
+ /* Get AHCI version */
+ reg32 = read32(abar + AHCI_VS);
+ major = AHCI_VS_MAJOR(reg32);
+ minor = AHCI_VS_MINOR(reg32);
+ printk(BIOS_DEBUG, "AHCI: implements AHCI %d.%d\n", major, minor);
+
+ reg32 = read32(abar + AHCI_CAP);
+ printk(BIOS_DEBUG, "AHCI: supports SATA Gen%d\n", (reg32 >> 20) & 0xf);
+
+ ports = reg32 & AHCI_CAP_NP;
+ printk(BIOS_DEBUG, "AHCI: supports up to %d ports\n", ports);
+
+ /* CAP (HBA Capabilities) : enable power management */
+ /* Program Write-Once bits (this isn't part of the AHCI spec, but PCH). */
+ if (sam)
+ reg32 |= AHCI_CAP_SAM;
+ if (cccs && major >= 1 && minor >= 1)
+ reg32 |= AHCI_CAP_CCCS;
+ if (iss) {
+ u8 max_iss;
+ if (major >= 1 && minor >= 2)
+ max_iss = MIN(iss, 3);
+ else
+ max_iss = MIN(iss, 2);
+ reg32 &= ~AHCI_CAP_ISS(0xf);
+ reg32 |= AHCI_CAP_ISS(max_iss);
+ printk(BIOS_DEBUG, "AHCI: limited to Gen%d\n", max_iss);
+ }
+ reg32 |= AHCI_CAP_PSC;
+ reg32 |= AHCI_CAP_SSC;
+ reg32 |= AHCI_CAP_SALP;
+ reg32 |= AHCI_CAP_SSS;
+ if (major >= 1 && minor >= 1) {
+ reg32 &= ~AHCI_CAP_SXS;
+ reg32 &= ~AHCI_CAP_EMS;
+ reg32 &= ~AHCI_CAP_SPM;
+ }
+ write32(abar + AHCI_CAP, reg32);
+
+ if (major >= 1 && minor >= 2) {
+ reg32 = read32(abar + AHCI_CAP2);
+ /* Clear BIOS handoff support */
+ reg32 &= ~AHCI_CAP2_BOH;
+ if (major >= 1 && minor >= 3) {
+ /* Configure DEVSLP support */
+ if (devslp) {
+ reg32 |= AHCI_CAP2_APST;
+ reg32 |= AHCI_CAP2_SDS;
+ reg32 |= AHCI_CAP2_SADM;
+ reg32 |= AHCI_CAP2_DESO;
+ } else {
+ reg32 &= ~AHCI_CAP2_SDS;
+ }
+ /* Disable NVMHCI */
+ reg32 &= ~AHCI_CAP2_NVMP;
+ }
+ write32(abar + AHCI_CAP2, reg32);
+ }
+
+ if (port_map & ~((1 << ports) - 1))
+ printk(BIOS_ERR, "AHCI: Invalid port map given!\n");
+
+ write32(abar + AHCI_PI, port_map & ((1 << ports) - 1));
+ /* PCH code reads back twice, do we need it, too? */
+ (void) read32(abar + AHCI_PI); /* Read back 1 */
+ (void) read32(abar + AHCI_PI); /* Read back 2 */
+
+ /* Clear vendor specific bits */
+ reg32 = read32(abar + AHCI_VENDOR);
+ reg32 &= ~clear_vnd;
+ write32(abar + AHCI_VENDOR, reg32);
+
+ /* Lock R/WO bits in Port command registers. */
+ for (size_t i = 0; i < ports; ++i) {
+ if (!((1 << i) & port_map))
+ continue;
+ u8 *addr = abar + AHCI_PORT + (i * AHCI_PORT_LEN);
+ write32(addr, read32(addr + AHCI_PORT_PxCMD));
+ }
+}
diff --git a/src/southbridge/intel/common/ahci.h b/src/southbridge/intel/common/ahci.h
new file mode 100644
index 0000000..9d4a025
--- /dev/null
+++ b/src/southbridge/intel/common/ahci.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_AHCI_H
+#define SOUTHBRIDGE_INTEL_COMMON_AHCI_H
+
+#include <device/device.h>
+
+void sb_ahci_init(struct device *const dev,
+ const u32 port_map,
+ const bool sam,
+ const bool cccs,
+ const u8 iss,
+ const bool devslp,
+ const u32 clear_vnd);
+
+#endif /* SOUTHBRIDGE_INTEL_COMMON_AHCI_H */
+
--
To view, visit https://review.coreboot.org/c/coreboot/+/37137
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5714788aa74b2d8bd855cbc65dd3d78c0a0101b8
Gerrit-Change-Number: 37137
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
8
13

Aug. 7, 2023
Sergey Larin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38253 )
Change subject: src/superio: Add it8987e
......................................................................
src/superio: Add it8987e
Add support for IT8987E SuperIO. Based on it8528e.
Currently untested.
Signed-off-by: cerg2010cerg2010 <cerg2010cerg2010(a)mail.ru>
Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f
---
A src/superio/ite/it8987e/Kconfig
A src/superio/ite/it8987e/Makefile.inc
A src/superio/ite/it8987e/it8987e.h
A src/superio/ite/it8987e/superio.c
4 files changed, 135 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38253/1
diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig
new file mode 100644
index 0000000..b8e3258
--- /dev/null
+++ b/src/superio/ite/it8987e/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8987E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc
new file mode 100644
index 0000000..01e4d3e
--- /dev/null
+++ b/src/superio/ite/it8987e/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c
diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h
new file mode 100644
index 0000000..4e265df
--- /dev/null
+++ b/src/superio/ite/it8987e/it8987e.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8987E_H
+#define SUPERIO_ITE_IT8987E_H
+
+#define IT8987E_SWUC 0x04 /* System Wake-Up */
+#define IT8987E_KBCM 0x05 /* PS/2 mouse */
+#define IT8987E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8987E_IR 0x0a /* Consumer IR */
+#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8987E_RTCT 0x10 /* RTC-like Timer */
+#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */
+#define IT8987E_PECI 0x14 /* Platform EC Interface */
+#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8987E_H */
diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c
new file mode 100644
index 0000000..dce7a6f
--- /dev/null
+++ b/src/superio/ite/it8987e/superio.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010(a)mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+
+#include "it8987e.h"
+
+static void it8987e_init(struct device *dev)
+{
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8987e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, IT8987E_KBCM, PNP_IRQ0, },
+ { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, },
+ { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0
+ | PNP_MSC0 | PNP_MSC1 | PNP_MSC2,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0,
+ 0x07fc, 0x07fc, 0xfff0 },
+ { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 },
+ { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x07ff, 0x07ff },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8987e_ops = {
+ CHIP_NAME("ITE IT8987E Super I/O")
+ .enable_dev = enable_dev,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/38253
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f
Gerrit-Change-Number: 38253
Gerrit-PatchSet: 1
Gerrit-Owner: Sergey Larin <cerg2010cerg2010(a)mail.ru>
Gerrit-MessageType: newchange
4
3
Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39705 )
Change subject: ok
......................................................................
ok
Change-Id: I1049a15110e671b334ab29411b4c148b33f207a6
---
M Documentation/contributing/project_ideas.md
A grub.cfg
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Kconfig
A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
A src/mainboard/dell/dell_system_vostro_3360/board_info.txt
A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
A src/mainboard/dell/dell_system_vostro_3360/early_init.c
A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
A src/mainboard/dell/dell_system_vostro_3360/gpio.c
A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
A src/mainboard/dell/dell_system_vostro_3360/mainboard.c
19 files changed, 782 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39705/1
diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md
index 2c621f4..141023f 100644
--- a/Documentation/contributing/project_ideas.md
+++ b/Documentation/contributing/project_ideas.md
@@ -184,3 +184,66 @@
### Mentors
* TODO
+
+## Fix POST code handling
+coreboot supports writing POST codes to I/O port 80.
+There are various Kconfigs that deal with POST codes, which don't have
+effect on most platforms.
+The code to send POST codes is scattered in C and Assembly, some use
+functions, some use macros and others simply use the `outb` instruction.
+The POST codes are duplicated between stages and aren't documented properly.
+
+
+Tasks:
+* Guard Kconfigs with a *depends on* to only show on supported platforms
+* Remove duplicated Kconfigs
+* Replace `outb(0x80, ...)` with calls to `post_code(...)`
+* Update Documentation/POSTCODES
+* Use defines from console/post_codes.h where possible
+* Drop duplicated POST codes
+* Make use of all possible 255 values
+
+### Requirements
+* knowledge in the coreboot build system and the concept of stages
+* other knowledge: Little experience with C and x86 Assembly
+* hardware requirements: Nothing special
+
+### Mentors
+* Patrick Rudolph <patrick.rudolph(a)9elements.com>
+* Christian Walter <christian.walter(a)9elements.com>
+
+## Board status replacement
+The [Board status page](https://coreboot.org/status/board-status.html) allows
+to see last working commit of a board. The page is generated by a cron job
+that runs on a huge git repository.
+
+Build an open source replacement written in Golang using existing tools
+and libraries, consisting of a backend, a frontend and client side
+scripts. The backend should connect to an SQL database with can be
+controlled using a RESTful API. The RESTful API should have basic authentication
+for managment tasks and new board status uploads.
+
+At least one older test result should be keept in the database.
+
+The frontend should use established UI libraries or frameworks (for example
+Angular) to display the current board status, that is if it's working or not
+and some details provided with the last test. If a board isn't working the last
+working commit (if any) should be shown in addition to the broken one.
+
+Provide a script/tool that allows to:
+1. Push mainboard details from coreboot master CI
+2. Push mainboard test results from authenticated users containing
+ * working
+ * commit hash
+ * bootlog (if any)
+ * dmesg (if it's booting)
+ * timestamps (if it's booting)
+ * coreboot config
+
+### Requirements
+* coreboot knowledge: Non-technical, needed to perform requirements analysis
+* software knowledge: Golang, SQL for the backend, JS for the frontend
+
+### Mentors
+* Patrick Rudolph <patrick.rudolph(a)9elements.com>
+* Christian Walter <christian.walter(a)9elements.com>
diff --git a/grub.cfg b/grub.cfg
new file mode 100644
index 0000000..fd425c3
--- /dev/null
+++ b/grub.cfg
@@ -0,0 +1,4 @@
+configfile (ahci0,3)/boot/grub/grub.cfg
+terminal_output --append cbmemc
+set debug=atkeyb
+
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100644
index 0000000..298c62b
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_DELL
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/dell/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/dell/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Dell Inc."
+
+endif # VENDOR_DELL
diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name
new file mode 100644
index 0000000..3d2fefd
--- /dev/null
+++ b/src/mainboard/dell/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_DELL
+ bool "Dell Inc."
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig
new file mode 100644
index 0000000..dfcc0e1
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig
@@ -0,0 +1,43 @@
+if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_INT15
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ string
+ default dell/dell_system_vostro_3360
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Dell System Vostro 3360"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0156.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0156"
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 60
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
new file mode 100644
index 0000000..8925217
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360
+ bool "Dell System Vostro 3360"
diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
new file mode 100644
index 0000000..18391d8
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
new file mode 100644
index 0000000..a9177df
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl
@@ -0,0 +1 @@
+#include<drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
new file mode 100644
index 0000000..552fb6c
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Method(_WAK, 1)
+{
+ Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl
diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
new file mode 100644
index 0000000..cfc2061
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt
new file mode 100644
index 0000000..be6bff8
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt
@@ -0,0 +1,4 @@
+Category: desktop
+ROM protocol: SPI
+Flashrom support: n
+FIXME: check category, , put ROM package, ROM socketed, Release year
diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
new file mode 100644
index 0000000..d234325
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb
@@ -0,0 +1,111 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "3000"
+ register "gpu_panel_power_backlight_on_delay" = "1700"
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_down_delay" = "300"
+ register "gpu_panel_power_up_delay" = "300"
+ register "gpu_pch_backlight" = "0x13121312"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0x0 on
+ end
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x00040069"
+ register "gen2_dec" = "0x00040911"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x000c06a1"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x1"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x1028 0x055c
+ end
+ device pci 16.0 off # Management Engine Interface 1
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 off # Management Engine KT
+ end
+ device pci 19.0 off # Intel Gigabit Ethernet
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.1 off # PCIe Port #2
+ end
+ device pci 1c.2 off # PCIe Port #3
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 on # PCIe Port #5
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1028 0x055c
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1028 0x055c
+ end
+ device pci 01.0 off # PEG
+ end
+ device pci 02.0 on # iGPU
+ subsystemid 0x1028 0x055c
+ end
+ end
+end
diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
new file mode 100644
index 0000000..98c2ad4
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI 2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c
new file mode 100644
index 0000000..6dbf226
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* FIXME: Check if all includes are needed. */
+
+#include <stdint.h>
+#include <string.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <console/console.h>
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/gpio.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 0, 1, 3 },
+ { 0, 1, 3 },
+ { 1, 1, 4 },
+ { 0, 1, 4 },
+ { 1, 1, 5 },
+ { 0, 1, 5 },
+ { 1, 1, 6 },
+ { 0, 1, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+}
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
new file mode 100644
index 0000000..6cb572a
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads
@@ -0,0 +1,35 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ -- FIXME: check this
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c
new file mode 100644
index 0000000..d7db210
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_NATIVE,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_GPIO,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_GPIO,
+ .gpio62 = GPIO_MODE_GPIO,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_INPUT,
+ .gpio62 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
new file mode 100644
index 0000000..c55bf3c
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10134213, /* Codec Vendor / Device ID: Cirrus */
+ 0x1028055c, /* Subsystem ID */
+ 6, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x0, 0x1028055c),
+ AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f),
+ AZALIA_PIN_CFG(0x0, 0x05, 0x90170010),
+ AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e),
+ AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0),
+ AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c
new file mode 100644
index 0000000..e6f8258
--- /dev/null
+++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/keyboard.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_init(struct device *const dev)
+ {
+ printk(BIOS_DEBUG, "Vostro3360: Initializing keyboard.\n");
+ pc_keyboard_init(NO_AUX_DEVICE);
+ }
+
+static void mainboard_enable(struct device *dev)
+{
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+ dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/39705
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1049a15110e671b334ab29411b4c148b33f207a6
Gerrit-Change-Number: 39705
Gerrit-PatchSet: 1
Gerrit-Owner: Name of user not set #1002723
Gerrit-MessageType: newchange
3
2

Change in coreboot[master]: soc/intel/baytrail: Start VBOOT in bootblock
by Arthur Heymans (Code Review) Aug. 7, 2023
by Arthur Heymans (Code Review) Aug. 7, 2023
Aug. 7, 2023
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36874 )
Change subject: soc/intel/baytrail: Start VBOOT in bootblock
......................................................................
soc/intel/baytrail: Start VBOOT in bootblock
The earlier the more that can be updated via RW fmap regions.
Change-Id: Ifcaf6ad8e27c09fee99cf6a8b12f9fadcb0cef2c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/rambi/Makefile.inc
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/Makefile.inc
M src/soc/intel/baytrail/pmutil.c
4 files changed, 9 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36874/1
diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc
index 0e80b64..6660d23 100644
--- a/src/mainboard/google/rambi/Makefile.inc
+++ b/src/mainboard/google/rambi/Makefile.inc
@@ -13,6 +13,7 @@
## GNU General Public License for more details.
##
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index cfea93a..e4e8c30 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -41,11 +41,8 @@
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
- select VBOOT_STARTS_IN_ROMSTAGE
-
-config BOOTBLOCK_CPU_INIT
- string
- default "soc/intel/baytrail/bootblock/bootblock.c"
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_SEPARATE_VERSTAGE
config MMCONF_BASE_ADDRESS
hex
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index eda3e25..d21f744 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -16,6 +16,8 @@
bootblock-y += ../../../cpu/x86/early_reset.S
bootblock-y += bootblock/bootblock.c
+verstage-y += pmutil.c
+
romstage-y += iosf.c
romstage-y += memmap.c
romstage-y += pmutil.c
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 51174fc..2d14d84 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -368,7 +368,10 @@
{
uint32_t gen_pmcon1;
int rtc_fail;
- struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+ struct chipset_power_state *ps = NULL;
+
+ if (ENV_RAMSTAGE)
+ ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps != NULL)
gen_pmcon1 = ps->gen_pmcon1;
--
To view, visit https://review.coreboot.org/c/coreboot/+/36874
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifcaf6ad8e27c09fee99cf6a8b12f9fadcb0cef2c
Gerrit-Change-Number: 36874
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
4
6

Change in ...coreboot[master]: nb/intel/sandybridge: Introduce soc/iomap.h
by Patrick Rudolph (Code Review) Aug. 7, 2023
by Patrick Rudolph (Code Review) Aug. 7, 2023
Aug. 7, 2023
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32075
Change subject: nb/intel/sandybridge: Introduce soc/iomap.h
......................................................................
nb/intel/sandybridge: Introduce soc/iomap.h
Defines the memory ranges used by the northbridge in a separate header.
Include the new header and rename the defines to match the one found
in soc/intel/common.
Change-Id: I93aa0e78ff52e46256debd26601600a96404509f
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/northbridge/intel/sandybridge/Makefile.inc
M src/northbridge/intel/sandybridge/acpi.c
M src/northbridge/intel/sandybridge/early_init.c
A src/northbridge/intel/sandybridge/include/soc/iomap.h
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/sandybridge/sandybridge.h
8 files changed, 92 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32075/1
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 54a4057..c3d9079 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y)
+CFLAGS_common += -Isrc/northbridge/intel/sandybridge/include
+
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += pcie.c
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 4afb546..af2f37b 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -92,7 +92,8 @@
unsigned long tmp;
tmp = current;
- current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
+ current += acpi_create_dmar_drhd(current, 0, 0,
+ GFXVT_BASE_ADDRESS);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
current += acpi_create_dmar_ds_pci(current, 0, 2, 1);
acpi_dmar_drhd_fixup(tmp, current);
@@ -107,8 +108,8 @@
}
const unsigned long tmp = current;
- current += acpi_create_dmar_drhd(current,
- DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2);
+ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0,
+ VTVC0_BASE_ADDRESS);
current += acpi_create_dmar_ds_ioapic(current,
2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
size_t i;
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 5307a2c..2e0f087 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -35,20 +35,20 @@
return;
/* setup BARs */
- MCHBAR32(0x5404) = IOMMU_BASE1 >> 32;
- MCHBAR32(0x5400) = IOMMU_BASE1 | 1;
- MCHBAR32(0x5414) = IOMMU_BASE2 >> 32;
- MCHBAR32(0x5410) = IOMMU_BASE2 | 1;
+ MCHBAR32(0x5404) = GFXVT_BASE_ADDRESS >> 32;
+ MCHBAR32(0x5400) = GFXVT_BASE_ADDRESS | 1;
+ MCHBAR32(0x5414) = VTVC0_BASE_ADDRESS >> 32;
+ MCHBAR32(0x5410) = VTVC0_BASE_ADDRESS | 1;
/* lock policies */
- write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000);
+ write32((void *)(GFXVT_BASE_ADDRESS + 0xff0), 0x80000000);
const struct device *const azalia = pcidev_on_root(0x1b, 0);
if (azalia && azalia->enabled) {
- write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000);
- write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000);
+ write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x20000000);
+ write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0xa0000000);
} else {
- write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000);
+ write32((void *)(VTVC0_BASE_ADDRESS + 0xff0), 0x80000000);
}
}
@@ -67,12 +67,12 @@
{
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, EP_BASE_ADDRESS | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, EP_BASE_ADDRESS >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, MCH_BASE_ADDRESS | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, MCH_BASE_ADDRESS >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DMI_BASE_ADDRESS | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, DMI_BASE_ADDRESS >> 32);
printk(BIOS_DEBUG, " done\n");
}
diff --git a/src/northbridge/intel/sandybridge/include/soc/iomap.h b/src/northbridge/intel/sandybridge/include/soc/iomap.h
new file mode 100644
index 0000000..75fd9d9
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/include/soc/iomap.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SANDYBRIDGE_IOMAP_H_
+#define _SOC_SANDYBRIDGE_IOMAP_H_
+
+/*
+ * Memory-mapped I/O registers.
+ */
+#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE 0x4000000
+
+/* Intel Enhanced Debug region must be 4MB */
+
+#define IED_SIZE CONFIG_IED_REGION_SIZE
+
+#define ILB_BASE_ADDRESS 0xfed08000ULL
+#define ILB_BASE_SIZE 0x400
+
+#define DMI_BASE_ADDRESS 0xfed18000ULL
+#define DMI_BASE_SIZE 0x1000
+
+#define MCH_BASE_ADDRESS 0xfed10000ULL
+#define MCH_BASE_SIZE 0x4000
+
+#define EP_BASE_ADDRESS 0xfed19000ULL
+#define EP_BASE_SIZE 0x1000
+
+#define GFXVT_BASE_ADDRESS 0xfed90000ULL
+#define GFXVT_BASE_SIZE 0x1000
+
+#define VTVC0_BASE_ADDRESS 0xfed91000ULL
+#define VTVC0_BASE_SIZE 0x1000
+
+#define TPM_BASE_ADDRESS 0xfed40000ULL
+#define TPM_BASE_SIZE 0x5000
+
+
+#endif
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 5aa06c8..71dea62 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -112,8 +112,8 @@
/* Reserve IOMMU BARs */
const u32 capid0_a = pci_read_config32(dev, 0xe4);
if (!(capid0_a & (1 << 23))) {
- mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4);
- mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4);
+ mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, 4);
+ mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, 4);
}
}
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 55df03b..72ae5b0 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -41,23 +41,23 @@
* Channel X = [0, 1]
* Command queue index Y = [0, 1, 2, 3]
*
- * DEFAULT_MCHBAR + 0x4220 + 0x400 * X + 4 * Y: command io register
+ * MCH_BASE_ADDRESS + 0x4220 + 0x400 * X + 4 * Y: command io register
* Controls the DRAM command signals
* Bit 0: !RAS
* Bit 1: !CAS
* Bit 2: !WE
*
- * DEFAULT_MCHBAR + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register
+ * MCH_BASE_ADDRESS + 0x4200 + 0x400 * X + 4 * Y: addr bankslot io register
* Controls the address, bank address and slotrank signals
* Bit 0-15 : Address
* Bit 20-22: Bank Address
* Bit 24-25: slotrank
*
- * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register
+ * MCH_BASE_ADDRESS + 0x4230 + 0x400 * X + 4 * Y: idle register
* Controls the idle time after issuing this DRAM command
* Bit 16-32: number of clock-cylces to idle
*
- * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue
+ * MCH_BASE_ADDRESS + 0x4284 + 0x400 * channel: execute command queue
* Starts to execute all queued commands
* Bit 0 : start DRAM command execution
* Bit 18-19 : number of queued commands - 1
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index c544a74..2382084 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -277,10 +277,10 @@
static void northbridge_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR;
- pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR;
- pei_data->epbar = DEFAULT_EPBAR;
- pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
+ pei_data->mchbar = MCH_BASE_ADDRESS;
+ pei_data->dmibar = DMI_BASE_ADDRESS;
+ pei_data->epbar = EP_BASE_ADDRESS;
+ pei_data->pciexbar = MCFG_BASE_ADDRESS;
pei_data->smbusbar = SMBUS_IO_BASE;
pei_data->wdbbar = 0x4000000;
pei_data->wdbsize = 0x1000;
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index d7de843..dc9f889 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -17,6 +17,8 @@
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
+#include <northbridge/intel/sandybridge/include/soc/iomap.h>
+
/* Device ID for SandyBridge and IvyBridge */
#define BASE_REV_SNB 0x00
#define BASE_REV_IVB 0x50
@@ -34,24 +36,6 @@
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
-/* Intel Enhanced Debug region must be 4MB */
-
-#define IED_SIZE CONFIG_IED_REGION_SIZE
-
-/* Northbridge BARs */
-#ifndef __ACPI__
-#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
-#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
-#else
-#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
-#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
-#endif
-#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
-
-#define IOMMU_BASE1 0xfed90000ULL
-#define IOMMU_BASE2 0xfed91000ULL
-
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
#include <cpu/intel/model_206ax/model_206ax.h>
@@ -118,9 +102,9 @@
* MCHBAR
*/
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR8(x) (*((volatile u8 *)((uintptr_t)MCH_BASE_ADDRESS + (x))))
+#define MCHBAR16(x) (*((volatile u16 *)((uintptr_t)MCH_BASE_ADDRESS + (x))))
+#define MCHBAR32(x) (*((volatile u32 *)((uintptr_t)MCH_BASE_ADDRESS + (x))))
#define MCHBAR32_OR(x, or) (MCHBAR32(x) = (MCHBAR32(x) | (or)))
#define MCHBAR32_AND(x, and) (MCHBAR32(x) = (MCHBAR32(x) & (and)))
#define MCHBAR32_AND_OR(x, and, or) \
@@ -133,9 +117,9 @@
* EPBAR - Egress Port Root Complex Register Block
*/
-#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
-#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
-#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
+#define EPBAR8(x) (*((volatile u8 *)((uintptr_t)EP_BASE_ADDRESS + (x))))
+#define EPBAR16(x) (*((volatile u16 *)((uintptr_t)EP_BASE_ADDRESS + (x))))
+#define EPBAR32(x) (*((volatile u32 *)((uintptr_t)EP_BASE_ADDRESS + (x))))
#define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */
@@ -164,9 +148,9 @@
* DMIBAR
*/
-#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
+#define DMIBAR8(x) (*((volatile u8 *)((uintptr_t)DMI_BASE_ADDRESS + (x))))
+#define DMIBAR16(x) (*((volatile u16 *)((uintptr_t)DMI_BASE_ADDRESS + (x))))
+#define DMIBAR32(x) (*((volatile u32 *)((uintptr_t)DMI_BASE_ADDRESS + (x))))
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I93aa0e78ff52e46256debd26601600a96404509f
Gerrit-Change-Number: 32075
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
6
9

Change in coreboot[master]: console,boot_state: Denote unit in beginning in log message
by Paul Menzel (Code Review) Aug. 7, 2023
by Paul Menzel (Code Review) Aug. 7, 2023
Aug. 7, 2023
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38136 )
Change subject: console,boot_state: Denote unit in beginning in log message
......................................................................
console,boot_state: Denote unit in beginning in log message
Looking at the board status repository logs, lines similar to
BS: postcar times (exec / console): total (unknown) / 0 ms
BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms
are not obvious right away, as the unit visually only applies to the
value after the slash.
So, add the unit after `times`.
BS: BS_DEV_ENUMERATE run times [ms] (exec / console): 6 / 0
Change-Id: If01a5d43a54aeefc0a6d49d4b600436c2a8328cd
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/console/printk.c
M src/lib/hardwaremain.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/38136/1
diff --git a/src/console/printk.c b/src/console/printk.c
index 3ef28f3..be7c98b 100644
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -49,7 +49,7 @@
if (!TRACK_CONSOLE_TIME)
return;
- printk(BIOS_DEBUG, "BS: " ENV_STRING " times (exec / console): total (unknown) / %ld ms\n",
+ printk(BIOS_DEBUG, "BS: " ENV_STRING " times [ms] (exec / console): total (unknown) / %ld\n",
DIV_ROUND_CLOSEST(console_usecs, USECS_PER_MSEC));
}
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index eba5f12..cf1e1b7 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -250,7 +250,7 @@
execution = DIV_ROUND_CLOSEST(execution, USECS_PER_MSEC);
console = DIV_ROUND_CLOSEST(console, USECS_PER_MSEC);
if (execution) {
- printk(BIOS_DEBUG, "BS: %s %s times (exec / console): %ld / %ld ms\n",
+ printk(BIOS_DEBUG, "BS: %s %s times [ms] (exec / console): %ld / %ld\n",
state->name, sample_id[i], execution - console, console);
/* Reset again to ignore printk() time above. */
console_time_get_and_reset();
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If01a5d43a54aeefc0a6d49d4b600436c2a8328cd
Gerrit-Change-Number: 38136
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
5
8

Change in coreboot[master]: util/lint/checkpatch: Update to 96 char line length limit
by Paul Menzel (Code Review) Aug. 7, 2023
by Paul Menzel (Code Review) Aug. 7, 2023
Aug. 7, 2023
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38677 )
Change subject: util/lint/checkpatch: Update to 96 char line length limit
......................................................................
util/lint/checkpatch: Update to 96 char line length limit
Follow up on commit bcbf2deb42 (Documentation/coding_style.md: Update
line length limit) and update the script `checkpatch.pl`.
Change-Id: I2b5c5d4cf9f0534298d00e76173cd448e8e13281
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M util/lint/checkpatch.pl
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38677/1
diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl
index 1affdb7..c6cbe69 100755
--- a/util/lint/checkpatch.pl
+++ b/util/lint/checkpatch.pl
@@ -51,7 +51,7 @@
my @exclude = (); #coreboot
my $help = 0;
my $configuration_file = ".checkpatch.conf";
-my $max_line_length = 80;
+my $max_line_length = 96;
my $ignore_perl_version = 0;
my $minimum_perl_version = 5.10.0;
my $min_conf_desc_length = 4;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2b5c5d4cf9f0534298d00e76173cd448e8e13281
Gerrit-Change-Number: 38677
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
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