coreboot-gerrit March 2020

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Change in coreboot[master]: nb/intel/sandybridge: Fix shift error
by Patrick Georgi (Code Review) 10 Mar '20

10 Mar '20

Patrick Georgi has uploaded a new patch set (#3) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/23362 ) Change subject: nb/intel/sandybridge: Fix shift error ...................................................................... nb/intel/sandybridge: Fix shift error ``` src/northbridge/intel/sandybridge/early_init.c: In function 'sandybridge_setup_graphics': src/northbridge/intel/sandybridge/early_init.c:141:14: error: result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] reg32 |= (1 << 31); ^~ cc1: all warnings being treated as errors ``` Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/northbridge/intel/sandybridge/early_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/23362/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/23362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075 Gerrit-Change-Number: 23362 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config
by PraveenX Hodagatta Pranesh (Code Review) 10 Mar '20

10 Mar '20

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36423 ) Change subject: mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config ...................................................................... mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36423/1 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 670a474..ea35785 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -34,7 +34,7 @@ register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "1" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 385a4be..22013bf 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -43,7 +43,7 @@ register "Device4Enable" = "0" register "Heci3Enabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch -- To view, visit https://review.coreboot.org/c/coreboot/+/36423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Gerrit-Change-Number: 36423 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: src: REmove unneeded 'include <arch/cache.h>'
by HAOUAS Elyes (Code Review) 10 Mar '20

10 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37984 ) Change subject: src: REmove unneeded 'include <arch/cache.h>' ...................................................................... src: REmove unneeded 'include <arch/cache.h>' Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/exception.c M src/arch/arm/armv7/mmu.c M src/arch/arm/boot.c M src/arch/arm/include/armv7/arch/mmio.h M src/arch/arm/stages.c M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/bl31.c M src/arch/arm64/boot.c M src/arch/arm64/transition.c M src/commonlib/storage/bouncebuf.c M src/cpu/ti/am335x/bootblock.c M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/gale/mmu.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/storm/mmu.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/soc/nvidia/tegra124/cache.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra124/verstage.c M src/soc/nvidia/tegra210/arm_tf.c M src/soc/nvidia/tegra210/sdram_lp0.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/spi.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/qcs405/mmu.c M src/soc/qualcomm/sc7180/aop_load_reset.c M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/qspi.c M src/soc/qualcomm/sdm845/aop_load_reset.c M src/soc/qualcomm/sdm845/mmu.c M src/soc/qualcomm/sdm845/qspi.c M src/soc/rockchip/rk3288/bootblock.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/display.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/bootblock.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/wakeup.c 56 files changed, 0 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/37984/1 diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index d6891b0..55fb780 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -29,7 +29,6 @@ #include <stdint.h> #include <types.h> -#include <arch/cache.h> #include <arch/exception.h> #include <console/console.h> diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 77b9b4b..8fc0c37 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -35,7 +35,6 @@ #include <console/console.h> -#include <arch/cache.h> #if CONFIG(ARM_LPAE) /* See B3.6.2 of ARMv7 Architecture Reference Manual */ diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 9d1e4cd..c689829 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <program_loading.h> void arch_prog_run(struct prog *prog) diff --git a/src/arch/arm/include/armv7/arch/mmio.h b/src/arch/arm/include/armv7/arch/mmio.h index 87f6871..3259080 100644 --- a/src/arch/arm/include/armv7/arch/mmio.h +++ b/src/arch/arm/include/armv7/arch/mmio.h @@ -17,7 +17,6 @@ #ifndef __ARCH_MMIO_H__ #define __ARCH_MMIO_H__ -#include <arch/cache.h> /* for dmb() */ #include <endian.h> #include <stdint.h> diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c index fc2ebdb..53fa5cb 100644 --- a/src/arch/arm/stages.c +++ b/src/arch/arm/stages.c @@ -24,7 +24,6 @@ #include <cbmem.h> #include <arch/stages.h> -#include <arch/cache.h> /** * generic stage entry point. override this if board specific code is needed. diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 46dc859..91ac8fc 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -33,7 +33,6 @@ #include <stdint.h> -#include <arch/cache.h> #include <arch/lib_helpers.h> #include <program_loading.h> diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 4d566aa..097be1b 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -30,7 +30,6 @@ #include <stdint.h> #include <types.h> #include <arch/barrier.h> -#include <arch/cache.h> #include <arch/exception.h> #include <arch/transition.h> #include <console/console.h> diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index bdec55c..95a4a70 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -35,7 +35,6 @@ #include <console/console.h> #include <arch/mmu.h> #include <arch/lib_helpers.h> -#include <arch/cache.h> /* This just caches the next free table slot (okay to do since they fill up from * bottom to top and can never be freed up again). It will reset to its initial diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c index c94b1d1..7089cbd 100644 --- a/src/arch/arm64/bl31.c +++ b/src/arch/arm64/bl31.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/lib_helpers.h> #include <arch/mmu.h> #include <arch/transition.h> diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 479a910..275dfbc 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -12,7 +12,6 @@ */ #include <cbmem.h> -#include <arch/cache.h> #include <arch/lib_helpers.h> #include <arch/stages.h> #include <arch/transition.h> diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index ac59d19..2681f55 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/lib_helpers.h> #include <arch/mmu.h> #include <arch/transition.h> diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 99287b6..4cbaa52 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -14,7 +14,6 @@ * Generic bounce buffer implementation */ -#include <arch/cache.h> #include "bouncebuf.h" #include "storage.h" #include <string.h> diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c index 93c29c0..5a39dd1 100644 --- a/src/cpu/ti/am335x/bootblock.c +++ b/src/cpu/ti/am335x/bootblock.c @@ -13,7 +13,6 @@ #include <types.h> -#include <arch/cache.h> #include <bootblock_common.h> void bootblock_soc_init(void) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 30f8805..2b1098a 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <delay.h> diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 0857024..e200640 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <armv7.h> #include <cbmem.h> diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index 7ac8b92..120a2dc 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -10,7 +10,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <symbols.h> #include <soc/soc_services.h> #include "mmu.h" diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 5cc7f6e..1ba74fc 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 5cc7f6e..1ba74fc 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 7a1b5fa..d8446bd 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index 421826c..ece6b85 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <boardid.h> #include <bootmode.h> #include <console/console.h> diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 553c2ad..60d35cd 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <boot/coreboot_tables.h> #include <console/console.h> #include <device/mmio.h> diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 0c2cb3e..c9c45d2 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <armv7.h> #include <boot_device.h> diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 3f1515a..ca6fd5a 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -10,7 +10,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <soc/soc_services.h> #include <symbols.h> #include "mmu.h" diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 8aa20aa..6d6a271 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <delay.h> diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index eba96c4..5309ec5 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <armv7.h> #include <assert.h> diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 2de720c..f7af1cf 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <device/device.h> diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index d20bdb4..95a7e48 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <armv7.h> #include <assert.h> diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 52ecbf6..8c775b6 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <console/console.h> diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index ac651ef..4734648 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <device/mmio.h> #include <armv7.h> diff --git a/src/soc/nvidia/tegra124/cache.c b/src/soc/nvidia/tegra124/cache.c index 5c3a43d..2e800a3 100644 --- a/src/soc/nvidia/tegra124/cache.c +++ b/src/soc/nvidia/tegra124/cache.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <soc/cache.h> #include <stdint.h> diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 7e930d1..d8ec93f 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -15,7 +15,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ #define __SOC_NVIDIA_TEGRA124_CHIP_H__ -#include <arch/cache.h> #include <gpio.h> #include <soc/addressmap.h> diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index aade07c..680a21b 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 007d189..4395dbf 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <assert.h> #include <boot_device.h> diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 6564dcb..4acb3cb 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/exception.h> #include <arch/hlt.h> #include <arch/stages.h> diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index e0863d2..87e17f9 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <assert.h> #include <bl31.h> #include <soc/addressmap.h> diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 09747ea..8555051 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <console/console.h> #include <soc/addressmap.h> #include <soc/pmc.h> diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index cedcc18..a4cea70 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <bootmem.h> #include <bootmode.h> #include <bootstate.h> diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index b0142a4..6171415 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <assert.h> #include <boot_device.h> diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 9d608fa..63d7fa8 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 2da868b..6eed141 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <cbfs.h> #include <console/console.h> diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index a2d626f..1d2b63f 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -15,7 +15,6 @@ #include <symbols.h> #include <arch/mmu.h> -#include <arch/cache.h> #include <soc/mmu.h> #include <soc/symbols.h> diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 5cf2311..8b69918 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <cbfs.h> #include <halt.h> #include <console/console.h> diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 2eb8c86..f4b2d40 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -15,7 +15,6 @@ #include <symbols.h> #include <arch/mmu.h> -#include <arch/cache.h> #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index 30dc1c3..6ed47de 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -15,7 +15,6 @@ #include <spi-generic.h> #include <spi_flash.h> -#include <arch/cache.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/qspi.h> diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 782c83a..3c73ee6 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <cbfs.h> #include <console/console.h> #include <soc/mmu.h> diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index e63bfed..aaef3f3 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -15,7 +15,6 @@ #include <symbols.h> #include <arch/mmu.h> -#include <arch/cache.h> #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index cced567..684f150 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -15,7 +15,6 @@ #include <spi-generic.h> #include <spi_flash.h> -#include <arch/cache.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/qspi.h> diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 8988804..240479d 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <bootblock_common.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index a66b2d4..62870fb 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 31c9998..9fb27cd 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <bootmode.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 9cd4053..1db7f99 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <arch/mmu.h> #include <device/mmio.h> #include <console/console.h> diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 5f99899..ca3f1fc 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index deb4f02..d9dcc38 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <boot_device.h> #include <console/console.h> #include <soc/alternate_cbfs.h> diff --git a/src/soc/samsung/exynos5420/bootblock.c b/src/soc/samsung/exynos5420/bootblock.c index 8e51774..1fd14b7 100644 --- a/src/soc/samsung/exynos5420/bootblock.c +++ b/src/soc/samsung/exynos5420/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <bootblock_common.h> #include <soc/clk.h> #include <soc/wakeup.h> diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 375b370..2c9421f 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c index 2bcc6b4..a2219b2 100644 --- a/src/soc/samsung/exynos5420/wakeup.c +++ b/src/soc/samsung/exynos5420/wakeup.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/cache.h> #include <soc/power.h> #include <soc/wakeup.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Gerrit-Change-Number: 37984 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: winbond/w83667hg-a: Disable mouse controller also during resume
by Patrick Georgi (Code Review) 10 Mar '20

10 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/22286 ) Change subject: winbond/w83667hg-a: Disable mouse controller also during resume ...................................................................... winbond/w83667hg-a: Disable mouse controller also during resume There is no reason to not disable the controller during resume. That way, no ASL is needed. Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/superio/winbond/w83667hg-a/superio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index bc7bd92..6850621 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -36,7 +36,7 @@ mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE); - if (!mouse_detected && !acpi_is_wakeup_s3()) { + if (!mouse_detected) { printk(BIOS_INFO, "%s: Disable mouse controller.", __func__); pnp_enter_conf_mode(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/22286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Gerrit-Change-Number: 22286 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: winbond/w83667hg-a: Disable mouse controller also during resume
by Patrick Georgi (Code Review) 10 Mar '20

10 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22286 ) Change subject: winbond/w83667hg-a: Disable mouse controller also during resume ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/22286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Gerrit-Change-Number: 22286 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Mar 2020 20:37:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/board_status: Add support of CMOS values dump
by 9elements QA (Code Review) 10 Mar '20

10 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28565 ) Change subject: util/board_status: Add support of CMOS values dump ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1233 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1232 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1231 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/28565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89f9a0e9622557b01dda52378f8f1323777bce39 Gerrit-Change-Number: 28565 Gerrit-PatchSet: 3 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 10 Mar 2020 20:32:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34663 ) Change subject: soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode ...................................................................... soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode SATA Mode Select is bit 16 of the SATA General Configuration register. This code currently incorrectly pokes at the Port Clock Disable bits in the Port Mapping Register, and without clock the affected ports can't link. Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/sata.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34663/1 diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index ddb8b02..610a4c6 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -31,7 +31,6 @@ static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u32 abar; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -46,10 +45,9 @@ printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set the controller mode */ - reg16 = pci_read_config16(dev, SATA_MAP); - reg16 &= ~(3 << 6); - reg16 |= SATA_MAP_AHCI; - pci_write_config16(dev, SATA_MAP, reg16); + reg32 = pci_read_config16(dev, SATAGC); + reg32 &= ~SATAGC_AHCI; + pci_write_config16(dev, SATAGC, reg32); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); -- To view, visit https://review.coreboot.org/c/coreboot/+/34663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Gerrit-Change-Number: 34663 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/intel: fix eist enabling
by Matt Delco (Code Review) 10 Mar '20

10 Mar '20

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39411 ) Change subject: soc/intel: fix eist enabling ...................................................................... soc/intel: fix eist enabling There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco <delco(a)chromium.org> Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 4 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39411/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index f01b499..3ba0562 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -263,9 +263,10 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index e058442..91282d8 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -71,9 +71,10 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index f5273f6..d7da56e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -291,14 +291,11 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - - if (conf->eist_enable) - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - else - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ - wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); + /* Disable Thermal interrupts */ msr.lo = 0; msr.hi = 0; diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 5f4f081..cfbfdb3 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -77,9 +77,10 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); + /* Set EIST status */ cpu_set_eist(conf->eist_enable); - wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ msr.lo = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Gerrit-Change-Number: 39411 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: Documentation: Update codenames
by Swift Geek (Sebastian Grzywna) (Code Review) 10 Mar '20

10 Mar '20

Swift Geek (Sebastian Grzywna) has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34352 ) Change subject: Documentation: Update codenames ...................................................................... Documentation: Update codenames austin-3 was a devel board, retracting t60 comes in variants with discrete gpu and only intel gpu one Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek(a)gmail.com> --- M Documentation/mainboard/lenovo/codenames.csv 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/34352/1 diff --git a/Documentation/mainboard/lenovo/codenames.csv b/Documentation/mainboard/lenovo/codenames.csv index ad77059..655ff7b 100644 --- a/Documentation/mainboard/lenovo/codenames.csv +++ b/Documentation/mainboard/lenovo/codenames.csv @@ -1,4 +1,6 @@ -t60,magi-5|magi-7|austin-3 +t60,magi (dGPU) | lisa (iGPU) +z61m,BW2 +z61t,BV2 t400,malibu-3 t400s,shinai t410,nozomi-1 @@ -16,13 +18,18 @@ w520,kendo-3 workstation w530,kendo-4 workstation w700,n-note +w701,n-note 3.0 (nico-3) x1_carbon_gen1,genesis-1 x60,ks note x61,ks note-3 x200,mocha-1 +x200s,pecan-1 +x200t,caramel-1 x201,mocha-3 x220,dasher-1 +x220t,comet-1 x230,dasher-2 +x230t,comet-2 x230s,rogue-1 x240,rogue-2 x300,kodachi -- To view, visit https://review.coreboot.org/c/coreboot/+/34352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d Gerrit-Change-Number: 34352 Gerrit-PatchSet: 1 Gerrit-Owner: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/nvramtool: fix building on OpenBSD
by Evgeny Zinoviev (Code Review) 10 Mar '20

10 Mar '20

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38348 ) Change subject: util/nvramtool: fix building on OpenBSD ...................................................................... util/nvramtool: fix building on OpenBSD OpenBSD's gcc 4.2.1 doesn't know about _Noreturn Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M util/nvramtool/common.c M util/nvramtool/common.h 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38348/1 diff --git a/util/nvramtool/common.c b/util/nvramtool/common.c index 9b0a6b9..5dfc3bd 100644 --- a/util/nvramtool/common.c +++ b/util/nvramtool/common.c @@ -56,7 +56,7 @@ * * We ran out of memory. Print an error message and die. ****************************************************************************/ -_Noreturn void out_of_memory(void) +noreturn void out_of_memory(void) { fprintf(stderr, "%s: Out of memory.\n", prog_name); exit(1); diff --git a/util/nvramtool/common.h b/util/nvramtool/common.h index 19ce566..f49bc33 100644 --- a/util/nvramtool/common.h +++ b/util/nvramtool/common.h @@ -69,6 +69,12 @@ #define MAP_SHARED 1 #endif +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define noreturn _Noreturn +#else +#define noreturn +#endif + /* basename of this program, as reported by argv[0] */ extern const char prog_name[]; @@ -76,7 +82,7 @@ extern const char prog_version[]; int get_line_from_file(FILE * f, char line[], int line_buf_size); -_Noreturn void out_of_memory(void); +noreturn void out_of_memory(void); void usage(FILE * outfile); #endif /* COMMON_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db Gerrit-Change-Number: 38348 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

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