Patrick Georgi has uploaded a new patch set (#3) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/23362 )
Change subject: nb/intel/sandybridge: Fix shift error
......................................................................
nb/intel/sandybridge: Fix shift error
```
src/northbridge/intel/sandybridge/early_init.c: In function
'sandybridge_setup_graphics':
src/northbridge/intel/sandybridge/early_init.c:141:14: error:
result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]
reg32 |= (1 << 31);
^~
cc1: all warnings being treated as errors
```
Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/northbridge/intel/sandybridge/early_init.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/23362/3
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075
Gerrit-Change-Number: 23362
Gerrit-PatchSet: 3
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/22286 )
Change subject: winbond/w83667hg-a: Disable mouse controller also during resume
......................................................................
winbond/w83667hg-a: Disable mouse controller also during resume
There is no reason to not disable the controller during resume. That
way, no ASL is needed.
Change-Id: I282a03647ee0958abb118fafe306abe5782db71c
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/superio/winbond/w83667hg-a/superio.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c
index bc7bd92..6850621 100644
--- a/src/superio/winbond/w83667hg-a/superio.c
+++ b/src/superio/winbond/w83667hg-a/superio.c
@@ -36,7 +36,7 @@
mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE);
- if (!mouse_detected && !acpi_is_wakeup_s3()) {
+ if (!mouse_detected) {
printk(BIOS_INFO, "%s: Disable mouse controller.",
__func__);
pnp_enter_conf_mode(dev);
--
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Gerrit-Change-Id: I282a03647ee0958abb118fafe306abe5782db71c
Gerrit-Change-Number: 22286
Gerrit-PatchSet: 2
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
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Gerrit-MessageType: merged
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22286 )
Change subject: winbond/w83667hg-a: Disable mouse controller also during resume
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com>
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Gerrit-Comment-Date: Tue, 10 Mar 2020 20:37:22 +0000
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9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28565 )
Change subject: util/board_status: Add support of CMOS values dump
......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1233
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1232
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1231
Please note: This test is under development and might not be accurate at all!
--
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Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.io>
Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34663 )
Change subject: soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
......................................................................
soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode
SATA Mode Select is bit 16 of the SATA General Configuration
register. This code currently incorrectly pokes at the Port Clock
Disable bits in the Port Mapping Register, and without clock the
affected ports can't link.
Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed
Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com>
---
M src/soc/intel/denverton_ns/sata.c
1 file changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34663/1
diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c
index ddb8b02..610a4c6 100644
--- a/src/soc/intel/denverton_ns/sata.c
+++ b/src/soc/intel/denverton_ns/sata.c
@@ -31,7 +31,6 @@
static void sata_init(struct device *dev)
{
u32 reg32;
- u16 reg16;
u32 abar;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@@ -46,10 +45,9 @@
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set the controller mode */
- reg16 = pci_read_config16(dev, SATA_MAP);
- reg16 &= ~(3 << 6);
- reg16 |= SATA_MAP_AHCI;
- pci_write_config16(dev, SATA_MAP, reg16);
+ reg32 = pci_read_config16(dev, SATAGC);
+ reg32 &= ~SATAGC_AHCI;
+ pci_write_config16(dev, SATAGC, reg32);
/* Initialize AHCI memory-mapped space */
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
--
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