coreboot-gerrit March 2020

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Change in coreboot[master]: nb/intel/sandybridge: Fix shift error
by Angel Pons (Code Review) 10 Mar '20

10 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23362 ) Change subject: nb/intel/sandybridge: Fix shift error ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/23362/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/23362/3//COMMIT_MSG@10 PS3, Line 10: src/northbridge/intel/sandybridge/early_init.c: In function > With the coreboot toolchain and https://review.coreboot. […] Then maybe mention that, when using `-Wshift-overflow=2`, this appears -- To view, visit https://review.coreboot.org/c/coreboot/+/23362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075 Gerrit-Change-Number: 23362 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Mar 2020 21:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Fix shift error
by Paul Menzel (Code Review) 10 Mar '20

10 Mar '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23362 ) Change subject: nb/intel/sandybridge: Fix shift error ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/23362/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/23362/3//COMMIT_MSG@10 PS3, Line 10: src/northbridge/intel/sandybridge/early_init.c: In function > With which toolchain does this error happen? With the coreboot toolchain and https://review.coreboot.org/c/coreboot/+/23360/ -- To view, visit https://review.coreboot.org/c/coreboot/+/23362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075 Gerrit-Change-Number: 23362 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Mar 2020 21:57:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Fix shift error
by Angel Pons (Code Review) 10 Mar '20

10 Mar '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23362 ) Change subject: nb/intel/sandybridge: Fix shift error ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/23362/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/23362/3//COMMIT_MSG@10 PS3, Line 10: src/northbridge/intel/sandybridge/early_init.c: In function With which toolchain does this error happen? -- To view, visit https://review.coreboot.org/c/coreboot/+/23362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075 Gerrit-Change-Number: 23362 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Mar 2020 21:18:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format
by Patrick Georgi (Code Review) 10 Mar '20

10 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/25546 ) Change subject: util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format ...................................................................... util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format Intel supplies microcode (at least for MinnowBoard) in Intel Assembly *.inc format rather than C header. This change allow to pass in configuration directory with *.inc files rather than list of *.h files. Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540 Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/scripts/ucode_h_to_bin.sh 1 file changed, 19 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/util/scripts/ucode_h_to_bin.sh b/util/scripts/ucode_h_to_bin.sh index f08b053..436c0fd 100755 --- a/util/scripts/ucode_h_to_bin.sh +++ b/util/scripts/ucode_h_to_bin.sh @@ -30,7 +30,7 @@ # if [ -z "$1" ] || [ -z "$2" ]; then - printf "Usage: %s <output file> \"<microcode .h files>\"\n" "$0" + printf "Usage: %s <output file> \"<microcode .h files>\"\\n" "$0" fi OUTFILE=$1 @@ -40,8 +40,24 @@ unsigned int microcode[] = { EOF -for UCODE in ${@:2}; do - echo "#include \"$UCODE\"" >> "${TMPFILE}.c" +include_file() { + if [ "${1: -4}" == ".inc" ]; then + awk '{gsub( /h.*$/, "", $2 ); print "0x" $2 ","; }' "$1" \ + >> "${TMPFILE}.c" + else + echo "#include \"$1\"" >> "${TMPFILE}.c" + fi +} + +for UCODE in "${@:2}"; do + if [ -d "$UCODE" ]; then + for f in "$UCODE/"*.inc + do + include_file "$f" + done + else + include_file "$UCODE" + fi done cat >> "${TMPFILE}.c" << EOF -- To view, visit https://review.coreboot.org/c/coreboot/+/25546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540 Gerrit-Change-Number: 25546 Gerrit-PatchSet: 4 Gerrit-Owner: Lev Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lev Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format
by Patrick Georgi (Code Review) 10 Mar '20

10 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25546 ) Change subject: util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540 Gerrit-Change-Number: 25546 Gerrit-PatchSet: 3 Gerrit-Owner: Lev Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lev Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 10 Mar 2020 20:50:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common: Add more GPIO definition macros
by Thomas Heijligen (Code Review) 10 Mar '20

10 Mar '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31350 to review the following change. Change subject: soc/intel/common: Add more GPIO definition macros ...................................................................... soc/intel/common: Add more GPIO definition macros Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31350/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9..4d9f2be 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -236,6 +236,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Gerrit-Change-Number: 31350 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34714 ) Change subject: soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling ...................................................................... soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling This code also sets unused interrupt lines to the recommended safe value of 0xff instead of ignoring such devices. Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434 Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/lpc.c 1 file changed, 259 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/34714/1 diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 5af0781..5f43e63 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -65,6 +65,261 @@ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } +/* interrupt router lookup for internal devices */ +struct dnv_ir_lut { + /* (dev << 3) | fn */ + u8 devfn; + u8 ir; +}; + +#define DEVFN(dev, fn) ((dev << 3) | (fn)) + +static const struct dnv_ir_lut dnv_ir_lut[] = { + {.devfn = DEVFN(0x05, 0), .ir = 3}, /* RCEC */ + {.devfn = DEVFN(0x06, 0), .ir = 4}, /* Virtual RP to QAT */ + {.devfn = DEVFN(0x09, 0), .ir = 7}, /* PCIe RP0 */ + {.devfn = DEVFN(0x0a, 0), .ir = 7}, /* PCIe RP1 */ + {.devfn = DEVFN(0x0b, 0), .ir = 7}, /* PCIe RP2 */ + {.devfn = DEVFN(0x0c, 0), .ir = 7}, /* PCIe RP3 */ + {.devfn = DEVFN(0x0e, 0), .ir = 8}, /* PCIe RP4 */ + {.devfn = DEVFN(0x0f, 0), .ir = 8}, /* PCIe RP5 */ + {.devfn = DEVFN(0x10, 0), .ir = 8}, /* PCIe RP6 */ + {.devfn = DEVFN(0x11, 0), .ir = 8}, /* PCIe RP7 */ + {.devfn = DEVFN(0x12, 0), .ir = 10}, /* SMBus - Host */ + {.devfn = DEVFN(0x13, 0), .ir = 6}, /* AHCI0 */ + {.devfn = DEVFN(0x14, 0), .ir = 11}, /* AHCI1 */ + {.devfn = DEVFN(0x15, 0), .ir = 9}, /* USB */ + {.devfn = DEVFN(0x16, 0), .ir = 1}, /* Virtual RP to LAN0 */ + {.devfn = DEVFN(0x17, 0), .ir = 2}, /* Virtual RP to LAN1 */ + {.devfn = DEVFN(0x18, 0), .ir = 5}, /* ME HECI1 */ + {.devfn = DEVFN(0x18, 1), .ir = 5}, /* ME HECI1 */ + {.devfn = DEVFN(0x18, 2), .ir = 5}, /* ME PTIO-IDER */ + {.devfn = DEVFN(0x18, 3), .ir = 5}, /* ME PTIO-KT */ + {.devfn = DEVFN(0x18, 4), .ir = 5}, /* ME HECI3 */ + {.devfn = DEVFN(0x1a, 0), .ir = 10}, /* HSUART0 */ + {.devfn = DEVFN(0x1a, 1), .ir = 10}, /* HSUART1 */ + {.devfn = DEVFN(0x1a, 2), .ir = 10}, /* HSUART2 */ + {.devfn = DEVFN(0x1b, 0), .ir = 12}, /* IE HECI1 */ + {.devfn = DEVFN(0x1b, 1), .ir = 12}, /* IE HECI1 */ + {.devfn = DEVFN(0x1b, 2), .ir = 12}, /* IE PTIO-IDER */ + {.devfn = DEVFN(0x1b, 3), .ir = 12}, /* IE PTIO-KT */ + {.devfn = DEVFN(0x1b, 4), .ir = 12}, /* IE HECI3 */ + {.devfn = DEVFN(0x1c, 0), .ir = 12}, /* SDHCI */ + {.devfn = DEVFN(0x1f, 0), .ir = 0}, /* LPC */ + {.devfn = DEVFN(0x1f, 1), .ir = 0}, /* PS2B */ + {.devfn = DEVFN(0x1f, 4), .ir = 0}, /* SMBus - Legacy */ + {.devfn = DEVFN(0x1f, 7), .ir = 0}, /* Trace Hub */ +}; + +/* + * Only 6 of the 8 root ports have swizzling, return '1' if this bdf is one of + * them, '0' otherwise + */ +static int is_dnv_swizzled_rp(uint16_t bdf) +{ + switch (bdf) { + case DEVFN(10, 0): + case DEVFN(11, 0): + case DEVFN(12, 0): + case DEVFN(15, 0): + case DEVFN(16, 0): + case DEVFN(17, 0): + return 1; + } + + return 0; +} + +/* + * Figure out which upstream interrupt pin a downstream device gets swizzled to + * + * config - pointer to chip_info containing routing info + * devfn - device/function of root port to check swizzling for + * pin - interrupt pin 1-4 = A-D + * + * Return new pin mapping, 0 if invalid pin + */ +static int dnv_get_swizzled_pin(config_t *config, u8 devfn, u8 pin) +{ + if (pin < 1 || pin > 4) + return 0; + + devfn >>= 3; + if (devfn < 13) + devfn -= 9; + else + devfn -= 14; + + return ((pin - 1 + devfn) % 4) + 1; +} + +/* + * Figure out which upstream interrupt pin a downstream device gets swizzled to + * + * config - pointer to chip_info containing routing info + * devfn - device/function of root port to check swizzling for + * pin - interrupt pin 1-4 = A-D + * + * Return new pin mapping, 0 if invalid pin + */ +static int dnv_get_ir(config_t *config, u8 devfn, u8 pin) +{ + int i = 0; + int line = 0xff; + u16 ir = 0xffff; + + /* The only valid pin values are 1-4 for A-D */ + if (pin < 1 || pin > 4) { + printk(BIOS_WARNING, "%s: pin %d is invalid\n", __func__, pin); + goto dnv_get_ir_done; + } + + for (i = 0; i < ARRAY_SIZE(dnv_ir_lut); i++) { + if (dnv_ir_lut[i].devfn == devfn) + break; + } + + if (i == ARRAY_SIZE(dnv_ir_lut)) { + printk(BIOS_WARNING, "%s: no entry\n", __func__); + goto dnv_get_ir_done; + } + + switch (dnv_ir_lut[i].ir) { + case 0: + ir = config->ir00_routing; + break; + case 1: + ir = config->ir01_routing; + break; + case 2: + ir = config->ir02_routing; + break; + case 3: + ir = config->ir03_routing; + break; + case 4: + ir = config->ir04_routing; + break; + case 5: + ir = config->ir05_routing; + break; + case 6: + ir = config->ir06_routing; + break; + case 7: + ir = config->ir07_routing; + break; + case 8: + ir = config->ir08_routing; + break; + case 9: + ir = config->ir09_routing; + break; + case 10: + ir = config->ir10_routing; + break; + case 11: + ir = config->ir11_routing; + break; + case 12: + ir = config->ir12_routing; + break; + default: + printk(BIOS_ERR, "%s: invalid ir %d for entry %d\n", __func__, dnv_ir_lut[i].ir, + i); + goto dnv_get_ir_done; + } + + ir >>= (pin - 1) * 4; + ir &= 0xf; + switch (ir) { + case 0: + line = config->pirqa_routing; + break; + case 1: + line = config->pirqb_routing; + break; + case 2: + line = config->pirqc_routing; + break; + case 3: + line = config->pirqd_routing; + break; + case 4: + line = config->pirqe_routing; + break; + case 5: + line = config->pirqf_routing; + break; + case 6: + line = config->pirqg_routing; + break; + case 7: + line = config->pirqh_routing; + break; + default: + printk(BIOS_ERR, "%s: invalid ir pirq %d for entry %d\n", __func__, ir, i); + break; + } + +dnv_get_ir_done: + return line; +} + +/* + * PCI devices have the INT_LINE (0x3C) and INT_PIN (0x3D) registers which + * report interrupt routing information to operating systems and drivers. The + * INT_PIN register is generally read only and reports which interrupt pin + * A - D it uses. The INT_LINE register is configurable and reports which IRQ + * (generally the PIC IRQs 1 - 15) it will use. This needs to take interrupt + * pin swizzling on devices that are downstream on a PCI bridge into account. + */ +static u8 dnv_get_int_line(struct device *irq_dev) +{ + config_t *config; + struct device *targ_dev = NULL; + uint16_t parent_bdf = 0; + int8_t original_int_pin = 0, new_int_pin = 0, swiz_int_pin = 0; + uint8_t int_line = 0xff; + + if (irq_dev->path.type != DEVICE_PATH_PCI || !irq_dev->enabled) { + printk(BIOS_ERR, "%s for non pci device?\n", __func__); + goto dnv_get_int_line_done; + } + + /* + * Get the INT_PIN swizzled up to the root port if necessary + * using the existing coreboot pci_device code + */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + goto dnv_get_int_line_done; + + printk(BIOS_DEBUG, "%s: irq_dev %s, targ_dev %s:\n", __func__, dev_path(irq_dev), + dev_path(targ_dev)); + printk(BIOS_DEBUG, "%s: std swizzle %s from %c to %c\n", __func__, dev_path(targ_dev), + '@' + original_int_pin, '@' + new_int_pin); + + /* Swizzle this device if needed */ + config = targ_dev->chip_info; + parent_bdf = targ_dev->path.pci.devfn | targ_dev->bus->secondary << 8; + if (is_dnv_swizzled_rp(parent_bdf) && irq_dev != targ_dev) { + swiz_int_pin = dnv_get_swizzled_pin(config, parent_bdf, new_int_pin); + printk(BIOS_DEBUG, "%s: dnv swizzle %s from %c to %c\n", __func__, + dev_path(targ_dev), '@' + new_int_pin, '@' + swiz_int_pin); + } else { + swiz_int_pin = new_int_pin; + } + + /* Look up the routing for the pin */ + int_line = dnv_get_ir(config, parent_bdf, swiz_int_pin); + +dnv_get_int_line_done: + printk(BIOS_DEBUG, "\tINT_LINE\t\t: %d\n", int_line); + return int_line; +} + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -150,6 +405,7 @@ config->ipc3); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + int devfn = irq_dev->path.pci.devfn; u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) @@ -157,23 +413,9 @@ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; - case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; - case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; - case 4: /* INTD# */ - int_line = config->pirqd_routing; - break; - } - - if (!int_line) - continue; + int_line = dnv_get_int_line(irq_dev); + printk(BIOS_DEBUG, "%s: %02x:%02x.%d pin %d int line %d\n", __func__, + irq_dev->bus->secondary, devfn >> 3, devfn & 0x7, int_pin, int_line); pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434 Gerrit-Change-Number: 34714 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Add ACPI _PRT methods for virtual root ports
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34713 ) Change subject: soc/intel/dnv: Add ACPI _PRT methods for virtual root ports ...................................................................... soc/intel/dnv: Add ACPI _PRT methods for virtual root ports This eliminates Linux kernel warnings that look like: pcieport 0000:00:17.0: can't derive routing for PCI INT B ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10 Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/acpi/pcie.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/34713/1 diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index f212557..14c55d8 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -168,4 +168,9 @@ // Virtual root port 2 Device (VRP2) { Name (_ADR, 0x00060000) + + Method (_PRT) + { + Return (IRQM (6)) + } } diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index c9bbd3f..bc47b77 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -118,7 +118,52 @@ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKG, 0 } }) + /* Interrupt Map INTA->INTC, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQIA, Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQIP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQJA, Package() { + Package() { 0x0000ffff, 0, 0, 23 }, + Package() { 0x0000ffff, 1, 0, 20 }, + Package() { 0x0000ffff, 2, 0, 21 }, + Package() { 0x0000ffff, 3, 0, 22 } }) + Name (IQJP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + + /* Interrupt Map INTA->INTB, INTB->INTB, INTC->INTC, INTD->INTD */ + Name (IQKA, Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) + Name (IQKP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + Switch (ToInteger (Arg0)) { + /* Virtual Root Port 2 - QAT */ + Case (Package() { 6 }) { + If (PICM) { + Return (IQIA) + } Else { + Return (IQIP) + } + } + /* PCIe Root Port 1 */ Case (Package() { 9 }) { If (PICM) { @@ -191,6 +236,24 @@ } } + /* Virtual Root Port 0 - LAN 0 */ + Case (Package() { 22 }) { + If (PICM) { + Return (IQJA) + } Else { + Return (IQJP) + } + } + + /* Virtual Root Port 1 - LAN 1 */ + Case (Package() { 23 }) { + If (PICM) { + Return (IQKA) + } Else { + Return (IQKP) + } + } + Default { If (PICM) { Return (IQDA) diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index bcc8a5c..674f043 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -62,11 +62,21 @@ // Virtual root port 0 Device (VRP0) { Name (_ADR, 0x00160000) + + Method (_PRT) + { + Return (IRQM (22)) + } } // Virtual root port 1 Device (VRP1) { Name (_ADR, 0x00170000) + + Method (_PRT) + { + Return (IRQM (23)) + } } // ME HECI -- To view, visit https://review.coreboot.org/c/coreboot/+/34713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d Gerrit-Change-Number: 34713 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
by Stephen Douthit (Code Review) 10 Mar '20

10 Mar '20

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34712 ) Change subject: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing ...................................................................... soc/intel/dnv: Fix ACPI reporting of root port interrupt routing pcie_port.asl defines an IRQM method that looks up legacy interrupt swizzling based on incoming interrupt "pin" A-D and root port number. Unfortunately the 8-bit root port number stored at offset 0x4F in the config space matches the device number, not the 1-8 scheme used in the LUT reported to the OS. Fix the case values to match the hardware. Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/soc/intel/denverton_ns/acpi/pcie.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/34712/1 diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index cb14cf8..c9bbd3f 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -120,7 +120,7 @@ Switch (ToInteger (Arg0)) { /* PCIe Root Port 1 */ - Case (Package() { 1 }) { + Case (Package() { 9 }) { If (PICM) { Return (IQAA) } Else { @@ -129,7 +129,7 @@ } /* PCIe Root Port 2 */ - Case (Package() { 2 }) { + Case (Package() { 10 }) { If (PICM) { Return (IQBA) } Else { @@ -138,7 +138,7 @@ } /* PCIe Root Port 3 */ - Case (Package() { 3 }) { + Case (Package() { 11 }) { If (PICM) { Return (IQCA) } Else { @@ -147,7 +147,7 @@ } /* PCIe Root Port 4 */ - Case (Package() { 4 }) { + Case (Package() { 12 }) { If (PICM) { Return (IQDA) } Else { @@ -156,7 +156,7 @@ } /* PCIe Root Port 5 */ - Case (Package() { 5 }) { + Case (Package() { 14 }) { If (PICM) { Return (IQEA) } Else { @@ -165,7 +165,7 @@ } /* PCIe Root Port 6 */ - Case (Package() { 6 }) { + Case (Package() { 15 }) { If (PICM) { Return (IQFA) } Else { @@ -174,7 +174,7 @@ } /* PCIe Root Port 7 */ - Case (Package() { 7 }) { + Case (Package() { 16 }) { If (PICM) { Return (IQGA) } Else { @@ -183,7 +183,7 @@ } /* PCIe Root Port 8 */ - Case (Package() { 8 }) { + Case (Package() { 17 }) { If (PICM) { Return (IQHA) } Else { -- To view, visit https://review.coreboot.org/c/coreboot/+/34712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Gerrit-Change-Number: 34712 Gerrit-PatchSet: 1 Gerrit-Owner: Stephen Douthit <stephend(a)silicom-usa.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Fix shift error
by Patrick Georgi (Code Review) 10 Mar '20

10 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23362 ) Change subject: nb/intel/sandybridge: Fix shift error ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/23362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0a2b3645e5ecdbd685efdc948c65544a35075 Gerrit-Change-Number: 23362 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Mar 2020 20:43:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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