coreboot-gerrit March 2020

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Change in ...coreboot[master]: inteltool: add support for CannonPoint-LP
by Matt DeVillier (Code Review) 14 Mar '20

14 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33411 Change subject: inteltool: add support for CannonPoint-LP ...................................................................... inteltool: add support for CannonPoint-LP Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from Intel 300 Series Chipset Family On-Package Platform Controller Hub, Datasheet volume 1 of 2, document #337867-002 Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ic3593ffe7d997261e9b7189ec4083cf75aaf3cf9 --- M util/inteltool/Makefile M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c M util/inteltool/platform.h A util/inteltool/platform_cannonlake_lp.c 8 files changed, 373 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/33411/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index c71c711..0ee1991 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,8 @@ CPPFLAGS += -I$(top)/src/commonlib/include PLATFORMS = platform_sunrise.o platform_apollolake.o platform_cannonlake.o \ - platform_denverton.o platform_lynxpoint.o platform_i631x.o + platform_cannonlake_lp.o platform_denverton.o \ + platform_lynxpoint.o platform_i631x.o OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 670ecf3..e9a919f 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -345,6 +345,7 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 27df34b..f3743bf 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -129,6 +129,12 @@ communities = apl_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: + community_count = cannonlake_pch_lp_communities_count; + communities = cannonlake_pch_lp_communities; + pad_stepping = 16; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 7e02510..f1a4c76 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -137,6 +137,10 @@ "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1, + "8th generation (Coffee Lake family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2, + "8th generation (Whiskey Lake family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -246,6 +250,8 @@ "Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM, "Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM, + "Cannon Point-LP U Premium/CoffeeLake/Whiskeylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 483c930..e26c229 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -155,6 +155,7 @@ #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b +#define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -276,6 +277,8 @@ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1 0x3ed0 /* Coffeelake (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2 0x3e34 /* Whiskeylake (Mobile) */ /* Intel GPUs */ diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index c969620..9323362 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -119,6 +119,7 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: sbbar_phys = 0xfd000000; use_p2sb = false; break; diff --git a/util/inteltool/platform.h b/util/inteltool/platform.h index d5fa8e6..8fd674b 100644 --- a/util/inteltool/platform.h +++ b/util/inteltool/platform.h @@ -25,6 +25,9 @@ extern const struct gpio_community *const cannonlake_pch_h_communities[]; size_t cannonlake_pch_h_communities_count; +extern const struct gpio_community *const cannonlake_pch_lp_communities[]; +size_t cannonlake_pch_lp_communities_count; + extern const struct gpio_community *const denverton_communities[]; size_t denverton_communities_count; diff --git a/util/inteltool/platform_cannonlake_lp.c b/util/inteltool/platform_cannonlake_lp.c new file mode 100644 index 0000000..b3a2eaf --- /dev/null +++ b/util/inteltool/platform_cannonlake_lp.c @@ -0,0 +1,351 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2019 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "inteltool.h" +#include "gpio.h" +#include "platform.h" + +const char *const cannonlake_pch_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "TIME_SYNC1", "n/a", + "GPP_A1", "LAD0", "ESPI_IO0", "n/a", + "GPP_A2", "LAD1", "ESPI_IO1", "n/a", + "GPP_A3", "LAD2", "ESPI_IO2", "n/a", + "GPP_A4", "LAD3", "ESPI_IO3", "n/a", + "GPP_A5", "LFRAME#", "ESPI_CS0#", "n/a", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "GSPI0_CS1#", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "ESPI_CLK", "n/a", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "GSPI1_CS1#", "SD_VDD2_PWR_EN#", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "ESPI_RESET#", "n/a", + "GPP_A15", "SUSACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_a_names, +}; + +const char *const cannonlake_pch_lp_group_b_names[] = { + "GPP_B0", "Reserved", "n/a", + "GPP_B1", "Reserved", "n/a", + "GPP_B2", "VRALERT#", "n/a", + "GPP_B3", "CPU_GP2", "n/a", + "GPP_B4", "CPU_GP3", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", + "GPP_B12", "SLP_S0#", "n/a", + "GPP_B13", "PLTRST#", "n/a", + "GPP_B14", "SPKR", "n/a", + "GPP_B15", "GSPI0_CS0#", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", +}; + +const struct gpio_group cannonlake_pch_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_b_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_b_names, +}; + +const char *const cannonlake_pch_lp_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0_RXD", "n/a", + "GPP_C9", "UART0_TXD", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_c_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_c_names, +}; + +const char *const cannonlake_pch_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "BK0", "SBK0", + "GPP_D1", "SPI1_CLK", "BK1", "SBK1", + "GPP_D2", "SPI1_MISO", "BK2", "SBK2", + "GPP_D3", "SPI1_MOSI", "BK3", "SBK3", + "GPP_D4", "IMGCLKOUT0", "BK4", "SBK4", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "SML0BDATA", "I2C4B_SDA", + "GPP_D14", "ISH_UART0_TXD", "SML0BCLK", "I2C4B_SCL", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "SML0BALERT", "n/a", + "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", + "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", + "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", + "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_d_names, +}; + +const char *const cannonlake_pch_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "n/a", "n/a", + "GPP_E2", "SATAXPCIE2", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "DISP_MISC0", "n/a", + "GPP_E14", "DDPC_HPD1", "DISP_MISC1", "n/a", + "GPP_E15", "DDPD_HPD2", "DISP_MISC2", "n/a", + "GPP_E16", "n/a", "DISP_MISC3", "n/a", + "GPP_E17", "EDP_HPD", "DISP_MISC4", "n/a", + "GPP_E18", "DPPB_CTRLCLK", "n/a", "CNV_BT_HOST_WAKE#", + "GPP_E19", "DPPB_CTRLDATA", "n/a", "CNV_BT_IF_SELECT", + "GPP_E20", "DPPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DPPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "DPPD_CTRLCLK", "n/a", "n/a", + "GPP_E23", "DPPD_CTRLDATA", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_e_names, +}; + +const char *const cannonlake_pch_lp_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", + "GPP_F13", "SATA_SDATAOUT0", "n/a", + "GPP_F14", "n/a", "PS_ON#", + "GPP_F15", "USB2_OC4#", "n/a", + "GPP_F16", "USB2_OC5#", "n/a", + "GPP_F17", "USB2_OC6#", "n/a", + "GPP_F18", "USB2_OC7#", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", + "GPP_F22", "DDPF_CTRLCLK", "n/a", + "GPP_F23", "DDPF_CTRLDATA", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_f_names) / 3, + .func_count = 3, + .pad_names = cannonlake_pch_lp_group_f_names, +}; + +const char *const cannonlake_pch_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", + "GPP_G1", "SD_DATA0", + "GPP_G2", "SD_DATA1", + "GPP_G3", "SD_DATA2", + "GPP_G4", "SD_DATA3", + "GPP_G5", "SD3_CD#", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +const struct gpio_group cannonlake_pch_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_g_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_g_names, +}; + +const char *const cannonlake_pch_lp_group_h_names[] = { + "GPP_H0", "I2S2_SCLK", "CNV_BT_I2S_SCLK", "n/a", + "GPP_H1", "I2S2_SFRM", "CNV_BT_I2S_BCLK", "CNV_RF_RESET#", + "GPP_H2", "I2S2_TXD", "CNV_BT_I2S_SDI", "MODEM_CLKREQ", + "GPP_H3", "I2S2_RXD", "CNV_BT_I2S_SDO", "n/a", + "GPP_H4", "I2C2_SDA", "n/a", "n/a", + "GPP_H5", "I2C2_SCL", "n/a", "n/a", + "GPP_H6", "I2C3_SDA", "n/a", "n/a", + "GPP_H7", "I2C3_SCL", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "n/a", "n/a", + "GPP_H9", "I2C4_SCL", "n/a", "n/a", + "GPP_H10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_H11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_H12", "M2_SKT2_CFG0", "n/a", "n/a", + "GPP_H13", "M2_SKT2_CFG1", "n/a", "n/a", + "GPP_H14", "M2_SKT2_CFG2", "n/a", "n/a", + "GPP_H15", "M2_SKT2_CFG3", "n/a", "n/a", + "GPP_H16", "n/a", "n/a", "n/a", + "GPP_H17", "n/a", "n/a", "n/a", + "GPP_H18", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_H19", "TIME_SYNC0", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", + "GPP_H21", "n/a", "n/a", "n/a", + "GPP_H22", "n/a", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group cannonlake_pch_lp_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_h_names) / 4, + .func_count = 4, + .pad_names = cannonlake_pch_lp_group_h_names, +}; + +const char *const cannonlake_pch_lp_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +}; +const struct gpio_group cannonlake_pch_lp_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(cannonlake_pch_lp_group_gpd_names) / 2, + .func_count = 2, + .pad_names = cannonlake_pch_lp_group_gpd_names, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_0_groups[] = { + &cannonlake_pch_lp_group_a, + &cannonlake_pch_lp_group_b, + &cannonlake_pch_lp_group_g, +}; +const struct gpio_community cannonlake_pch_lp_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_0_groups), + .groups = cannonlake_pch_lp_community_0_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_1_groups[] = { + &cannonlake_pch_lp_group_d, + &cannonlake_pch_lp_group_f, + &cannonlake_pch_lp_group_h, +}; +const struct gpio_community cannonlake_pch_lp_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_1_groups), + .groups = cannonlake_pch_lp_community_1_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_2_groups[] = { + &cannonlake_pch_lp_group_gpd, +}; + +const struct gpio_community cannonlake_pch_lp_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_2_groups), + .groups = cannonlake_pch_lp_community_2_groups, +}; + +const struct gpio_group *const cannonlake_pch_lp_community_4_groups[] = { + &cannonlake_pch_lp_group_c, + &cannonlake_pch_lp_group_e, +}; + +const struct gpio_community cannonlake_pch_lp_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(cannonlake_pch_lp_community_4_groups), + .groups = cannonlake_pch_lp_community_4_groups, +}; + +const struct gpio_community *const cannonlake_pch_lp_communities[] = { + &cannonlake_pch_lp_community_0, + &cannonlake_pch_lp_community_1, + &cannonlake_pch_lp_community_2, + &cannonlake_pch_lp_community_4, +}; + +size_t cannonlake_pch_lp_communities_count = ARRAY_SIZE(cannonlake_pch_lp_communities); -- To view, visit https://review.coreboot.org/c/coreboot/+/33411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3593ffe7d997261e9b7189ec4083cf75aaf3cf9 Gerrit-Change-Number: 33411 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: WIP: inteltool: Add option to output GPIOs as coreboot macros
by Matt DeVillier (Code Review) 14 Mar '20

14 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39392 ) Change subject: WIP: inteltool: Add option to output GPIOs as coreboot macros ...................................................................... WIP: inteltool: Add option to output GPIOs as coreboot macros based on Nico's work in CB:25145, but updated to use current macros found in gpio_defs.h in soc/intel/common. Avoids use of "legacy" macros which are only applicable to Skylake/Kabylake. Test: Generate reasonably sane list of macros for out-of-tree Whiskeylake-based device. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: If2a873eb3666c952213790ee8624ce9a89a868fb --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 4 files changed, 212 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/39392/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index d40ed32..5646c87 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -374,7 +374,7 @@ case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: - print_gpio_groups(sb); + print_gpio_groups(sb, false); return 0; case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index ed991cc..c762f35 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -44,13 +44,185 @@ return "RESERVED"; } +static const char *decode_table_gpio_term(const size_t term) +{ + switch (term) { + case 0: return "NONE"; + case 2: return "DN_5K"; + case 4: return "DN_20K"; + case 9: return "UP_1K"; + case 10: return "UP_5K"; + case 11: return "UP_2K"; + case 12: return "UP_20K"; + case 13: return "UP_667"; + case 15: return "NATIVE"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_reset(const size_t reset) +{ + switch (reset) { + case 0: return "PWROK"; + case 1: return "DEEP"; + case 2: return "PLTRST"; + case 3: return "RSMRST"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_nf(const size_t pad_mode) +{ + switch (pad_mode) { + case 0: return "GPIO"; + case 1: return "NF1"; + case 2: return "NF2"; + case 3: return "NF3"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_trig(const size_t trig_mode) +{ + switch (trig_mode) { + case 0: return "LEVEL"; + case 1: return "EDGE_SINGLE"; + case 2: return "OFF"; + case 3: return "EDGE_BOTH"; + default: return "UNSUPPORTED"; + } +} + +static int print_table_gpio(const struct gpio_group *const group, + const size_t pad, + const uint32_t dw0, const uint32_t dw1) +{ + const size_t tx_state = dw0 >> 0 & 1; + const size_t tx_disable = dw0 >> 8 & 1; + const size_t rx_disable = dw0 >> 9 & 1; + const size_t pad_mode = dw0 >> 10 & 3; + const size_t int_route = dw0 >> 17 & 0x0f; + const size_t rx_invert = dw0 >> 23 & 1; + const size_t rx_evcfg = dw0 >> 25 & 3; + const size_t rx_raw1 = dw0 >> 28 & 1; + const size_t rx_padsel = dw0 >> 29 & 1; + const size_t pad_reset = dw0 >> 30 & 3; + const size_t term = dw1 >> 10 & 0x0f; + const size_t pad_tol = dw1 >> 25 & 0x01; + const size_t driver = dw1 >> 4 & 1; + + const char *const pad_name = group->pad_names[pad * group->func_count]; + + if (rx_padsel || rx_raw1) + return -1; + + if (pad_mode) { + printf("PAD_CFG_NF%s(%s, %s, %s, %s),\n", + pad_tol ? "_1V8" : "", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_nf(pad_mode)); + } else if (!tx_disable) { + if (!rx_disable) { + fprintf(stderr, "WARNING: %s has both TX and RX enabled" + ", disabling RX!\n", pad_name); + } + if (term) { + printf("PAD_CFG_TERM_GPO(%s, %zu, %s, %s),\n", + pad_name, tx_state, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPO(%s, %zu, %s),\n", + pad_name, tx_state, + decode_table_gpio_reset(pad_reset)); + } + } else if (!rx_disable && tx_disable) { + switch (int_route) { + case 0x0: + if (rx_invert || rx_evcfg > 1) + return -1; + if (driver) { + printf("PAD_CFG_GPI_GPIO_DRIVER(%s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else if (rx_evcfg & ~0x04) { + printf("PAD_CFG_GPI(%s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPI_INT(%s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + } + break; + case 0x1: + return -1; + case 0x2: + if (rx_evcfg == 1) { + printf("PAD_CFG_GPI_SMI_" + "%s(%s, %s, %s, %s),\n", + rx_invert ? "LOW" : "HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + } else { + return -1; + } + break; + case 0x4: + if (rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI_SCI_%s(%s, %s, %s, %s),\n", + rx_invert ? "LOW" : "HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + break; + case 0x8: + if (rx_evcfg > 1) + return -1; + if (rx_evcfg && !rx_invert) { + printf("PAD_CFG_GPI_APIC(%s, %s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg), + rx_invert ? "INVERT" : "NONE"); + } else { + printf("PAD_CFG_GPI_APIC%s%s(%s, %s, %s),\n", + rx_evcfg ? "_EDGE" : "", + rx_invert ? "_LOW" : "_HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } + break; + default: + return -1; + } + } else { + printf("PAD_NC(%s, %s),\n", pad_name, decode_table_gpio_term(term)); + } + return 0; +} + static void print_gpio_group(const uint8_t pid, size_t pad_cfg, const struct gpio_group *const group, - size_t pad_stepping) + size_t pad_stepping, const bool use_macros) { size_t p; - printf("%s\n", group->display); + if (use_macros) + printf("\n/* %s */\n\n", group->display); + else + printf("%s\n", group->display); for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) { const uint32_t dw0 = read_pcr32(pid, pad_cfg); @@ -58,21 +230,31 @@ const char *const pad_name = group->pad_names[p * group->func_count]; - printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, - (uint64_t)dw1 << 32 | dw0, - pad_name[0] == '*' ? &pad_name[1] : pad_name, - decode_pad_mode(group, p, dw0)); + if (use_macros) { + printf("/* %-8s %-20s */\t", + group->pad_names[p * group->func_count], + decode_pad_mode(group, p, dw0)); + + if (print_table_gpio(group, p, dw0, dw1)) + printf("PAD_CFG_UNSUPPORTED,\n"); + } else { + printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, + (uint64_t)dw1 << 32 | dw0, + pad_name[0] == '*' ? &pad_name[1] : pad_name, + decode_pad_mode(group, p, dw0)); + } } } static void print_gpio_community(const struct gpio_community *const community, - size_t pad_stepping) + size_t pad_stepping, const bool use_macros) { size_t group, pad_count; size_t pad_cfg; /* offset in bytes under this communities PCR port */ - printf("%s\n\nPCR Port ID: 0x%06zx\n\n", - community->name, (size_t)community->pcr_port_id << 16); + if (!use_macros) + printf("%s\n\nPCR Port ID: 0x%06zx\n\n", + community->name, (size_t)community->pcr_port_id << 16); for (group = 0, pad_count = 0; group < community->group_count; ++group) pad_count += community->groups[group]->pad_count; @@ -87,12 +269,12 @@ for (group = 0; group < community->group_count; ++group) { print_gpio_group(community->pcr_port_id, pad_cfg, community->groups[group], - pad_stepping); + pad_stepping, use_macros); pad_cfg += community->groups[group]->pad_count * pad_stepping; } } -void print_gpio_groups(struct pci_dev *const sb) +void print_gpio_groups(struct pci_dev *const sb, const bool use_macros) { size_t community_count; const struct gpio_community *const *communities; @@ -189,5 +371,5 @@ printf("\n============= GPIOS =============\n\n"); for (; community_count; --community_count) - print_gpio_community(*communities++, pad_stepping); + print_gpio_community(*communities++, pad_stepping, use_macros); } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 555aa2f..bd0e5e9 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -490,7 +490,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrpmedPMaAsfSRxC]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -510,6 +510,7 @@ " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" " -a | --all: dump all known (safe) registers\n" + " -C | --macros: dump GPIOs in coreboot macro format\n" " --pcr=PORT_ID: dump all registers of a PCR port\n" " (may be specified max %d times)\n" "\n", MAX_PCR_PORTS); @@ -570,7 +571,7 @@ int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; - int show_gpio_diffs = 0; + int show_gpio_diffs = 0, use_gpio_macros = 0; size_t pcr_count = 0; uint8_t dump_pcr[MAX_PCR_PORTS]; @@ -593,11 +594,12 @@ {"gfx", 0, 0, 'f'}, {"ahci", 0, 0, 'R'}, {"sgx", 0, 0, 'x'}, + {"macros", 0, 0, 'C'}, {"pcr", required_argument, 0, LONG_OPT_PCR}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRCS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -665,6 +667,10 @@ case 'x': dump_sgx = 1; break; + case 'C': + dump_gpios = 1; + use_gpio_macros = 1; + break; case LONG_OPT_PCR: if (pcr_count < MAX_PCR_PORTS) { errno = 0; @@ -795,8 +801,12 @@ /* Now do the deed */ if (dump_gpios) { - print_gpios(sb, 1, show_gpio_diffs); - printf("\n\n"); + if (use_gpio_macros) { + print_gpio_groups(sb, use_gpio_macros); + } else { + print_gpios(sb, 1, show_gpio_diffs); + printf("\n\n"); + } } else if (show_gpio_diffs) { print_gpios(sb, 0, show_gpio_diffs); printf("\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 169d590..0a924ba 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -19,6 +19,7 @@ #include <commonlib/helpers.h> +#include <stdbool.h> #include <stdint.h> #if defined(__GLIBC__) @@ -396,7 +397,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); -void print_gpio_groups(struct pci_dev *sb); +void print_gpio_groups(struct pci_dev *sb, bool use_macros); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); -- To view, visit https://review.coreboot.org/c/coreboot/+/39392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2a873eb3666c952213790ee8624ce9a89a868fb Gerrit-Change-Number: 39392 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [WIP] mainboard: Add Acer ES1-572
by Michael Niewöhner (Code Review) 14 Mar '20

14 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mainboard: Add Acer ES1-572 ...................................................................... Patch Set 5: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig File acer_a_thing.defconfig: https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig@2 PS5, Line 2: CONFIG_VENDOR_ACER=y move file to configs/ -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Sun, 15 Mar 2020 00:49:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: coreboot: add Volteer template files
by Nick Vaccaro (Code Review) 14 Mar '20

14 Mar '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39462 ) Change subject: coreboot: add Volteer template files ...................................................................... coreboot: add Volteer template files Add template files for making a new barebones-copy of Volteer. Also move the coreboot scripts according to CLs that landed after this branch was created. BUG=b:147483699 BRANCH=None TEST=N/A Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A util/mainboard/google/create_coreboot_variant.sh A util/mainboard/google/kconfig.py M util/mainboard/google/volteer/template/Makefile.inc A util/mainboard/google/volteer/template/include/variant/ec.h A util/mainboard/google/volteer/template/include/variant/gpio.h A util/mainboard/google/volteer/template/overridetree.cb 6 files changed, 283 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/39462/1 diff --git a/util/mainboard/google/create_coreboot_variant.sh b/util/mainboard/google/create_coreboot_variant.sh new file mode 100755 index 0000000..245bc1f --- /dev/null +++ b/util/mainboard/google/create_coreboot_variant.sh @@ -0,0 +1,86 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# Copyright 2020 Google LLC. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +VERSION="1.0.2" +SCRIPT=$(basename -- "${0}") + +export LC_ALL=C + +if [[ "$#" -lt 2 ]]; then + echo "Usage: ${SCRIPT} base_name variant_name [bug_number]" + echo "e.g. ${SCRIPT} hatch kohaku b:140261109" + echo "* Adds a new variant of the baseboard to Kconfig and Kconfig.name" + echo "* Copies the template files for the baseboard to the new variant" + exit 1 +fi + +# This is the name of the base board that we're using to make the variant. +# ${var,,} converts to all lowercase. +BASE="${1,,}" +# This is the name of the variant that is being cloned. +# ${var,,} converts to all lowercase; ${var^^} is all uppercase. +VARIANT="${2,,}" +VARIANT_UPPER="${VARIANT^^}" + +# Assign BUG= text, or "None" if that parameter was not specified. +BUG=${3:-None} + +# This script lives in util/mainboard/google +# The template files are in util/mainboard/google/${BASE}/templates +# We need to create files in src/mainboard/google/${BASE}/variants/${VARIANT} +pushd "${BASH_SOURCE%/*}" || exit 1 +SRC=$(pwd) +popd || exit 1 +pushd "${SRC}/../../../src/mainboard/google/${BASE}" || { + echo "The baseboard directory for ${BASE} does not exist."; + exit 1; } + +# Make sure the variant doesn't already exist. +if [[ -e variants/${VARIANT} ]]; then + echo "variants/${VARIANT} already exists." + echo "Have you already created this variant?" + exit 1 +fi + +# Start a branch. Use YMD timestamp to avoid collisions. +DATE=$(date +%Y%m%d) +git checkout -b "coreboot_${VARIANT}_${DATE}" || exit 1 + +# Copy the template tree to the target. +mkdir -p "variants/${VARIANT}/" +cp -pr "${SRC}/${BASE}/template/." "variants/${VARIANT}/" +git add "variants/${VARIANT}/" + +# Now add the new variant to Kconfig and Kconfig.name +# These files are in the current directory, e.g. src/mainboard/google/hatch +"${SRC}/kconfig.py" --board "${BASE}" --variant "${VARIANT}" || exit 1 + +mv Kconfig.new Kconfig +mv Kconfig.name.new Kconfig.name + +git add Kconfig Kconfig.name + +# Now commit the files. +git commit -sm "${BASE}: Create ${VARIANT} variant + +Create the ${VARIANT} variant of the ${BASE} baseboard by +copying the baseboard template files to a new directory +named for the variant. + +(Auto-Generated by ${SCRIPT} version ${VERSION}). + +BUG=${BUG} +TEST=util/abuild/abuild -p none -t google/${BASE} -x -a +make sure the build includes GOOGLE_${VARIANT_UPPER}" diff --git a/util/mainboard/google/kconfig.py b/util/mainboard/google/kconfig.py new file mode 100755 index 0000000..6f9fccf --- /dev/null +++ b/util/mainboard/google/kconfig.py @@ -0,0 +1,135 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +"""Add a new variant to the Kconfig and Kconfig.name for the baseboard + +To start a new variant of an existing baseboard, we need to add +the variant into the Kconfig and Kconfig.name files for the +baseboard. In Kconfig, we have two sections that need additional +entries, MAINBOARD_PART_NUMBER and VARIANT_DIR. + +The MAINBOARD_PART_NUMBER and VARIANT_DIR just use various +capitalizations of the variant name to create the strings. + +Kconfig.name adds an entire section for the new variant, and all +of these use various capitalizations of the variant name. The strings +in this section are SOC-specific, so we'll need versions for each +SOC that we support. + +Copyright 2019 Google LLC. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; version 2 of the License. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. +""" + +from __future__ import print_function +import argparse +import sys + + +def main(): + parser = argparse.ArgumentParser( + description='Add strings to coreboot Kconfig for a new board variant') + parser.add_argument('--board', type=str, required=True, + help='Name of the baseboard') + parser.add_argument('--variant', type=str, required=True, + help='Name of the board variant') + args = parser.parse_args() + + if args.board not in ['hatch', 'volteer']: + print('Unsupported baseboard "' + args.board + '"') + sys.exit(1) + + add_to_Kconfig(args.variant) + add_to_Kconfig_name(args.board, args.variant) + + +def add_to_Kconfig(variant_name): + """Add options for the variant to the Kconfig + + Open the Kconfig file and read it line-by-line. When we detect that we're + in one of the sections of interest, wait until we get a blank line + (signalling the end of that section), and then add our new line before + the blank line. The updated lines are written out to Kconfig.new in the + same directory as Kconfig. + + variant_name The name of the board variant, e.g. 'kohaku' + """ + # These are the part of the strings that we'll add to the sections + BOARD = 'BOARD_GOOGLE_' + variant_name.upper() + lowercase = variant_name.lower() + capitalized = lowercase.capitalize() + + # These flags track whether we're in a section where we need to add an option + in_mainboard_part_number = False + in_variant_dir = False + + inputname = 'Kconfig' + outputname = 'Kconfig.new' + with open(outputname, 'w') as outfile: + with open(inputname, 'r') as infile: + for rawline in infile: + line = rawline.rstrip('\r\n') + + # Are we in one of the sections of interest? + if line == 'config MAINBOARD_PART_NUMBER': + in_mainboard_part_number = True + if line == 'config VARIANT_DIR': + in_variant_dir = True + + # Are we at the end of a section, and if so, is it one of the + # sections of interest? + if line == '': + if in_mainboard_part_number: + print('\tdefault "' + capitalized + '" if ' + BOARD, file=outfile) + in_mainboard_part_number = False + if in_variant_dir: + print('\tdefault "' + lowercase + '" if ' + BOARD, file=outfile) + in_variant_dir = False + + print(line, file=outfile) + + +def add_to_Kconfig_name(baseboard_name, variant_name): + """Add a config section for the variant to the Kconfig.name + + Kconfig.name is easier to modify than Kconfig; it only has a block at + the end with the new variant's details. + + baseboard_name The name of the baseboard, e.g. 'hatch' + We expect the caller to have checked that it is one we support + variant_name The name of the board variant, e.g. 'kohaku' + """ + # Board name for the config section + uppercase = variant_name.upper() + capitalized = variant_name.lower().capitalize() + + inputname = 'Kconfig.name' + outputname = 'Kconfig.name.new' + with open(outputname, 'w') as outfile: + with open(inputname, 'r') as infile: + # Copy all input lines to output + for rawline in infile: + line = rawline.rstrip('\r\n') + print(line, file=outfile) + + # Now add the new section + if baseboard_name == 'hatch': + print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) + print('\tbool "-> ' + capitalized + '"', file=outfile) + print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) + print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) + + if baseboard_name == 'volteer': + print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) + print('\tbool "-> ' + capitalized + '"', file=outfile) + print('\tselect BOARD_GOOGLE_BASEBOARD_VOLTEER', file=outfile) + + +if __name__ == '__main__': + main() diff --git a/util/mainboard/google/volteer/template/Makefile.inc b/util/mainboard/google/volteer/template/Makefile.inc index 38cf728..f130808 100644 --- a/util/mainboard/google/volteer/template/Makefile.inc +++ b/util/mainboard/google/volteer/template/Makefile.inc @@ -1,5 +1,8 @@ +## ## This file is part of the coreboot project. ## +## Copyright 2020 Google LLC +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; version 2 of the License. diff --git a/util/mainboard/google/volteer/template/include/variant/ec.h b/util/mainboard/google/volteer/template/include/variant/ec.h new file mode 100644 index 0000000..5d3278f --- /dev/null +++ b/util/mainboard/google/volteer/template/include/variant/ec.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/util/mainboard/google/volteer/template/include/variant/gpio.h b/util/mainboard/google/volteer/template/include/variant/gpio.h new file mode 100644 index 0000000..ad4d68b --- /dev/null +++ b/util/mainboard/google/volteer/template/include/variant/gpio.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/util/mainboard/google/volteer/template/overridetree.cb b/util/mainboard/google/volteer/template/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/util/mainboard/google/volteer/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7 Gerrit-Change-Number: 39462 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/google/drallion: Enable GEO SAR
by EricR Lai (Code Review) 14 Mar '20

14 Mar '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39467 ) Change subject: mb/google/drallion: Enable GEO SAR ...................................................................... mb/google/drallion: Enable GEO SAR Enable GEO SAR function. BUG=b:150347463 TEST=NA Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd --- M src/mainboard/google/drallion/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/39467/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index aff19c8..431644aa 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -40,6 +40,7 @@ select SAR_ENABLE select USE_SAR select WIFI_SAR_CBFS + select GEO_SAR_ENABLE config DIMM_MAX int -- To view, visit https://review.coreboot.org/c/coreboot/+/39467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd Gerrit-Change-Number: 39467 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/google/dedede: Add WLAN configuration
by Karthik Ramasubramanian (Code Review) 14 Mar '20

14 Mar '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39115 ) Change subject: mb/google/dedede: Add WLAN configuration ...................................................................... mb/google/dedede: Add WLAN configuration Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 34 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index ea7689e..f27251d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -70,6 +70,14 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + # PCIe root port 4 hosts M.2 E-key WLAN and uses Clk Source 4. The concerned + # Clk Source maps to Clk Request 4. Note the indices are off by 1 for + # zero-indexing. + register "PcieRpEnable[3]" = "1" + register "PcieClkSrcUsage[3]" = "3" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" @@ -119,7 +127,10 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - device pci 14.3 off end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 @@ -137,7 +148,7 @@ device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 - device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.3 on end # PCI Express Root Port 4 - WLAN device pci 1c.4 off end # PCI Express Root Port 5 device pci 1c.5 off end # PCI Express Root Port 6 device pci 1c.6 off end # PCI Express Root Port 7 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0e2a168..dc90e60 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -64,8 +64,8 @@ PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_NC(GPP_B7, NONE), - /* B8 : PCIE_CLKREQ3_N */ - PAD_NC(GPP_B8, NONE), + /* B8 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ @@ -149,11 +149,11 @@ /* D0 : WWAN_HOST_WAKE */ PAD_NC(GPP_D0, NONE), /* D1 : WLAN_PERST_L */ - PAD_NC(GPP_D1, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* D2 : WLAN_INT_L */ - PAD_NC(GPP_D2, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_D2, NONE, DEEP, EDGE_SINGLE), /* D3 : WLAN_PCIE_WAKE_ODL */ - PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* D4 : TOUCH_INT_ODL */ PAD_NC(GPP_D4, NONE), /* D5 : TOUCH_RESET_L */ @@ -185,11 +185,11 @@ /* D18 : I2S_MCLK */ PAD_NC(GPP_D18, NONE), /* D19 : WWAN_WLAN_COEX1 */ - PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), /* D20 : WWAN_WLAN_COEX2 */ - PAD_NC(GPP_D20, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), /* D21 : WWAN_WLAN_COEX3 */ - PAD_NC(GPP_D21, NONE), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* D22 : AP_I2C_SUB_SDA*/ PAD_NC(GPP_D22, NONE), /* D23 : AP_I2C_SUB_SCL */ @@ -325,7 +325,7 @@ /* H17 : WWAN_RST_L */ PAD_NC(GPP_H17, NONE), /* H18 : WLAN_DISABLE_L */ - PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H18, 1, DEEP), /* H19 : BT_DISABLE_L */ PAD_NC(GPP_H19, NONE), @@ -380,7 +380,7 @@ /* GPD7 : GPP_GPD7 */ PAD_NC(GPD7, NONE), /* GPD8 : WLAN_SUSCLK */ - PAD_NC(GPD8, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 : AP_SLP_WLAN_L */ PAD_NC(GPD9, NONE), /* GPD10 : AP_SPL_S5_L */ @@ -399,6 +399,9 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* D1 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index ac9d576..f0bdb63 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,3 +1,10 @@ chip soc/intel/tigerlake - device domain 0 on end + device domain 0 on + device pci 1c.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 4 - WLAN + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/39115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Gerrit-Change-Number: 39115 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

7 37

Change in coreboot[master]: mb/google/dedede: Add BT Disable GPIO configuration
by Karthik Ramasubramanian (Code Review) 14 Mar '20

14 Mar '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39446 ) Change subject: mb/google/dedede: Add BT Disable GPIO configuration ...................................................................... mb/google/dedede: Add BT Disable GPIO configuration TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39446/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 994e96e..5a635b3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -190,6 +190,7 @@ chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" device usb 2.4 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index af95f6a..49af7fe 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -328,7 +328,7 @@ /* H18 : WLAN_DISABLE_L */ PAD_NC(GPP_H18, NONE), /* H19 : BT_DISABLE_L */ - PAD_NC(GPP_H19, NONE), + PAD_CFG_GPO(GPP_H19, 1, DEEP), /* R0 : I2S_HP_BCLK */ PAD_NC(GPP_R0, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/39446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc Gerrit-Change-Number: 39446 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/intel/tglrvp: Update GPIO setting
by Wonkyu Kim (Code Review) 14 Mar '20

14 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39476 ) Change subject: mb/intel/tglrvp: Update GPIO setting ...................................................................... mb/intel/tglrvp: Update GPIO setting Update GPIO reset type from PLTRST to DEEP. DEEP setting is more conservative for S3/S4/S5. Detail information is bug. BUG=b:151305120 TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 2 files changed, 68 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/39476/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 30d148a..3a50eb6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -20,46 +20,46 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ - PAD_CFG_GPO(GPP_B16, 1, PLTRST), - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Camera */ - PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ - PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ - PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ - PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ - PAD_CFG_GPO(GPP_B23, 0, PLTRST), - PAD_CFG_GPO(GPP_C15, 0, PLTRST), - PAD_CFG_GPO(GPP_R6, 0, PLTRST), - PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_GPO(GPP_C15, 0, DEEP), + PAD_CFG_GPO(GPP_R6, 0, DEEP), + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ - PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* ISH UART0 RX/TX */ - PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH I2C0 */ - PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* ISH GPI 0-6 */ - PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), /*Audio */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), - PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ }; @@ -87,14 +87,14 @@ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ /* DP */ - PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ - PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ - PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ - PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ - PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ - PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ - PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ - PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 2f952d2..9998419 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -20,46 +20,46 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { /* PCH M.2 SSD */ - PAD_CFG_GPO(GPP_B16, 1, PLTRST), - PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_CFG_GPO(GPP_B16, 1, DEEP), + PAD_CFG_GPO(GPP_H0, 1, DEEP), /* Camera */ - PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ - PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ - PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ - PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ - PAD_CFG_GPO(GPP_B23, 0, PLTRST), - PAD_CFG_GPO(GPP_C15, 0, PLTRST), - PAD_CFG_GPO(GPP_E22, 0, PLTRST), - PAD_CFG_GPO(GPP_H12, 0, PLTRST), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_GPO(GPP_C15, 0, DEEP), + PAD_CFG_GPO(GPP_E22, 0, DEEP), + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ - PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* ISH UART0 RX/TX */ - PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH I2C0 */ - PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* ISH GPI 0-6 */ - PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), /*Audio */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), - PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ }; @@ -88,14 +88,14 @@ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ /* DP */ - PAD_CFG_NF(GPP_L_BKLTEN, NONE, PLTRST, NF1), /* L_BKLTEN */ - PAD_CFG_NF(GPP_L_BKLTCTL, NONE, PLTRST, NF1), /* L_BKLTCTL */ - PAD_CFG_NF(GPP_L_VDDEN, NONE, PLTRST, NF1), /* L_VDDEN */ - PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), /* HPD_A */ - PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1), /* HPD_B */ - PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* HPD_1 */ - PAD_CFG_NF(GPP_E18, NONE, PLTRST, NF1), /* DDP_1_CTRCLK */ - PAD_CFG_NF(GPP_E19, NONE, PLTRST, NF1), /* DDP_1_CTRDATA */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/39476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b Gerrit-Change-Number: 39476 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: util/inteltool: add code for dumping IO registers
by Michael Niewöhner (Code Review) 14 Mar '20

14 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39524 ) Change subject: util/inteltool: add code for dumping IO registers ...................................................................... Uploaded patch set 10: Patch Set 9 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I200e7a8fb85184fc954d6ae3cd71c6b5bdcb664a Gerrit-Change-Number: 39524 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Mar 2020 23:10:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/inteltool: add code for dumping APIC registers
by Michael Niewöhner (Code Review) 14 Mar '20

14 Mar '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39523 ) Change subject: util/inteltool: add code for dumping APIC registers ...................................................................... Uploaded patch set 10: Patch Set 9 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/39523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic35e4d1dcb77ae2246197befb8cccc5af52d20e3 Gerrit-Change-Number: 39523 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Mar 2020 23:10:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2020