Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )
Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip…
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip…
PS6, Line 221: PcieRpAspm
This disabled ASPM on both my root ports. If parameters are implicitly zero-initialised, this needs to be corrected.
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Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8
Gerrit-Change-Number: 39538
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39538
to look at the new patch set (#6).
Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
......................................................................
soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
Port of CB:39412 for Skylake. Exposes PcieRpAspm and PcieRpL1Substates
to devicetree to allow boards to set these options
Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.
get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.
Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/6
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39538
to look at the new patch set (#5).
Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
......................................................................
soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
Port of CB:39412 for Skylake. Exposes PcieRpAspm and PcieRpL1Substates
to devicetree to allow boards to set these options
Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.
get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.
Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/5
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39538
to look at the new patch set (#4).
Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
......................................................................
soc/intel/skylake: Configure L1 substates for PCH root ports
Port of CB:39412 for Skylake.
Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.
get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.
Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)
Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/4
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Benjamin Doron has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39539 )
Change subject: soc/intel/skylake: add ASPM configuration for root ports
......................................................................
Abandoned
Cleaner and more logical to merge into CB:39538
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39539
to look at the new patch set (#4).
Change subject: soc/intel/skylake: add ASPM configuration for root ports
......................................................................
soc/intel/skylake: add ASPM configuration for root ports
Expose PcieRpAspm to devicetree.cb to allow boards to disable ASPM
Change-Id: I85dcf601d908d855aa9ff307b3a34bdfb50a0a86
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/39539/4
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39539 )
Change subject: soc/intel/skylake: add ASPM configuration for root ports
......................................................................
Patch Set 3:
This change is ready for review.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mainboard: Add Acer ES1-572
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig
File acer_a_thing.defconfig:
https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig@2
PS5, Line 2: CONFIG_VENDOR_ACER=y
> move file to configs/
Oh, I'm still carrying this over? I don't need it anymore
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