coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

1 participants
3326 discussions

Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by EricR Lai (Code Review) 18 Mar '20

18 Mar '20

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/39502/5/src/mainboard/google/delta… File src/mainboard/google/deltaur/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/39502/5/src/mainboard/google/delta… PS5, Line 4: SI_EC@0x1000 0x100000 > We have a separate set of patches for enabling GBE. okay 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-CC: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Comment-Date: Wed, 18 Mar 2020 17:19:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Selma Bensaid <selma.bensaid(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/tigerlake: Correct number of gpio group for Jasper Lake
by Maulik V Vaghela (Code Review) 18 Mar '20

18 Mar '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39604 ) Change subject: soc/intel/tigerlake: Correct number of gpio group for Jasper Lake ...................................................................... soc/intel/tigerlake: Correct number of gpio group for Jasper Lake Correct number of gpio pad group for Jasper Lake soc. BUG=None BRANCH=None Test=Code compilation for Jasper Lake RVP Change-Id: I381d0e48430e933569a3b22b66b4e6077383e9e2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39604/1 diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h index ce7d0d8..ded4228 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h @@ -35,7 +35,7 @@ #define GPP_GPD 0xA #define GPP_E 0xD -#define GPIO_NUM_GROUPS 11 +#define GPIO_NUM_GROUPS 12 #define GPIO_MAX_NUM_PER_GROUP 24 /* -- To view, visit https://review.coreboot.org/c/coreboot/+/39604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I381d0e48430e933569a3b22b66b4e6077383e9e2 Gerrit-Change-Number: 39604 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/common/block/lpc: Add support to allow all UART options
by Wim Vervoorn (Code Review) 18 Mar '20

18 Mar '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38748 ) Change subject: soc/intel/common/block/lpc: Add support to allow all UART options ...................................................................... soc/intel/common/block/lpc: Add support to allow all UART options The current implementation only allows 0x3f8 for COMA and 0x2f8 for COMB in the LPC decode. Add the support to allow selection of all options supported by the PCH. BUG=N/A TEST=build Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/common/block/lpc/Kconfig M src/soc/intel/common/block/lpc/lpc_def.h 2 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38748/1 diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index 41e72c4..b95e9be 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -11,3 +11,25 @@ help By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection. + +config SOC_INTEL_COMMON_BLOCK_LPC_COMA_UART + int + prompt "Index for COMA UART" + depends on SOC_INTEL_COMMON_BLOCK_LPC && DRIVERS_UART_8250IO + default 0 + range 0 7 + help + Select an I/O port for COMA (Used to open LPC IO window) + 0 = 0x3f8, 1 = 0x2f8, 2 = 0x220, 3 = 0x228, + 4 = 0x238, 5 = 0x2e8, 6 = 0x338, 7 = 0x3e8 + +config SOC_INTEL_COMMON_BLOCK_LPC_COMB_UART + int + prompt "Index for COMB UART" if DRIVERS_UART_8250IO + depends on SOC_INTEL_COMMON_BLOCK_LPC && DRIVERS_UART_8250IO && SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + default 1 + range 0 7 + help + Select an I/O port for COMB (Used to open LPC IO window) + 0 = 0x3f8, 1 = 0x2f8, 2 = 0x220, 3 = 0x228, + 4 = 0x238, 5 = 0x2e8, 6 = 0x338, 7 = 0x3e8 diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 9a72580..7af235f 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -21,8 +21,8 @@ #define LPC_SCNT_EN (1 << 7) #define LPC_SCNT_MODE (1 << 6) #define LPC_IO_DECODE 0x80 -#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/ -#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/ +#define LPC_IOD_COMA_RANGE (CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMA_UART << 0) +#define LPC_IOD_COMB_RANGE (CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_UART << 4) /* Use IO_<peripheral>_<IO port> style macros defined in lpc_lib.h * to enable decoding of I/O locations for a peripheral. */ #define LPC_IO_ENABLES 0x82 -- To view, visit https://review.coreboot.org/c/coreboot/+/38748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Gerrit-Change-Number: 38748 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
by Brandon Breitenstein (Code Review) 18 Mar '20

18 Mar '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38737 ) Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT ...................................................................... soc/tigerlake: Update FSP UPDs to turn on USB4/TBT FSP needs to know to allow the root ports for USB4/TBT to be enabled This patch may need additional checks for each board as it might not be the right thing to turn them all on for every tigerlake board. BUG=b:141609883 BRANCH=NONE TEST=Built image and verified that the root ports were visible with lspci Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..22c1b2a 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,10 @@ sizeof(params->SataPortsDevSlp)); } + /* USB4/TBT */ + for (i = 0; i < 4; i++) + params->ITbtPcieRootPortEn[i] = 1; + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index fc3155f..0d11306 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -129,6 +129,13 @@ config = config_of_soc(); soc_memory_init_params(m_cfg, config); + + /* USB4/TBT */ + m_cfg->TcssItbtPcie0En = 1; + m_cfg->TcssItbtPcie1En = 1; + m_cfg->TcssItbtPcie2En = 1; + m_cfg->TcssItbtPcie3En = 1; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Gerrit-Change-Number: 38737 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

7 20

Change in coreboot[master]: soc/mediatek/mt8183: Fix wrong setting of DRS config
by huayang duan (Code Review) 18 Mar '20

18 Mar '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39626 to review the following change. Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config ...................................................................... soc/mediatek/mt8183: Fix wrong setting of DRS config Update setting of DRS config BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39626/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index dc3676a..67ed2db 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -486,9 +486,10 @@ /* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), - (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) | + (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21), + (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) | + (0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset(); -- To view, visit https://review.coreboot.org/c/coreboot/+/39626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Gerrit-Change-Number: 39626 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/mediatek/mt8183: Improve the AC timing of DRAMC
by huayang duan (Code Review) 18 Mar '20

18 Mar '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39314 to review the following change. Change subject: soc/mediatek/mt8183: Improve the AC timing of DRAMC ...................................................................... soc/mediatek/mt8183: Improve the AC timing of DRAMC 1. Set more AC timing items to make the system more stable. 2. Fix wrong setting of DRS config. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ibd003582a3ffab1ae91f6378651c2c9e585c4676 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/emi.c 2 files changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/39314/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 4033a91..89321a4 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -484,9 +484,10 @@ /* DRAM DRS DISABLE */ clrsetbits32(&ch[chn].ao.drsctrl, - (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), - (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | - (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); + (0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) | + (0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21), + (0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) | + (0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21)); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } dramc_dqs_precalculation_preset(); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 2310b5e..4a8f618 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -64,6 +64,8 @@ struct optimize_ac_time { u8 rfc; u8 rfc_05t; + u8 rfc_pb; + u8 rfrc_pb05t; u16 tx_ref_cnt; }; @@ -336,19 +338,27 @@ static void dramc_ac_timing_optimize(u8 freq_group) { struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = { - [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62}, - [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91}, - [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119}, - [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138}, + [LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16, + .rfrc_pb05t = 0, .tx_ref_cnt = 62}, + [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30, + .rfrc_pb05t = 0, .tx_ref_cnt = 91}, + [LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44, + .rfrc_pb05t = 0, .tx_ref_cnt = 119}, + [LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53, + .rfrc_pb05t = 1, .tx_ref_cnt = 138}, }; for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { clrsetbits32(&ch[chn].ao.shu[0].actim[3], 0xff << 16, rf_cab_opt[freq_group].rfc << 16); - clrbits32(&ch[chn].ao.shu[0].ac_time_05t, - rf_cab_opt[freq_group].rfc_05t << 2); - clrsetbits32(&ch[chn].ao.shu[0].actim[4], + clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + 0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + 0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0); + clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + 0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd003582a3ffab1ae91f6378651c2c9e585c4676 Gerrit-Change-Number: 39314 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: src/mainboard/g/octopus: Enables GMM in the devicetree for octopus
by Franklin (Yanjin) He (Code Review) 18 Mar '20

18 Mar '20

Franklin (Yanjin) He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39600 ) Change subject: src/mainboard/g/octopus: Enables GMM in the devicetree for octopus ...................................................................... src/mainboard/g/octopus: Enables GMM in the devicetree for octopus As title suggests, adds GMM to the device tree for octopus devices Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd Signed-off-by: Franklin He <franklinh(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39600/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 8f85070..9f64a1e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -112,6 +112,7 @@ device pci 00.2 off end # - NPK device pci 02.0 on end # - Gen device pci 03.0 on end # - Iunit + device pci 08.0 on end # - Gaussian Mixture Model (GMM) chip drivers/intel/wifi register "wake" = "GPE0A_CNVI_PME_STS" device pci 0c.0 on end # - CNVi -- To view, visit https://review.coreboot.org/c/coreboot/+/39600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd Gerrit-Change-Number: 39600 Gerrit-PatchSet: 1 Gerrit-Owner: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake
by Patrick Georgi (Code Review) 18 Mar '20

18 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39579 ) Change subject: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake ...................................................................... soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake Enables Gaussian Mixture Model (GMM) if the pci device is enabled in the devicetree for Gemini Lake This ports commit 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b BUG=b:151115705 BRANCH=none TEST=Flashed to Chromebook, PCI device enabled in cbmem, userspace app that uses device still works Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Signed-off-by: Franklin He <franklinh(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39579 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h 2 files changed, 7 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 178ccac..5a65260 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -612,6 +612,7 @@ { #if CONFIG(SOC_INTEL_GLK) uint8_t port; + struct device *dev; for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { if (!cfg->usb2eye[port].Usb20OverrideEn) @@ -627,7 +628,8 @@ cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; } - silconfig->Gmm = 0; + dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM); + silconfig->Gmm = dev ? dev->enabled : 0; /* On Geminilake, we need to override the default FSP PCIe de-emphasis * settings using the device tree settings. This is because PCIe diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 6544b7a..12a4e8d 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -46,6 +46,10 @@ #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) #define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_GLK_DEV_SLOT_GMM 0x03 +#define SA_GLK_DEVFN_GMM PCI_DEVFN(SA_GLK_DEV_SLOT_GMM, 0) +#define SA_GLK_DEV_GMM PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_NPK 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/39579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Gerrit-Change-Number: 39579 Gerrit-PatchSet: 5 Gerrit-Owner: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/dedede: Add support for integrated BT enumeration
by Aamir Bohra (Code Review) 18 Mar '20

18 Mar '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39471 ) Change subject: mb/google/dedede: Add support for integrated BT enumeration ...................................................................... mb/google/dedede: Add support for integrated BT enumeration The integrated BT is routed via USB2 port8, add USB configuration to support integrated BT enumeration. Change-Id: I46d8c92ba57cd72a91ee15ef4d11f07824c29e9a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39471/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 994e96e..4cd2400 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -31,10 +31,10 @@ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used - register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 @@ -188,11 +188,16 @@ device usb 2.3 on end end chip drivers/usb/acpi - register "desc" = ""Bluetooth"" + register "desc" = ""Discrete Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.4 on end end chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 1)" -- To view, visit https://review.coreboot.org/c/coreboot/+/39471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46d8c92ba57cd72a91ee15ef4d11f07824c29e9a Gerrit-Change-Number: 39471 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/autoport: Correct formatting issues
by Angel Pons (Code Review) 18 Mar '20

18 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38901 ) Change subject: util/autoport: Correct formatting issues ...................................................................... util/autoport: Correct formatting issues There is no need to use hexadecimal values in azalia codec IDs, nor need to print a redundant "LPC bridge PCI-LPC bridge" comment. Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/azalia.go M util/autoport/bd82x6x.go 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38901/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index d94441b..c98b03c 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -26,7 +26,7 @@ codec.SubsystemID) fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n", len(codec.PinConfig)+1) - fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(%d, 0x%08x),\n", codec.CodecNo, codec.SubsystemID) keys := []int{} @@ -37,7 +37,7 @@ sort.Ints(keys) for _, nid := range keys { - fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(%d, 0x%02x, 0x%08x),\n", codec.CodecNo, nid, codec.PinConfig[nid]) } az.WriteString("\n"); diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 3ad212b..87e7584 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -277,7 +277,7 @@ } PutPCIChip(addr, cur) - PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + PutPCIDevParent(addr, "", "lpc") DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/common/acpi/platform.asl", -- To view, visit https://review.coreboot.org/c/coreboot/+/38901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Gerrit-Change-Number: 38901 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2020