coreboot-gerrit February 2020

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Change in coreboot[master]: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35821 ) Change subject: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table ...................................................................... [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table There is no explicit dependency on an option table since the reboot counter and the normal/fallback byte is at a fixed offset. I don't feel strongly about imposing this... Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35821/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 502e774..9d26692 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -255,6 +255,7 @@ bool "Always load fallback" config BOOTBLOCK_NORMAL + depends on USE_OPTION_TABLE select CONFIGURABLE_CBFS_PREFIX bool "Switch to normal if CMOS says so" -- To view, visit https://review.coreboot.org/c/coreboot/+/35821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Gerrit-Change-Number: 35821 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35823 ) Change subject: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes ...................................................................... [RFC]arch/x86: Only allow normal and fallback cbfs prefixes Using other cbfsprefixes is errorprone: It requires a properly formatted cbfs file to be present (an error in the cbfsfile will render the system unbootable) and to correctly enter the cbfs prefix in menuconfig. Therefore remove this functionality that merely allows to use different names. Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/bootblock_normal.c 2 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35823/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..5b2a615 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -48,13 +48,10 @@ config CBFS_PREFIX_NORMAL bool "normal" -config CBFS_PREFIX_DIY - bool "Define your own cbfs prefix" - endchoice config CBFS_PREFIX - string "CBFS prefix to use" if CBFS_PREFIX_DIY + string default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK default "normal" if CBFS_PREFIX_NORMAL help diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 905ecb2..c55eda2 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -16,18 +16,9 @@ #include <pc80/mc146818rtc.h> #include <halt.h> -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - static void main(unsigned long bist) { u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; if (boot_cpu()) { bootblock_mainboard_init(); @@ -44,20 +35,15 @@ boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - unsigned long entry; if (boot_mode) { - entry = findstage(normal_candidate); + entry = findstage("normal/romstage"); if (entry) call(entry, bist); } - entry = findstage(get_fallback(normal_candidate)); + entry = findstage("fallback/romstage"); if (entry) call(entry, bist); -- To view, visit https://review.coreboot.org/c/coreboot/+/35823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Gerrit-Change-Number: 35823 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]Makefile.inc: Add Macro to generate cbfs int files
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33353 Change subject: [WIP]Makefile.inc: Add Macro to generate cbfs int files ...................................................................... [WIP]Makefile.inc: Add Macro to generate cbfs int files Add the makefile function 'add-cbfs-int' to generate cbfs files containing a little endian integer. Adding cbfs files containing a 64 bit is usually done with cbfstool add-int, but this requires the coreboot.rom image to be already build which clutters the Makefile. Instead add a method to cleanly generate the cbfsfile containing a 64bit little endian int which integrates better with the rest of the makefile. Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33353/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..d0f47e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -788,6 +788,20 @@ $(call cbfs-add-cmd-for-region,$(1),$(2)) endef +# add-cbfs-int (little endian) +# $(call add-cbfs-int, +# integer +# cbfs-file-name) +define add-cbfs-int + $(eval tmp_int:=$(shell mktemp -u int_file.XXXX)) + $(eval $(obj)/$(tmp_int): + echo -n -e $$$$(printf "%016x" $$$$(($(1))) \ + | sed -re "s/(..)(..)(..)(..)(..)(..)(..)(..)/\\\x\8\\\x\7\\\x\6\\\x\5\\\x\4\\\x\3\\\x\2\\\x\1/") > $$@) + cbfs-files-y += $(2) + $(2)-file := $(obj)/$(tmp_int) + $(2)-type := raw +endef + # list of files to add (using their file system names, not CBFS names), # for dependencies etc. prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) @@ -1064,18 +1078,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efa..24eeba6 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -110,6 +110,18 @@ bootorder-type := raw endif +# Add SeaBIOS PS2 timeout file +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_PS2_TIMEOUT),etc/ps2-keyboard-spinup)) +endif +endif + +# Add SeaBIOS Sercon port file +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_SERCON_PORT_ADDR),etc/sercon-port)) +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/33353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Gerrit-Change-Number: 33353 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
by Arthur Heymans (Code Review) 13 Apr '22

13 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 ) Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage ...................................................................... [TESTONLY]nb/intel/x4x: Cache cbmem in romstage Probably not a good idea to avoid eviction in romstage. TESTED: works fine on P5QL-EM. Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/raminit.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e24..6665eb0 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -27,6 +27,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8013af9..e8729fb 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -33,6 +33,7 @@ #include <mrc_cache.h> #include <timestamp.h> #include <types.h> +#include <cpu/x86/mtrr.h> #include "iomap.h" #include "x4x.h" @@ -718,6 +719,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); if (!fast_boot) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, -- To view, visit https://review.coreboot.org/c/coreboot/+/37213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6 Gerrit-Change-Number: 37213 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 ) Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/nehalem: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@ udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume); if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/sandybridge: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@ report_memory_config(); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); } + setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM
by Arthur Heymans (Code Review) 12 Apr '22

12 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37198 ) Change subject: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM ...................................................................... nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM AGESA sets up MTRR's to cache the whole dram, so decompressing postcar stage to cbmem should be fast and is now selected by default. Change-Id: I62ffe1bd646e9ddad77be240f030601790f4da4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/37198/1 diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 173714f..cfafb23 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index a0841eb..e6a469f 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 2be2fd3..e34ef60 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -15,6 +15,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB -- To view, visit https://review.coreboot.org/c/coreboot/+/37198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62ffe1bd646e9ddad77be240f030601790f4da4b Gerrit-Change-Number: 37198 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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